1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
2 # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 -run-pass=register-coalescer -verify-coalescing -o - %s | FileCheck %s
4 # Make sure coalescing doesn't produce "no live segment at def" when
5 # there is a live out implicit_def with subranges.
7 # %1 will be coalesced into %0. %0 is a cross block implicit_def that
8 # cannot be deleted. The def of %0 in %bb.2 is a live out subregister
9 # def of the same register. We need to ensure that the resulting
10 # subrange for %0.sub0 includes the def in %bb.1
13 name: liveout_implicit_def_super_reg_redefine_sub0_implicit_def
14 tracksRegLiveness: true
16 ; CHECK-LABEL: name: liveout_implicit_def_super_reg_redefine_sub0_implicit_def
18 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
20 ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.2, implicit undef $scc
23 ; CHECK-NEXT: successors: %bb.3(0x80000000)
25 ; CHECK-NEXT: undef %0.sub0:sgpr_128 = S_MOV_B32 0
26 ; CHECK-NEXT: S_BRANCH %bb.3
29 ; CHECK-NEXT: successors: %bb.3(0x80000000)
31 ; CHECK-NEXT: undef %0.sub0:sgpr_128 = IMPLICIT_DEF
34 ; CHECK-NEXT: S_NOP 0, implicit %0
35 ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
36 ; CHECK-NEXT: S_ENDPGM 0
38 S_CBRANCH_SCC0 %bb.2, implicit undef $scc
41 %0:sgpr_128 = IMPLICIT_DEF
42 %1:sgpr_32 = S_MOV_B32 0
46 undef %0.sub0:sgpr_128 = IMPLICIT_DEF
47 %1:sgpr_32 = COPY %0.sub0
57 # Redef of sub0 is a meaningful value.
59 name: liveout_implicit_def_redefine_sub0_undef_other
60 tracksRegLiveness: true
62 ; CHECK-LABEL: name: liveout_implicit_def_redefine_sub0_undef_other
64 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
66 ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.2, implicit undef $scc
69 ; CHECK-NEXT: successors: %bb.3(0x80000000)
71 ; CHECK-NEXT: undef %0.sub0:sgpr_128 = S_MOV_B32 0
72 ; CHECK-NEXT: S_BRANCH %bb.3
75 ; CHECK-NEXT: successors: %bb.3(0x80000000)
77 ; CHECK-NEXT: undef %0.sub0:sgpr_128 = S_MOV_B32 9
80 ; CHECK-NEXT: S_NOP 0, implicit %0
81 ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
82 ; CHECK-NEXT: S_ENDPGM 0
84 S_CBRANCH_SCC0 %bb.2, implicit undef $scc
87 %0:sgpr_128 = IMPLICIT_DEF
88 %1:sgpr_32 = S_MOV_B32 0
92 undef %0.sub0:sgpr_128 = S_MOV_B32 9
93 %1:sgpr_32 = COPY %0.sub0
102 # The initial def of the register doesn't doesn't cover the redefined
103 # lanes. This had no error but was useful to compare against the
106 name: only_redefine_undefined_lanes
107 tracksRegLiveness: true
109 ; CHECK-LABEL: name: only_redefine_undefined_lanes
111 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
113 ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.2, implicit undef $scc
116 ; CHECK-NEXT: successors: %bb.3(0x80000000)
118 ; CHECK-NEXT: S_NOP 0, implicit-def undef %0.sub1_sub2_sub3
119 ; CHECK-NEXT: %0.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
120 ; CHECK-NEXT: S_BRANCH %bb.3
123 ; CHECK-NEXT: successors: %bb.3(0x80000000)
125 ; CHECK-NEXT: undef %0.sub0:vreg_128 = V_MOV_B32_e32 9, implicit $exec
128 ; CHECK-NEXT: S_NOP 0, implicit %0
129 ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
130 ; CHECK-NEXT: S_ENDPGM 0
132 S_CBRANCH_SCC0 %bb.2, implicit undef $scc
135 S_NOP 0, implicit-def undef %0.sub1_sub2_sub3:vreg_128
136 %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
140 undef %0.sub0:vreg_128 = V_MOV_B32_e32 9, implicit $exec
141 %1:vgpr_32 = COPY %0.sub0