| blob | 7a492f51cce49f448634d5df29cf7be0f455ad70 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr="+wavefrontsize32" -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX11,SDAG-GFX11 %s
3 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr="+wavefrontsize32" -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,SDAG-GFX10 %s
5 ; RUN: llc -global-isel -global-isel-abort=2 -march=amdgcn -mcpu=gfx1100 -mattr="+wavefrontsize32" -verify-machineinstrs < %s 2>%t | FileCheck -check-prefixes=GCN,GFX11,GISEL-GFX11 %s
6 ; RUN: FileCheck --check-prefix=ERR %s < %t
7 ; RUN: llc -global-isel -global-isel-abort=2 -march=amdgcn -mcpu=gfx1010 -mattr="+wavefrontsize32" -verify-machineinstrs < %s 2>%t | FileCheck -check-prefixes=GCN,GFX10,GISEL-GFX10 %s
8 ; RUN: FileCheck --check-prefix=ERR %s < %t
10 ; Note: GlobalISel abort is disabled so we don't crash on i1 inputs.
11 ; They are allowed in DAGISel but we (intentionally) don't support them
12 ; in GlobalISel.
14 ; ERR: warning: Instruction selection used fallback path for v_icmp_i1_ne0
16 declare i32 @llvm.amdgcn.icmp.i32(i32, i32, i32) #0
17 declare i32 @llvm.amdgcn.icmp.i64(i64, i64, i32) #0
18 declare i32 @llvm.amdgcn.icmp.i16(i16, i16, i32) #0
19 declare i32 @llvm.amdgcn.icmp.i1(i1, i1, i32) #0
21 define amdgpu_kernel void @v_icmp_i32_eq(ptr addrspace(1) %out, i32 %src) {
22 ; SDAG-GFX11-LABEL: v_icmp_i32_eq:
23 ; SDAG-GFX11: ; %bb.0:
24 ; SDAG-GFX11-NEXT: s_clause 0x1
25 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
26 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
27 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
28 ; SDAG-GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0x64, s2
29 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
30 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
31 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
32 ; SDAG-GFX11-NEXT: s_nop 0
33 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
34 ; SDAG-GFX11-NEXT: s_endpgm
35 ;
36 ; SDAG-GFX10-LABEL: v_icmp_i32_eq:
37 ; SDAG-GFX10: ; %bb.0:
38 ; SDAG-GFX10-NEXT: s_clause 0x1
39 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
40 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
41 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
42 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
43 ; SDAG-GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0x64, s4
44 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
45 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
46 ; SDAG-GFX10-NEXT: s_endpgm
47 ;
48 ; GISEL-GFX11-LABEL: v_icmp_i32_eq:
49 ; GISEL-GFX11: ; %bb.0:
50 ; GISEL-GFX11-NEXT: s_clause 0x1
51 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
52 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
53 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
54 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
55 ; GISEL-GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0x64, s2
56 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
57 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
58 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
59 ; GISEL-GFX11-NEXT: s_nop 0
60 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
61 ; GISEL-GFX11-NEXT: s_endpgm
62 ;
63 ; GISEL-GFX10-LABEL: v_icmp_i32_eq:
64 ; GISEL-GFX10: ; %bb.0:
65 ; GISEL-GFX10-NEXT: s_clause 0x1
66 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
67 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
68 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
69 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
70 ; GISEL-GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0x64, s4
71 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
72 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
73 ; GISEL-GFX10-NEXT: s_endpgm
74 %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 32)
75 store i32 %result, ptr addrspace(1) %out
76 ret void
77 }
79 define amdgpu_kernel void @v_icmp_i32(ptr addrspace(1) %out, i32 %src) {
80 ; SDAG-GFX11-LABEL: v_icmp_i32:
81 ; SDAG-GFX11: ; %bb.0:
82 ; SDAG-GFX11-NEXT: s_endpgm
83 ;
84 ; SDAG-GFX10-LABEL: v_icmp_i32:
85 ; SDAG-GFX10: ; %bb.0:
86 ; SDAG-GFX10-NEXT: s_endpgm
87 ;
88 ; GISEL-GFX11-LABEL: v_icmp_i32:
89 ; GISEL-GFX11: ; %bb.0:
90 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
91 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, 0
92 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
93 ; GISEL-GFX11-NEXT: global_store_b32 v0, v0, s[0:1]
94 ; GISEL-GFX11-NEXT: s_nop 0
95 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
96 ; GISEL-GFX11-NEXT: s_endpgm
97 ;
98 ; GISEL-GFX10-LABEL: v_icmp_i32:
99 ; GISEL-GFX10: ; %bb.0:
100 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
101 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, 0
102 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
103 ; GISEL-GFX10-NEXT: global_store_dword v0, v0, s[0:1]
104 ; GISEL-GFX10-NEXT: s_endpgm
105 %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 30)
106 store i32 %result, ptr addrspace(1) %out
107 ret void
108 }
110 define amdgpu_kernel void @v_icmp_i32_ne(ptr addrspace(1) %out, i32 %src) {
111 ; SDAG-GFX11-LABEL: v_icmp_i32_ne:
112 ; SDAG-GFX11: ; %bb.0:
113 ; SDAG-GFX11-NEXT: s_clause 0x1
114 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
115 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
116 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
117 ; SDAG-GFX11-NEXT: v_cmp_ne_u32_e64 s2, 0x64, s2
118 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
119 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
120 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
121 ; SDAG-GFX11-NEXT: s_nop 0
122 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
123 ; SDAG-GFX11-NEXT: s_endpgm
124 ;
125 ; SDAG-GFX10-LABEL: v_icmp_i32_ne:
126 ; SDAG-GFX10: ; %bb.0:
127 ; SDAG-GFX10-NEXT: s_clause 0x1
128 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
129 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
130 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
131 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
132 ; SDAG-GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0x64, s4
133 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
134 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
135 ; SDAG-GFX10-NEXT: s_endpgm
136 ;
137 ; GISEL-GFX11-LABEL: v_icmp_i32_ne:
138 ; GISEL-GFX11: ; %bb.0:
139 ; GISEL-GFX11-NEXT: s_clause 0x1
140 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
141 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
142 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
143 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
144 ; GISEL-GFX11-NEXT: v_cmp_ne_u32_e64 s2, 0x64, s2
145 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
146 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
147 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
148 ; GISEL-GFX11-NEXT: s_nop 0
149 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
150 ; GISEL-GFX11-NEXT: s_endpgm
151 ;
152 ; GISEL-GFX10-LABEL: v_icmp_i32_ne:
153 ; GISEL-GFX10: ; %bb.0:
154 ; GISEL-GFX10-NEXT: s_clause 0x1
155 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
156 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
157 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
158 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
159 ; GISEL-GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0x64, s4
160 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
161 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
162 ; GISEL-GFX10-NEXT: s_endpgm
163 %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 33)
164 store i32 %result, ptr addrspace(1) %out
165 ret void
166 }
168 define amdgpu_kernel void @v_icmp_i32_ugt(ptr addrspace(1) %out, i32 %src) {
169 ; SDAG-GFX11-LABEL: v_icmp_i32_ugt:
170 ; SDAG-GFX11: ; %bb.0:
171 ; SDAG-GFX11-NEXT: s_clause 0x1
172 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
173 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
174 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
175 ; SDAG-GFX11-NEXT: v_cmp_lt_u32_e64 s2, 0x64, s2
176 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
177 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
178 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
179 ; SDAG-GFX11-NEXT: s_nop 0
180 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
181 ; SDAG-GFX11-NEXT: s_endpgm
182 ;
183 ; SDAG-GFX10-LABEL: v_icmp_i32_ugt:
184 ; SDAG-GFX10: ; %bb.0:
185 ; SDAG-GFX10-NEXT: s_clause 0x1
186 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
187 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
188 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
189 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
190 ; SDAG-GFX10-NEXT: v_cmp_lt_u32_e64 s0, 0x64, s4
191 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
192 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
193 ; SDAG-GFX10-NEXT: s_endpgm
194 ;
195 ; GISEL-GFX11-LABEL: v_icmp_i32_ugt:
196 ; GISEL-GFX11: ; %bb.0:
197 ; GISEL-GFX11-NEXT: s_clause 0x1
198 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
199 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
200 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
201 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
202 ; GISEL-GFX11-NEXT: v_cmp_lt_u32_e64 s2, 0x64, s2
203 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
204 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
205 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
206 ; GISEL-GFX11-NEXT: s_nop 0
207 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
208 ; GISEL-GFX11-NEXT: s_endpgm
209 ;
210 ; GISEL-GFX10-LABEL: v_icmp_i32_ugt:
211 ; GISEL-GFX10: ; %bb.0:
212 ; GISEL-GFX10-NEXT: s_clause 0x1
213 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
214 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
215 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
216 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
217 ; GISEL-GFX10-NEXT: v_cmp_lt_u32_e64 s0, 0x64, s4
218 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
219 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
220 ; GISEL-GFX10-NEXT: s_endpgm
221 %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 34)
222 store i32 %result, ptr addrspace(1) %out
223 ret void
224 }
226 define amdgpu_kernel void @v_icmp_i32_uge(ptr addrspace(1) %out, i32 %src) {
227 ; SDAG-GFX11-LABEL: v_icmp_i32_uge:
228 ; SDAG-GFX11: ; %bb.0:
229 ; SDAG-GFX11-NEXT: s_clause 0x1
230 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
231 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
232 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
233 ; SDAG-GFX11-NEXT: v_cmp_le_u32_e64 s2, 0x64, s2
234 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
235 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
236 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
237 ; SDAG-GFX11-NEXT: s_nop 0
238 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
239 ; SDAG-GFX11-NEXT: s_endpgm
240 ;
241 ; SDAG-GFX10-LABEL: v_icmp_i32_uge:
242 ; SDAG-GFX10: ; %bb.0:
243 ; SDAG-GFX10-NEXT: s_clause 0x1
244 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
245 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
246 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
247 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
248 ; SDAG-GFX10-NEXT: v_cmp_le_u32_e64 s0, 0x64, s4
249 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
250 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
251 ; SDAG-GFX10-NEXT: s_endpgm
252 ;
253 ; GISEL-GFX11-LABEL: v_icmp_i32_uge:
254 ; GISEL-GFX11: ; %bb.0:
255 ; GISEL-GFX11-NEXT: s_clause 0x1
256 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
257 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
258 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
259 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
260 ; GISEL-GFX11-NEXT: v_cmp_le_u32_e64 s2, 0x64, s2
261 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
262 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
263 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
264 ; GISEL-GFX11-NEXT: s_nop 0
265 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
266 ; GISEL-GFX11-NEXT: s_endpgm
267 ;
268 ; GISEL-GFX10-LABEL: v_icmp_i32_uge:
269 ; GISEL-GFX10: ; %bb.0:
270 ; GISEL-GFX10-NEXT: s_clause 0x1
271 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
272 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
273 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
274 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
275 ; GISEL-GFX10-NEXT: v_cmp_le_u32_e64 s0, 0x64, s4
276 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
277 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
278 ; GISEL-GFX10-NEXT: s_endpgm
279 %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 35)
280 store i32 %result, ptr addrspace(1) %out
281 ret void
282 }
284 define amdgpu_kernel void @v_icmp_i32_ult(ptr addrspace(1) %out, i32 %src) {
285 ; SDAG-GFX11-LABEL: v_icmp_i32_ult:
286 ; SDAG-GFX11: ; %bb.0:
287 ; SDAG-GFX11-NEXT: s_clause 0x1
288 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
289 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
290 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
291 ; SDAG-GFX11-NEXT: v_cmp_gt_u32_e64 s2, 0x64, s2
292 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
293 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
294 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
295 ; SDAG-GFX11-NEXT: s_nop 0
296 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
297 ; SDAG-GFX11-NEXT: s_endpgm
298 ;
299 ; SDAG-GFX10-LABEL: v_icmp_i32_ult:
300 ; SDAG-GFX10: ; %bb.0:
301 ; SDAG-GFX10-NEXT: s_clause 0x1
302 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
303 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
304 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
305 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
306 ; SDAG-GFX10-NEXT: v_cmp_gt_u32_e64 s0, 0x64, s4
307 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
308 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
309 ; SDAG-GFX10-NEXT: s_endpgm
310 ;
311 ; GISEL-GFX11-LABEL: v_icmp_i32_ult:
312 ; GISEL-GFX11: ; %bb.0:
313 ; GISEL-GFX11-NEXT: s_clause 0x1
314 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
315 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
316 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
317 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
318 ; GISEL-GFX11-NEXT: v_cmp_gt_u32_e64 s2, 0x64, s2
319 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
320 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
321 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
322 ; GISEL-GFX11-NEXT: s_nop 0
323 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
324 ; GISEL-GFX11-NEXT: s_endpgm
325 ;
326 ; GISEL-GFX10-LABEL: v_icmp_i32_ult:
327 ; GISEL-GFX10: ; %bb.0:
328 ; GISEL-GFX10-NEXT: s_clause 0x1
329 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
330 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
331 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
332 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
333 ; GISEL-GFX10-NEXT: v_cmp_gt_u32_e64 s0, 0x64, s4
334 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
335 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
336 ; GISEL-GFX10-NEXT: s_endpgm
337 %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 36)
338 store i32 %result, ptr addrspace(1) %out
339 ret void
340 }
342 define amdgpu_kernel void @v_icmp_i32_ule(ptr addrspace(1) %out, i32 %src) {
343 ; SDAG-GFX11-LABEL: v_icmp_i32_ule:
344 ; SDAG-GFX11: ; %bb.0:
345 ; SDAG-GFX11-NEXT: s_clause 0x1
346 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
347 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
348 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
349 ; SDAG-GFX11-NEXT: v_cmp_ge_u32_e64 s2, 0x64, s2
350 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
351 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
352 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
353 ; SDAG-GFX11-NEXT: s_nop 0
354 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
355 ; SDAG-GFX11-NEXT: s_endpgm
356 ;
357 ; SDAG-GFX10-LABEL: v_icmp_i32_ule:
358 ; SDAG-GFX10: ; %bb.0:
359 ; SDAG-GFX10-NEXT: s_clause 0x1
360 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
361 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
362 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
363 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
364 ; SDAG-GFX10-NEXT: v_cmp_ge_u32_e64 s0, 0x64, s4
365 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
366 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
367 ; SDAG-GFX10-NEXT: s_endpgm
368 ;
369 ; GISEL-GFX11-LABEL: v_icmp_i32_ule:
370 ; GISEL-GFX11: ; %bb.0:
371 ; GISEL-GFX11-NEXT: s_clause 0x1
372 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
373 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
374 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
375 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
376 ; GISEL-GFX11-NEXT: v_cmp_ge_u32_e64 s2, 0x64, s2
377 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
378 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
379 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
380 ; GISEL-GFX11-NEXT: s_nop 0
381 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
382 ; GISEL-GFX11-NEXT: s_endpgm
383 ;
384 ; GISEL-GFX10-LABEL: v_icmp_i32_ule:
385 ; GISEL-GFX10: ; %bb.0:
386 ; GISEL-GFX10-NEXT: s_clause 0x1
387 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
388 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
389 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
390 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
391 ; GISEL-GFX10-NEXT: v_cmp_ge_u32_e64 s0, 0x64, s4
392 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
393 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
394 ; GISEL-GFX10-NEXT: s_endpgm
395 %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 37)
396 store i32 %result, ptr addrspace(1) %out
397 ret void
398 }
400 define amdgpu_kernel void @v_icmp_i32_sgt(ptr addrspace(1) %out, i32 %src) #1 {
401 ; SDAG-GFX11-LABEL: v_icmp_i32_sgt:
402 ; SDAG-GFX11: ; %bb.0:
403 ; SDAG-GFX11-NEXT: s_clause 0x1
404 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
405 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
406 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
407 ; SDAG-GFX11-NEXT: v_cmp_lt_i32_e64 s2, 0x64, s2
408 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
409 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
410 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
411 ; SDAG-GFX11-NEXT: s_nop 0
412 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
413 ; SDAG-GFX11-NEXT: s_endpgm
414 ;
415 ; SDAG-GFX10-LABEL: v_icmp_i32_sgt:
416 ; SDAG-GFX10: ; %bb.0:
417 ; SDAG-GFX10-NEXT: s_clause 0x1
418 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
419 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
420 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
421 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
422 ; SDAG-GFX10-NEXT: v_cmp_lt_i32_e64 s0, 0x64, s4
423 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
424 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
425 ; SDAG-GFX10-NEXT: s_endpgm
426 ;
427 ; GISEL-GFX11-LABEL: v_icmp_i32_sgt:
428 ; GISEL-GFX11: ; %bb.0:
429 ; GISEL-GFX11-NEXT: s_clause 0x1
430 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
431 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
432 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
433 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
434 ; GISEL-GFX11-NEXT: v_cmp_lt_i32_e64 s2, 0x64, s2
435 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
436 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
437 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
438 ; GISEL-GFX11-NEXT: s_nop 0
439 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
440 ; GISEL-GFX11-NEXT: s_endpgm
441 ;
442 ; GISEL-GFX10-LABEL: v_icmp_i32_sgt:
443 ; GISEL-GFX10: ; %bb.0:
444 ; GISEL-GFX10-NEXT: s_clause 0x1
445 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
446 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
447 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
448 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
449 ; GISEL-GFX10-NEXT: v_cmp_lt_i32_e64 s0, 0x64, s4
450 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
451 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
452 ; GISEL-GFX10-NEXT: s_endpgm
453 %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 38)
454 store i32 %result, ptr addrspace(1) %out
455 ret void
456 }
458 define amdgpu_kernel void @v_icmp_i32_sge(ptr addrspace(1) %out, i32 %src) {
459 ; SDAG-GFX11-LABEL: v_icmp_i32_sge:
460 ; SDAG-GFX11: ; %bb.0:
461 ; SDAG-GFX11-NEXT: s_clause 0x1
462 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
463 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
464 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
465 ; SDAG-GFX11-NEXT: v_cmp_le_i32_e64 s2, 0x64, s2
466 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
467 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
468 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
469 ; SDAG-GFX11-NEXT: s_nop 0
470 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
471 ; SDAG-GFX11-NEXT: s_endpgm
472 ;
473 ; SDAG-GFX10-LABEL: v_icmp_i32_sge:
474 ; SDAG-GFX10: ; %bb.0:
475 ; SDAG-GFX10-NEXT: s_clause 0x1
476 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
477 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
478 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
479 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
480 ; SDAG-GFX10-NEXT: v_cmp_le_i32_e64 s0, 0x64, s4
481 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
482 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
483 ; SDAG-GFX10-NEXT: s_endpgm
484 ;
485 ; GISEL-GFX11-LABEL: v_icmp_i32_sge:
486 ; GISEL-GFX11: ; %bb.0:
487 ; GISEL-GFX11-NEXT: s_clause 0x1
488 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
489 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
490 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
491 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
492 ; GISEL-GFX11-NEXT: v_cmp_le_i32_e64 s2, 0x64, s2
493 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
494 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
495 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
496 ; GISEL-GFX11-NEXT: s_nop 0
497 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
498 ; GISEL-GFX11-NEXT: s_endpgm
499 ;
500 ; GISEL-GFX10-LABEL: v_icmp_i32_sge:
501 ; GISEL-GFX10: ; %bb.0:
502 ; GISEL-GFX10-NEXT: s_clause 0x1
503 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
504 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
505 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
506 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
507 ; GISEL-GFX10-NEXT: v_cmp_le_i32_e64 s0, 0x64, s4
508 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
509 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
510 ; GISEL-GFX10-NEXT: s_endpgm
511 %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 39)
512 store i32 %result, ptr addrspace(1) %out
513 ret void
514 }
516 define amdgpu_kernel void @v_icmp_i32_slt(ptr addrspace(1) %out, i32 %src) {
517 ; SDAG-GFX11-LABEL: v_icmp_i32_slt:
518 ; SDAG-GFX11: ; %bb.0:
519 ; SDAG-GFX11-NEXT: s_clause 0x1
520 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
521 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
522 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
523 ; SDAG-GFX11-NEXT: v_cmp_gt_i32_e64 s2, 0x64, s2
524 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
525 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
526 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
527 ; SDAG-GFX11-NEXT: s_nop 0
528 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
529 ; SDAG-GFX11-NEXT: s_endpgm
530 ;
531 ; SDAG-GFX10-LABEL: v_icmp_i32_slt:
532 ; SDAG-GFX10: ; %bb.0:
533 ; SDAG-GFX10-NEXT: s_clause 0x1
534 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
535 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
536 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
537 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
538 ; SDAG-GFX10-NEXT: v_cmp_gt_i32_e64 s0, 0x64, s4
539 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
540 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
541 ; SDAG-GFX10-NEXT: s_endpgm
542 ;
543 ; GISEL-GFX11-LABEL: v_icmp_i32_slt:
544 ; GISEL-GFX11: ; %bb.0:
545 ; GISEL-GFX11-NEXT: s_clause 0x1
546 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
547 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
548 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
549 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
550 ; GISEL-GFX11-NEXT: v_cmp_gt_i32_e64 s2, 0x64, s2
551 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
552 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
553 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
554 ; GISEL-GFX11-NEXT: s_nop 0
555 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
556 ; GISEL-GFX11-NEXT: s_endpgm
557 ;
558 ; GISEL-GFX10-LABEL: v_icmp_i32_slt:
559 ; GISEL-GFX10: ; %bb.0:
560 ; GISEL-GFX10-NEXT: s_clause 0x1
561 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
562 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
563 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
564 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
565 ; GISEL-GFX10-NEXT: v_cmp_gt_i32_e64 s0, 0x64, s4
566 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
567 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
568 ; GISEL-GFX10-NEXT: s_endpgm
569 %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 40)
570 store i32 %result, ptr addrspace(1) %out
571 ret void
572 }
574 define amdgpu_kernel void @v_icmp_i32_sle(ptr addrspace(1) %out, i32 %src) {
575 ; SDAG-GFX11-LABEL: v_icmp_i32_sle:
576 ; SDAG-GFX11: ; %bb.0:
577 ; SDAG-GFX11-NEXT: s_clause 0x1
578 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
579 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
580 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
581 ; SDAG-GFX11-NEXT: v_cmp_ge_i32_e64 s2, 0x64, s2
582 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
583 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
584 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
585 ; SDAG-GFX11-NEXT: s_nop 0
586 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
587 ; SDAG-GFX11-NEXT: s_endpgm
588 ;
589 ; SDAG-GFX10-LABEL: v_icmp_i32_sle:
590 ; SDAG-GFX10: ; %bb.0:
591 ; SDAG-GFX10-NEXT: s_clause 0x1
592 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
593 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
594 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
595 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
596 ; SDAG-GFX10-NEXT: v_cmp_ge_i32_e64 s0, 0x64, s4
597 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
598 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
599 ; SDAG-GFX10-NEXT: s_endpgm
600 ;
601 ; GISEL-GFX11-LABEL: v_icmp_i32_sle:
602 ; GISEL-GFX11: ; %bb.0:
603 ; GISEL-GFX11-NEXT: s_clause 0x1
604 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
605 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
606 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
607 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
608 ; GISEL-GFX11-NEXT: v_cmp_ge_i32_e64 s2, 0x64, s2
609 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
610 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
611 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
612 ; GISEL-GFX11-NEXT: s_nop 0
613 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
614 ; GISEL-GFX11-NEXT: s_endpgm
615 ;
616 ; GISEL-GFX10-LABEL: v_icmp_i32_sle:
617 ; GISEL-GFX10: ; %bb.0:
618 ; GISEL-GFX10-NEXT: s_clause 0x1
619 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
620 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
621 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
622 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
623 ; GISEL-GFX10-NEXT: v_cmp_ge_i32_e64 s0, 0x64, s4
624 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
625 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
626 ; GISEL-GFX10-NEXT: s_endpgm
627 %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 41)
628 store i32 %result, ptr addrspace(1) %out
629 ret void
630 }
632 define amdgpu_kernel void @v_icmp_i64_eq(ptr addrspace(1) %out, i64 %src) {
633 ; SDAG-GFX11-LABEL: v_icmp_i64_eq:
634 ; SDAG-GFX11: ; %bb.0:
635 ; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
636 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
637 ; SDAG-GFX11-NEXT: v_cmp_eq_u64_e64 s2, 0x64, s[2:3]
638 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
639 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
640 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
641 ; SDAG-GFX11-NEXT: s_nop 0
642 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
643 ; SDAG-GFX11-NEXT: s_endpgm
644 ;
645 ; SDAG-GFX10-LABEL: v_icmp_i64_eq:
646 ; SDAG-GFX10: ; %bb.0:
647 ; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
648 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
649 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
650 ; SDAG-GFX10-NEXT: v_cmp_eq_u64_e64 s2, 0x64, s[2:3]
651 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
652 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
653 ; SDAG-GFX10-NEXT: s_endpgm
654 ;
655 ; GISEL-GFX11-LABEL: v_icmp_i64_eq:
656 ; GISEL-GFX11: ; %bb.0:
657 ; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
658 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
659 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
660 ; GISEL-GFX11-NEXT: v_cmp_eq_u64_e64 s2, 0x64, s[2:3]
661 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
662 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
663 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
664 ; GISEL-GFX11-NEXT: s_nop 0
665 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
666 ; GISEL-GFX11-NEXT: s_endpgm
667 ;
668 ; GISEL-GFX10-LABEL: v_icmp_i64_eq:
669 ; GISEL-GFX10: ; %bb.0:
670 ; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
671 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
672 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
673 ; GISEL-GFX10-NEXT: v_cmp_eq_u64_e64 s2, 0x64, s[2:3]
674 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
675 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
676 ; GISEL-GFX10-NEXT: s_endpgm
677 %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 32)
678 store i32 %result, ptr addrspace(1) %out
679 ret void
680 }
682 define amdgpu_kernel void @v_icmp_i64_ne(ptr addrspace(1) %out, i64 %src) {
683 ; SDAG-GFX11-LABEL: v_icmp_i64_ne:
684 ; SDAG-GFX11: ; %bb.0:
685 ; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
686 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
687 ; SDAG-GFX11-NEXT: v_cmp_ne_u64_e64 s2, 0x64, s[2:3]
688 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
689 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
690 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
691 ; SDAG-GFX11-NEXT: s_nop 0
692 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
693 ; SDAG-GFX11-NEXT: s_endpgm
694 ;
695 ; SDAG-GFX10-LABEL: v_icmp_i64_ne:
696 ; SDAG-GFX10: ; %bb.0:
697 ; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
698 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
699 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
700 ; SDAG-GFX10-NEXT: v_cmp_ne_u64_e64 s2, 0x64, s[2:3]
701 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
702 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
703 ; SDAG-GFX10-NEXT: s_endpgm
704 ;
705 ; GISEL-GFX11-LABEL: v_icmp_i64_ne:
706 ; GISEL-GFX11: ; %bb.0:
707 ; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
708 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
709 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
710 ; GISEL-GFX11-NEXT: v_cmp_ne_u64_e64 s2, 0x64, s[2:3]
711 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
712 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
713 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
714 ; GISEL-GFX11-NEXT: s_nop 0
715 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
716 ; GISEL-GFX11-NEXT: s_endpgm
717 ;
718 ; GISEL-GFX10-LABEL: v_icmp_i64_ne:
719 ; GISEL-GFX10: ; %bb.0:
720 ; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
721 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
722 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
723 ; GISEL-GFX10-NEXT: v_cmp_ne_u64_e64 s2, 0x64, s[2:3]
724 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
725 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
726 ; GISEL-GFX10-NEXT: s_endpgm
727 %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 33)
728 store i32 %result, ptr addrspace(1) %out
729 ret void
730 }
732 define amdgpu_kernel void @v_icmp_u64_ugt(ptr addrspace(1) %out, i64 %src) {
733 ; SDAG-GFX11-LABEL: v_icmp_u64_ugt:
734 ; SDAG-GFX11: ; %bb.0:
735 ; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
736 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
737 ; SDAG-GFX11-NEXT: v_cmp_lt_u64_e64 s2, 0x64, s[2:3]
738 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
739 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
740 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
741 ; SDAG-GFX11-NEXT: s_nop 0
742 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
743 ; SDAG-GFX11-NEXT: s_endpgm
744 ;
745 ; SDAG-GFX10-LABEL: v_icmp_u64_ugt:
746 ; SDAG-GFX10: ; %bb.0:
747 ; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
748 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
749 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
750 ; SDAG-GFX10-NEXT: v_cmp_lt_u64_e64 s2, 0x64, s[2:3]
751 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
752 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
753 ; SDAG-GFX10-NEXT: s_endpgm
754 ;
755 ; GISEL-GFX11-LABEL: v_icmp_u64_ugt:
756 ; GISEL-GFX11: ; %bb.0:
757 ; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
758 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
759 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
760 ; GISEL-GFX11-NEXT: v_cmp_lt_u64_e64 s2, 0x64, s[2:3]
761 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
762 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
763 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
764 ; GISEL-GFX11-NEXT: s_nop 0
765 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
766 ; GISEL-GFX11-NEXT: s_endpgm
767 ;
768 ; GISEL-GFX10-LABEL: v_icmp_u64_ugt:
769 ; GISEL-GFX10: ; %bb.0:
770 ; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
771 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
772 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
773 ; GISEL-GFX10-NEXT: v_cmp_lt_u64_e64 s2, 0x64, s[2:3]
774 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
775 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
776 ; GISEL-GFX10-NEXT: s_endpgm
777 %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 34)
778 store i32 %result, ptr addrspace(1) %out
779 ret void
780 }
782 define amdgpu_kernel void @v_icmp_u64_uge(ptr addrspace(1) %out, i64 %src) {
783 ; SDAG-GFX11-LABEL: v_icmp_u64_uge:
784 ; SDAG-GFX11: ; %bb.0:
785 ; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
786 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
787 ; SDAG-GFX11-NEXT: v_cmp_le_u64_e64 s2, 0x64, s[2:3]
788 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
789 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
790 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
791 ; SDAG-GFX11-NEXT: s_nop 0
792 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
793 ; SDAG-GFX11-NEXT: s_endpgm
794 ;
795 ; SDAG-GFX10-LABEL: v_icmp_u64_uge:
796 ; SDAG-GFX10: ; %bb.0:
797 ; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
798 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
799 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
800 ; SDAG-GFX10-NEXT: v_cmp_le_u64_e64 s2, 0x64, s[2:3]
801 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
802 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
803 ; SDAG-GFX10-NEXT: s_endpgm
804 ;
805 ; GISEL-GFX11-LABEL: v_icmp_u64_uge:
806 ; GISEL-GFX11: ; %bb.0:
807 ; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
808 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
809 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
810 ; GISEL-GFX11-NEXT: v_cmp_le_u64_e64 s2, 0x64, s[2:3]
811 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
812 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
813 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
814 ; GISEL-GFX11-NEXT: s_nop 0
815 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
816 ; GISEL-GFX11-NEXT: s_endpgm
817 ;
818 ; GISEL-GFX10-LABEL: v_icmp_u64_uge:
819 ; GISEL-GFX10: ; %bb.0:
820 ; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
821 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
822 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
823 ; GISEL-GFX10-NEXT: v_cmp_le_u64_e64 s2, 0x64, s[2:3]
824 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
825 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
826 ; GISEL-GFX10-NEXT: s_endpgm
827 %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 35)
828 store i32 %result, ptr addrspace(1) %out
829 ret void
830 }
832 define amdgpu_kernel void @v_icmp_u64_ult(ptr addrspace(1) %out, i64 %src) {
833 ; SDAG-GFX11-LABEL: v_icmp_u64_ult:
834 ; SDAG-GFX11: ; %bb.0:
835 ; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
836 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
837 ; SDAG-GFX11-NEXT: v_cmp_gt_u64_e64 s2, 0x64, s[2:3]
838 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
839 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
840 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
841 ; SDAG-GFX11-NEXT: s_nop 0
842 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
843 ; SDAG-GFX11-NEXT: s_endpgm
844 ;
845 ; SDAG-GFX10-LABEL: v_icmp_u64_ult:
846 ; SDAG-GFX10: ; %bb.0:
847 ; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
848 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
849 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
850 ; SDAG-GFX10-NEXT: v_cmp_gt_u64_e64 s2, 0x64, s[2:3]
851 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
852 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
853 ; SDAG-GFX10-NEXT: s_endpgm
854 ;
855 ; GISEL-GFX11-LABEL: v_icmp_u64_ult:
856 ; GISEL-GFX11: ; %bb.0:
857 ; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
858 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
859 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
860 ; GISEL-GFX11-NEXT: v_cmp_gt_u64_e64 s2, 0x64, s[2:3]
861 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
862 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
863 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
864 ; GISEL-GFX11-NEXT: s_nop 0
865 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
866 ; GISEL-GFX11-NEXT: s_endpgm
867 ;
868 ; GISEL-GFX10-LABEL: v_icmp_u64_ult:
869 ; GISEL-GFX10: ; %bb.0:
870 ; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
871 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
872 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
873 ; GISEL-GFX10-NEXT: v_cmp_gt_u64_e64 s2, 0x64, s[2:3]
874 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
875 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
876 ; GISEL-GFX10-NEXT: s_endpgm
877 %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 36)
878 store i32 %result, ptr addrspace(1) %out
879 ret void
880 }
882 define amdgpu_kernel void @v_icmp_u64_ule(ptr addrspace(1) %out, i64 %src) {
883 ; SDAG-GFX11-LABEL: v_icmp_u64_ule:
884 ; SDAG-GFX11: ; %bb.0:
885 ; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
886 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
887 ; SDAG-GFX11-NEXT: v_cmp_ge_u64_e64 s2, 0x64, s[2:3]
888 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
889 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
890 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
891 ; SDAG-GFX11-NEXT: s_nop 0
892 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
893 ; SDAG-GFX11-NEXT: s_endpgm
894 ;
895 ; SDAG-GFX10-LABEL: v_icmp_u64_ule:
896 ; SDAG-GFX10: ; %bb.0:
897 ; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
898 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
899 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
900 ; SDAG-GFX10-NEXT: v_cmp_ge_u64_e64 s2, 0x64, s[2:3]
901 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
902 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
903 ; SDAG-GFX10-NEXT: s_endpgm
904 ;
905 ; GISEL-GFX11-LABEL: v_icmp_u64_ule:
906 ; GISEL-GFX11: ; %bb.0:
907 ; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
908 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
909 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
910 ; GISEL-GFX11-NEXT: v_cmp_ge_u64_e64 s2, 0x64, s[2:3]
911 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
912 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
913 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
914 ; GISEL-GFX11-NEXT: s_nop 0
915 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
916 ; GISEL-GFX11-NEXT: s_endpgm
917 ;
918 ; GISEL-GFX10-LABEL: v_icmp_u64_ule:
919 ; GISEL-GFX10: ; %bb.0:
920 ; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
921 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
922 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
923 ; GISEL-GFX10-NEXT: v_cmp_ge_u64_e64 s2, 0x64, s[2:3]
924 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
925 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
926 ; GISEL-GFX10-NEXT: s_endpgm
927 %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 37)
928 store i32 %result, ptr addrspace(1) %out
929 ret void
930 }
932 define amdgpu_kernel void @v_icmp_i64_sgt(ptr addrspace(1) %out, i64 %src) {
933 ; SDAG-GFX11-LABEL: v_icmp_i64_sgt:
934 ; SDAG-GFX11: ; %bb.0:
935 ; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
936 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
937 ; SDAG-GFX11-NEXT: v_cmp_lt_i64_e64 s2, 0x64, s[2:3]
938 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
939 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
940 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
941 ; SDAG-GFX11-NEXT: s_nop 0
942 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
943 ; SDAG-GFX11-NEXT: s_endpgm
944 ;
945 ; SDAG-GFX10-LABEL: v_icmp_i64_sgt:
946 ; SDAG-GFX10: ; %bb.0:
947 ; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
948 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
949 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
950 ; SDAG-GFX10-NEXT: v_cmp_lt_i64_e64 s2, 0x64, s[2:3]
951 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
952 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
953 ; SDAG-GFX10-NEXT: s_endpgm
954 ;
955 ; GISEL-GFX11-LABEL: v_icmp_i64_sgt:
956 ; GISEL-GFX11: ; %bb.0:
957 ; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
958 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
959 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
960 ; GISEL-GFX11-NEXT: v_cmp_lt_i64_e64 s2, 0x64, s[2:3]
961 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
962 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
963 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
964 ; GISEL-GFX11-NEXT: s_nop 0
965 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
966 ; GISEL-GFX11-NEXT: s_endpgm
967 ;
968 ; GISEL-GFX10-LABEL: v_icmp_i64_sgt:
969 ; GISEL-GFX10: ; %bb.0:
970 ; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
971 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
972 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
973 ; GISEL-GFX10-NEXT: v_cmp_lt_i64_e64 s2, 0x64, s[2:3]
974 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
975 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
976 ; GISEL-GFX10-NEXT: s_endpgm
977 %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 38)
978 store i32 %result, ptr addrspace(1) %out
979 ret void
980 }
982 define amdgpu_kernel void @v_icmp_i64_sge(ptr addrspace(1) %out, i64 %src) {
983 ; SDAG-GFX11-LABEL: v_icmp_i64_sge:
984 ; SDAG-GFX11: ; %bb.0:
985 ; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
986 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
987 ; SDAG-GFX11-NEXT: v_cmp_le_i64_e64 s2, 0x64, s[2:3]
988 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
989 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
990 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
991 ; SDAG-GFX11-NEXT: s_nop 0
992 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
993 ; SDAG-GFX11-NEXT: s_endpgm
994 ;
995 ; SDAG-GFX10-LABEL: v_icmp_i64_sge:
996 ; SDAG-GFX10: ; %bb.0:
997 ; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
998 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
999 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1000 ; SDAG-GFX10-NEXT: v_cmp_le_i64_e64 s2, 0x64, s[2:3]
1001 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
1002 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
1003 ; SDAG-GFX10-NEXT: s_endpgm
1004 ;
1005 ; GISEL-GFX11-LABEL: v_icmp_i64_sge:
1006 ; GISEL-GFX11: ; %bb.0:
1007 ; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
1008 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
1009 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1010 ; GISEL-GFX11-NEXT: v_cmp_le_i64_e64 s2, 0x64, s[2:3]
1011 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1012 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
1013 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
1014 ; GISEL-GFX11-NEXT: s_nop 0
1015 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1016 ; GISEL-GFX11-NEXT: s_endpgm
1017 ;
1018 ; GISEL-GFX10-LABEL: v_icmp_i64_sge:
1019 ; GISEL-GFX10: ; %bb.0:
1020 ; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1021 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
1022 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1023 ; GISEL-GFX10-NEXT: v_cmp_le_i64_e64 s2, 0x64, s[2:3]
1024 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
1025 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
1026 ; GISEL-GFX10-NEXT: s_endpgm
1027 %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 39)
1028 store i32 %result, ptr addrspace(1) %out
1029 ret void
1030 }
1032 define amdgpu_kernel void @v_icmp_i64_slt(ptr addrspace(1) %out, i64 %src) {
1033 ; SDAG-GFX11-LABEL: v_icmp_i64_slt:
1034 ; SDAG-GFX11: ; %bb.0:
1035 ; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
1036 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1037 ; SDAG-GFX11-NEXT: v_cmp_gt_i64_e64 s2, 0x64, s[2:3]
1038 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1039 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
1040 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1041 ; SDAG-GFX11-NEXT: s_nop 0
1042 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1043 ; SDAG-GFX11-NEXT: s_endpgm
1044 ;
1045 ; SDAG-GFX10-LABEL: v_icmp_i64_slt:
1046 ; SDAG-GFX10: ; %bb.0:
1047 ; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1048 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
1049 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1050 ; SDAG-GFX10-NEXT: v_cmp_gt_i64_e64 s2, 0x64, s[2:3]
1051 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
1052 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
1053 ; SDAG-GFX10-NEXT: s_endpgm
1054 ;
1055 ; GISEL-GFX11-LABEL: v_icmp_i64_slt:
1056 ; GISEL-GFX11: ; %bb.0:
1057 ; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
1058 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
1059 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1060 ; GISEL-GFX11-NEXT: v_cmp_gt_i64_e64 s2, 0x64, s[2:3]
1061 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1062 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
1063 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
1064 ; GISEL-GFX11-NEXT: s_nop 0
1065 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1066 ; GISEL-GFX11-NEXT: s_endpgm
1067 ;
1068 ; GISEL-GFX10-LABEL: v_icmp_i64_slt:
1069 ; GISEL-GFX10: ; %bb.0:
1070 ; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1071 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
1072 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1073 ; GISEL-GFX10-NEXT: v_cmp_gt_i64_e64 s2, 0x64, s[2:3]
1074 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
1075 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
1076 ; GISEL-GFX10-NEXT: s_endpgm
1077 %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 40)
1078 store i32 %result, ptr addrspace(1) %out
1079 ret void
1080 }
1082 define amdgpu_kernel void @v_icmp_i64_sle(ptr addrspace(1) %out, i64 %src) {
1083 ; SDAG-GFX11-LABEL: v_icmp_i64_sle:
1084 ; SDAG-GFX11: ; %bb.0:
1085 ; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
1086 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1087 ; SDAG-GFX11-NEXT: v_cmp_ge_i64_e64 s2, 0x64, s[2:3]
1088 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1089 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
1090 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1091 ; SDAG-GFX11-NEXT: s_nop 0
1092 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1093 ; SDAG-GFX11-NEXT: s_endpgm
1094 ;
1095 ; SDAG-GFX10-LABEL: v_icmp_i64_sle:
1096 ; SDAG-GFX10: ; %bb.0:
1097 ; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1098 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
1099 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1100 ; SDAG-GFX10-NEXT: v_cmp_ge_i64_e64 s2, 0x64, s[2:3]
1101 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2
1102 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1]
1103 ; SDAG-GFX10-NEXT: s_endpgm
1104 ;
1105 ; GISEL-GFX11-LABEL: v_icmp_i64_sle:
1106 ; GISEL-GFX11: ; %bb.0:
1107 ; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
1108 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
1109 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1110 ; GISEL-GFX11-NEXT: v_cmp_ge_i64_e64 s2, 0x64, s[2:3]
1111 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1112 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
1113 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
1114 ; GISEL-GFX11-NEXT: s_nop 0
1115 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1116 ; GISEL-GFX11-NEXT: s_endpgm
1117 ;
1118 ; GISEL-GFX10-LABEL: v_icmp_i64_sle:
1119 ; GISEL-GFX10: ; %bb.0:
1120 ; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1121 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
1122 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1123 ; GISEL-GFX10-NEXT: v_cmp_ge_i64_e64 s2, 0x64, s[2:3]
1124 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2
1125 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1]
1126 ; GISEL-GFX10-NEXT: s_endpgm
1127 %result = call i32 @llvm.amdgcn.icmp.i64(i64 %src, i64 100, i32 41)
1128 store i32 %result, ptr addrspace(1) %out
1129 ret void
1130 }
1132 define amdgpu_kernel void @v_icmp_i16_eq(ptr addrspace(1) %out, i16 %src) {
1133 ; SDAG-GFX11-LABEL: v_icmp_i16_eq:
1134 ; SDAG-GFX11: ; %bb.0:
1135 ; SDAG-GFX11-NEXT: s_clause 0x1
1136 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1137 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1138 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1139 ; SDAG-GFX11-NEXT: v_cmp_eq_u16_e64 s2, 0x64, s2
1140 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1141 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
1142 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1143 ; SDAG-GFX11-NEXT: s_nop 0
1144 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1145 ; SDAG-GFX11-NEXT: s_endpgm
1146 ;
1147 ; SDAG-GFX10-LABEL: v_icmp_i16_eq:
1148 ; SDAG-GFX10: ; %bb.0:
1149 ; SDAG-GFX10-NEXT: s_clause 0x1
1150 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1151 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1152 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
1153 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1154 ; SDAG-GFX10-NEXT: v_cmp_eq_u16_e64 s0, 0x64, s4
1155 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
1156 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
1157 ; SDAG-GFX10-NEXT: s_endpgm
1158 ;
1159 ; GISEL-GFX11-LABEL: v_icmp_i16_eq:
1160 ; GISEL-GFX11: ; %bb.0:
1161 ; GISEL-GFX11-NEXT: s_clause 0x1
1162 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1163 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1164 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
1165 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1166 ; GISEL-GFX11-NEXT: v_cmp_eq_u16_e64 s2, 0x64, s2
1167 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1168 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
1169 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
1170 ; GISEL-GFX11-NEXT: s_nop 0
1171 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1172 ; GISEL-GFX11-NEXT: s_endpgm
1173 ;
1174 ; GISEL-GFX10-LABEL: v_icmp_i16_eq:
1175 ; GISEL-GFX10: ; %bb.0:
1176 ; GISEL-GFX10-NEXT: s_clause 0x1
1177 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1178 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1179 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
1180 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1181 ; GISEL-GFX10-NEXT: v_cmp_eq_u16_e64 s0, 0x64, s4
1182 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
1183 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
1184 ; GISEL-GFX10-NEXT: s_endpgm
1185 %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 32)
1186 store i32 %result, ptr addrspace(1) %out
1187 ret void
1188 }
1190 define amdgpu_kernel void @v_icmp_i16(ptr addrspace(1) %out, i16 %src) {
1191 ; SDAG-GFX11-LABEL: v_icmp_i16:
1192 ; SDAG-GFX11: ; %bb.0:
1193 ; SDAG-GFX11-NEXT: s_endpgm
1194 ;
1195 ; SDAG-GFX10-LABEL: v_icmp_i16:
1196 ; SDAG-GFX10: ; %bb.0:
1197 ; SDAG-GFX10-NEXT: s_endpgm
1198 ;
1199 ; GISEL-GFX11-LABEL: v_icmp_i16:
1200 ; GISEL-GFX11: ; %bb.0:
1201 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1202 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, 0
1203 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1204 ; GISEL-GFX11-NEXT: global_store_b32 v0, v0, s[0:1]
1205 ; GISEL-GFX11-NEXT: s_nop 0
1206 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1207 ; GISEL-GFX11-NEXT: s_endpgm
1208 ;
1209 ; GISEL-GFX10-LABEL: v_icmp_i16:
1210 ; GISEL-GFX10: ; %bb.0:
1211 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1212 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, 0
1213 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1214 ; GISEL-GFX10-NEXT: global_store_dword v0, v0, s[0:1]
1215 ; GISEL-GFX10-NEXT: s_endpgm
1216 %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 30)
1217 store i32 %result, ptr addrspace(1) %out
1218 ret void
1219 }
1221 define amdgpu_kernel void @v_icmp_i16_ne(ptr addrspace(1) %out, i16 %src) {
1222 ; SDAG-GFX11-LABEL: v_icmp_i16_ne:
1223 ; SDAG-GFX11: ; %bb.0:
1224 ; SDAG-GFX11-NEXT: s_clause 0x1
1225 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1226 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1227 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1228 ; SDAG-GFX11-NEXT: v_cmp_ne_u16_e64 s2, 0x64, s2
1229 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1230 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
1231 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1232 ; SDAG-GFX11-NEXT: s_nop 0
1233 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1234 ; SDAG-GFX11-NEXT: s_endpgm
1235 ;
1236 ; SDAG-GFX10-LABEL: v_icmp_i16_ne:
1237 ; SDAG-GFX10: ; %bb.0:
1238 ; SDAG-GFX10-NEXT: s_clause 0x1
1239 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1240 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1241 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
1242 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1243 ; SDAG-GFX10-NEXT: v_cmp_ne_u16_e64 s0, 0x64, s4
1244 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
1245 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
1246 ; SDAG-GFX10-NEXT: s_endpgm
1247 ;
1248 ; GISEL-GFX11-LABEL: v_icmp_i16_ne:
1249 ; GISEL-GFX11: ; %bb.0:
1250 ; GISEL-GFX11-NEXT: s_clause 0x1
1251 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1252 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1253 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
1254 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1255 ; GISEL-GFX11-NEXT: v_cmp_ne_u16_e64 s2, 0x64, s2
1256 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1257 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
1258 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
1259 ; GISEL-GFX11-NEXT: s_nop 0
1260 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1261 ; GISEL-GFX11-NEXT: s_endpgm
1262 ;
1263 ; GISEL-GFX10-LABEL: v_icmp_i16_ne:
1264 ; GISEL-GFX10: ; %bb.0:
1265 ; GISEL-GFX10-NEXT: s_clause 0x1
1266 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1267 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1268 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
1269 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1270 ; GISEL-GFX10-NEXT: v_cmp_ne_u16_e64 s0, 0x64, s4
1271 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
1272 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
1273 ; GISEL-GFX10-NEXT: s_endpgm
1274 %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 33)
1275 store i32 %result, ptr addrspace(1) %out
1276 ret void
1277 }
1279 define amdgpu_kernel void @v_icmp_i16_ugt(ptr addrspace(1) %out, i16 %src) {
1280 ; SDAG-GFX11-LABEL: v_icmp_i16_ugt:
1281 ; SDAG-GFX11: ; %bb.0:
1282 ; SDAG-GFX11-NEXT: s_clause 0x1
1283 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1284 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1285 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1286 ; SDAG-GFX11-NEXT: v_cmp_lt_u16_e64 s2, 0x64, s2
1287 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1288 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
1289 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1290 ; SDAG-GFX11-NEXT: s_nop 0
1291 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1292 ; SDAG-GFX11-NEXT: s_endpgm
1293 ;
1294 ; SDAG-GFX10-LABEL: v_icmp_i16_ugt:
1295 ; SDAG-GFX10: ; %bb.0:
1296 ; SDAG-GFX10-NEXT: s_clause 0x1
1297 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1298 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1299 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
1300 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1301 ; SDAG-GFX10-NEXT: v_cmp_lt_u16_e64 s0, 0x64, s4
1302 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
1303 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
1304 ; SDAG-GFX10-NEXT: s_endpgm
1305 ;
1306 ; GISEL-GFX11-LABEL: v_icmp_i16_ugt:
1307 ; GISEL-GFX11: ; %bb.0:
1308 ; GISEL-GFX11-NEXT: s_clause 0x1
1309 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1310 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1311 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
1312 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1313 ; GISEL-GFX11-NEXT: v_cmp_lt_u16_e64 s2, 0x64, s2
1314 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1315 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
1316 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
1317 ; GISEL-GFX11-NEXT: s_nop 0
1318 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1319 ; GISEL-GFX11-NEXT: s_endpgm
1320 ;
1321 ; GISEL-GFX10-LABEL: v_icmp_i16_ugt:
1322 ; GISEL-GFX10: ; %bb.0:
1323 ; GISEL-GFX10-NEXT: s_clause 0x1
1324 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1325 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1326 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
1327 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1328 ; GISEL-GFX10-NEXT: v_cmp_lt_u16_e64 s0, 0x64, s4
1329 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
1330 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
1331 ; GISEL-GFX10-NEXT: s_endpgm
1332 %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 34)
1333 store i32 %result, ptr addrspace(1) %out
1334 ret void
1335 }
1337 define amdgpu_kernel void @v_icmp_i16_uge(ptr addrspace(1) %out, i16 %src) {
1338 ; SDAG-GFX11-LABEL: v_icmp_i16_uge:
1339 ; SDAG-GFX11: ; %bb.0:
1340 ; SDAG-GFX11-NEXT: s_clause 0x1
1341 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1342 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1343 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1344 ; SDAG-GFX11-NEXT: v_cmp_le_u16_e64 s2, 0x64, s2
1345 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1346 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
1347 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1348 ; SDAG-GFX11-NEXT: s_nop 0
1349 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1350 ; SDAG-GFX11-NEXT: s_endpgm
1351 ;
1352 ; SDAG-GFX10-LABEL: v_icmp_i16_uge:
1353 ; SDAG-GFX10: ; %bb.0:
1354 ; SDAG-GFX10-NEXT: s_clause 0x1
1355 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1356 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1357 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
1358 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1359 ; SDAG-GFX10-NEXT: v_cmp_le_u16_e64 s0, 0x64, s4
1360 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
1361 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
1362 ; SDAG-GFX10-NEXT: s_endpgm
1363 ;
1364 ; GISEL-GFX11-LABEL: v_icmp_i16_uge:
1365 ; GISEL-GFX11: ; %bb.0:
1366 ; GISEL-GFX11-NEXT: s_clause 0x1
1367 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1368 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1369 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
1370 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1371 ; GISEL-GFX11-NEXT: v_cmp_le_u16_e64 s2, 0x64, s2
1372 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1373 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
1374 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
1375 ; GISEL-GFX11-NEXT: s_nop 0
1376 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1377 ; GISEL-GFX11-NEXT: s_endpgm
1378 ;
1379 ; GISEL-GFX10-LABEL: v_icmp_i16_uge:
1380 ; GISEL-GFX10: ; %bb.0:
1381 ; GISEL-GFX10-NEXT: s_clause 0x1
1382 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1383 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1384 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
1385 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1386 ; GISEL-GFX10-NEXT: v_cmp_le_u16_e64 s0, 0x64, s4
1387 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
1388 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
1389 ; GISEL-GFX10-NEXT: s_endpgm
1390 %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 35)
1391 store i32 %result, ptr addrspace(1) %out
1392 ret void
1393 }
1395 define amdgpu_kernel void @v_icmp_i16_ult(ptr addrspace(1) %out, i16 %src) {
1396 ; SDAG-GFX11-LABEL: v_icmp_i16_ult:
1397 ; SDAG-GFX11: ; %bb.0:
1398 ; SDAG-GFX11-NEXT: s_clause 0x1
1399 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1400 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1401 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1402 ; SDAG-GFX11-NEXT: v_cmp_gt_u16_e64 s2, 0x64, s2
1403 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1404 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
1405 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1406 ; SDAG-GFX11-NEXT: s_nop 0
1407 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1408 ; SDAG-GFX11-NEXT: s_endpgm
1409 ;
1410 ; SDAG-GFX10-LABEL: v_icmp_i16_ult:
1411 ; SDAG-GFX10: ; %bb.0:
1412 ; SDAG-GFX10-NEXT: s_clause 0x1
1413 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1414 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1415 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
1416 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1417 ; SDAG-GFX10-NEXT: v_cmp_gt_u16_e64 s0, 0x64, s4
1418 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
1419 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
1420 ; SDAG-GFX10-NEXT: s_endpgm
1421 ;
1422 ; GISEL-GFX11-LABEL: v_icmp_i16_ult:
1423 ; GISEL-GFX11: ; %bb.0:
1424 ; GISEL-GFX11-NEXT: s_clause 0x1
1425 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1426 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1427 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
1428 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1429 ; GISEL-GFX11-NEXT: v_cmp_gt_u16_e64 s2, 0x64, s2
1430 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1431 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
1432 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
1433 ; GISEL-GFX11-NEXT: s_nop 0
1434 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1435 ; GISEL-GFX11-NEXT: s_endpgm
1436 ;
1437 ; GISEL-GFX10-LABEL: v_icmp_i16_ult:
1438 ; GISEL-GFX10: ; %bb.0:
1439 ; GISEL-GFX10-NEXT: s_clause 0x1
1440 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1441 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1442 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
1443 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1444 ; GISEL-GFX10-NEXT: v_cmp_gt_u16_e64 s0, 0x64, s4
1445 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
1446 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
1447 ; GISEL-GFX10-NEXT: s_endpgm
1448 %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 36)
1449 store i32 %result, ptr addrspace(1) %out
1450 ret void
1451 }
1453 define amdgpu_kernel void @v_icmp_i16_ule(ptr addrspace(1) %out, i16 %src) {
1454 ; SDAG-GFX11-LABEL: v_icmp_i16_ule:
1455 ; SDAG-GFX11: ; %bb.0:
1456 ; SDAG-GFX11-NEXT: s_clause 0x1
1457 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1458 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1459 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1460 ; SDAG-GFX11-NEXT: v_cmp_ge_u16_e64 s2, 0x64, s2
1461 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1462 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
1463 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1464 ; SDAG-GFX11-NEXT: s_nop 0
1465 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1466 ; SDAG-GFX11-NEXT: s_endpgm
1467 ;
1468 ; SDAG-GFX10-LABEL: v_icmp_i16_ule:
1469 ; SDAG-GFX10: ; %bb.0:
1470 ; SDAG-GFX10-NEXT: s_clause 0x1
1471 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1472 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1473 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
1474 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1475 ; SDAG-GFX10-NEXT: v_cmp_ge_u16_e64 s0, 0x64, s4
1476 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
1477 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
1478 ; SDAG-GFX10-NEXT: s_endpgm
1479 ;
1480 ; GISEL-GFX11-LABEL: v_icmp_i16_ule:
1481 ; GISEL-GFX11: ; %bb.0:
1482 ; GISEL-GFX11-NEXT: s_clause 0x1
1483 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1484 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1485 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
1486 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1487 ; GISEL-GFX11-NEXT: v_cmp_ge_u16_e64 s2, 0x64, s2
1488 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1489 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
1490 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
1491 ; GISEL-GFX11-NEXT: s_nop 0
1492 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1493 ; GISEL-GFX11-NEXT: s_endpgm
1494 ;
1495 ; GISEL-GFX10-LABEL: v_icmp_i16_ule:
1496 ; GISEL-GFX10: ; %bb.0:
1497 ; GISEL-GFX10-NEXT: s_clause 0x1
1498 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1499 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1500 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
1501 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1502 ; GISEL-GFX10-NEXT: v_cmp_ge_u16_e64 s0, 0x64, s4
1503 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
1504 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
1505 ; GISEL-GFX10-NEXT: s_endpgm
1506 %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 37)
1507 store i32 %result, ptr addrspace(1) %out
1508 ret void
1509 }
1511 define amdgpu_kernel void @v_icmp_i16_sgt(ptr addrspace(1) %out, i16 %src) #1 {
1512 ; SDAG-GFX11-LABEL: v_icmp_i16_sgt:
1513 ; SDAG-GFX11: ; %bb.0:
1514 ; SDAG-GFX11-NEXT: s_clause 0x1
1515 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1516 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1517 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1518 ; SDAG-GFX11-NEXT: v_cmp_lt_i16_e64 s2, 0x64, s2
1519 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1520 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
1521 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1522 ; SDAG-GFX11-NEXT: s_nop 0
1523 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1524 ; SDAG-GFX11-NEXT: s_endpgm
1525 ;
1526 ; SDAG-GFX10-LABEL: v_icmp_i16_sgt:
1527 ; SDAG-GFX10: ; %bb.0:
1528 ; SDAG-GFX10-NEXT: s_clause 0x1
1529 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1530 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1531 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
1532 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1533 ; SDAG-GFX10-NEXT: v_cmp_lt_i16_e64 s0, 0x64, s4
1534 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
1535 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
1536 ; SDAG-GFX10-NEXT: s_endpgm
1537 ;
1538 ; GISEL-GFX11-LABEL: v_icmp_i16_sgt:
1539 ; GISEL-GFX11: ; %bb.0:
1540 ; GISEL-GFX11-NEXT: s_clause 0x1
1541 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1542 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1543 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
1544 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1545 ; GISEL-GFX11-NEXT: v_cmp_lt_i16_e64 s2, 0x64, s2
1546 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1547 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
1548 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
1549 ; GISEL-GFX11-NEXT: s_nop 0
1550 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1551 ; GISEL-GFX11-NEXT: s_endpgm
1552 ;
1553 ; GISEL-GFX10-LABEL: v_icmp_i16_sgt:
1554 ; GISEL-GFX10: ; %bb.0:
1555 ; GISEL-GFX10-NEXT: s_clause 0x1
1556 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1557 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1558 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
1559 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1560 ; GISEL-GFX10-NEXT: v_cmp_lt_i16_e64 s0, 0x64, s4
1561 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
1562 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
1563 ; GISEL-GFX10-NEXT: s_endpgm
1564 %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 38)
1565 store i32 %result, ptr addrspace(1) %out
1566 ret void
1567 }
1569 define amdgpu_kernel void @v_icmp_i16_sge(ptr addrspace(1) %out, i16 %src) {
1570 ; SDAG-GFX11-LABEL: v_icmp_i16_sge:
1571 ; SDAG-GFX11: ; %bb.0:
1572 ; SDAG-GFX11-NEXT: s_clause 0x1
1573 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1574 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1575 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1576 ; SDAG-GFX11-NEXT: v_cmp_le_i16_e64 s2, 0x64, s2
1577 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1578 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
1579 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1580 ; SDAG-GFX11-NEXT: s_nop 0
1581 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1582 ; SDAG-GFX11-NEXT: s_endpgm
1583 ;
1584 ; SDAG-GFX10-LABEL: v_icmp_i16_sge:
1585 ; SDAG-GFX10: ; %bb.0:
1586 ; SDAG-GFX10-NEXT: s_clause 0x1
1587 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1588 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1589 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
1590 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1591 ; SDAG-GFX10-NEXT: v_cmp_le_i16_e64 s0, 0x64, s4
1592 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
1593 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
1594 ; SDAG-GFX10-NEXT: s_endpgm
1595 ;
1596 ; GISEL-GFX11-LABEL: v_icmp_i16_sge:
1597 ; GISEL-GFX11: ; %bb.0:
1598 ; GISEL-GFX11-NEXT: s_clause 0x1
1599 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1600 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1601 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
1602 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1603 ; GISEL-GFX11-NEXT: v_cmp_le_i16_e64 s2, 0x64, s2
1604 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1605 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
1606 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
1607 ; GISEL-GFX11-NEXT: s_nop 0
1608 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1609 ; GISEL-GFX11-NEXT: s_endpgm
1610 ;
1611 ; GISEL-GFX10-LABEL: v_icmp_i16_sge:
1612 ; GISEL-GFX10: ; %bb.0:
1613 ; GISEL-GFX10-NEXT: s_clause 0x1
1614 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1615 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1616 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
1617 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1618 ; GISEL-GFX10-NEXT: v_cmp_le_i16_e64 s0, 0x64, s4
1619 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
1620 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
1621 ; GISEL-GFX10-NEXT: s_endpgm
1622 %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 39)
1623 store i32 %result, ptr addrspace(1) %out
1624 ret void
1625 }
1627 define amdgpu_kernel void @v_icmp_i16_slt(ptr addrspace(1) %out, i16 %src) {
1628 ; SDAG-GFX11-LABEL: v_icmp_i16_slt:
1629 ; SDAG-GFX11: ; %bb.0:
1630 ; SDAG-GFX11-NEXT: s_clause 0x1
1631 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1632 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1633 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1634 ; SDAG-GFX11-NEXT: v_cmp_gt_i16_e64 s2, 0x64, s2
1635 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1636 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
1637 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1638 ; SDAG-GFX11-NEXT: s_nop 0
1639 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1640 ; SDAG-GFX11-NEXT: s_endpgm
1641 ;
1642 ; SDAG-GFX10-LABEL: v_icmp_i16_slt:
1643 ; SDAG-GFX10: ; %bb.0:
1644 ; SDAG-GFX10-NEXT: s_clause 0x1
1645 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1646 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1647 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
1648 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1649 ; SDAG-GFX10-NEXT: v_cmp_gt_i16_e64 s0, 0x64, s4
1650 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
1651 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
1652 ; SDAG-GFX10-NEXT: s_endpgm
1653 ;
1654 ; GISEL-GFX11-LABEL: v_icmp_i16_slt:
1655 ; GISEL-GFX11: ; %bb.0:
1656 ; GISEL-GFX11-NEXT: s_clause 0x1
1657 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1658 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1659 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
1660 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1661 ; GISEL-GFX11-NEXT: v_cmp_gt_i16_e64 s2, 0x64, s2
1662 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1663 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
1664 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
1665 ; GISEL-GFX11-NEXT: s_nop 0
1666 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1667 ; GISEL-GFX11-NEXT: s_endpgm
1668 ;
1669 ; GISEL-GFX10-LABEL: v_icmp_i16_slt:
1670 ; GISEL-GFX10: ; %bb.0:
1671 ; GISEL-GFX10-NEXT: s_clause 0x1
1672 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1673 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1674 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
1675 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1676 ; GISEL-GFX10-NEXT: v_cmp_gt_i16_e64 s0, 0x64, s4
1677 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
1678 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
1679 ; GISEL-GFX10-NEXT: s_endpgm
1680 %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 40)
1681 store i32 %result, ptr addrspace(1) %out
1682 ret void
1683 }
1685 define amdgpu_kernel void @v_icmp_i16_sle(ptr addrspace(1) %out, i16 %src) {
1686 ; SDAG-GFX11-LABEL: v_icmp_i16_sle:
1687 ; SDAG-GFX11: ; %bb.0:
1688 ; SDAG-GFX11-NEXT: s_clause 0x1
1689 ; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1690 ; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1691 ; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1692 ; SDAG-GFX11-NEXT: v_cmp_ge_i16_e64 s2, 0x64, s2
1693 ; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1694 ; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
1695 ; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1696 ; SDAG-GFX11-NEXT: s_nop 0
1697 ; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1698 ; SDAG-GFX11-NEXT: s_endpgm
1699 ;
1700 ; SDAG-GFX10-LABEL: v_icmp_i16_sle:
1701 ; SDAG-GFX10: ; %bb.0:
1702 ; SDAG-GFX10-NEXT: s_clause 0x1
1703 ; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1704 ; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1705 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0
1706 ; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1707 ; SDAG-GFX10-NEXT: v_cmp_ge_i16_e64 s0, 0x64, s4
1708 ; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0
1709 ; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3]
1710 ; SDAG-GFX10-NEXT: s_endpgm
1711 ;
1712 ; GISEL-GFX11-LABEL: v_icmp_i16_sle:
1713 ; GISEL-GFX11: ; %bb.0:
1714 ; GISEL-GFX11-NEXT: s_clause 0x1
1715 ; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
1716 ; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
1717 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0
1718 ; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0)
1719 ; GISEL-GFX11-NEXT: v_cmp_ge_i16_e64 s2, 0x64, s2
1720 ; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
1721 ; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2
1722 ; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
1723 ; GISEL-GFX11-NEXT: s_nop 0
1724 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1725 ; GISEL-GFX11-NEXT: s_endpgm
1726 ;
1727 ; GISEL-GFX10-LABEL: v_icmp_i16_sle:
1728 ; GISEL-GFX10: ; %bb.0:
1729 ; GISEL-GFX10-NEXT: s_clause 0x1
1730 ; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c
1731 ; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
1732 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0
1733 ; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0)
1734 ; GISEL-GFX10-NEXT: v_cmp_ge_i16_e64 s0, 0x64, s4
1735 ; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0
1736 ; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3]
1737 ; GISEL-GFX10-NEXT: s_endpgm
1738 %result = call i32 @llvm.amdgcn.icmp.i16(i16 %src, i16 100, i32 41)
1739 store i32 %result, ptr addrspace(1) %out
1740 ret void
1741 }
1743 define amdgpu_kernel void @v_icmp_i1_ne0(ptr addrspace(1) %out, i32 %a, i32 %b) {
1744 ; GFX11-LABEL: v_icmp_i1_ne0:
1745 ; GFX11: ; %bb.0:
1746 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
1747 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
1748 ; GFX11-NEXT: s_cmp_gt_u32 s2, 1
1749 ; GFX11-NEXT: s_cselect_b32 s2, -1, 0
1750 ; GFX11-NEXT: s_cmp_gt_u32 s3, 2
1751 ; GFX11-NEXT: s_cselect_b32 s3, -1, 0
1752 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
1753 ; GFX11-NEXT: s_and_b32 s2, s2, s3
1754 ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
1755 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
1756 ; GFX11-NEXT: s_nop 0
1757 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1758 ; GFX11-NEXT: s_endpgm
1759 ;
1760 ; GFX10-LABEL: v_icmp_i1_ne0:
1761 ; GFX10: ; %bb.0:
1762 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1763 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
1764 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
1765 ; GFX10-NEXT: s_cmp_gt_u32 s2, 1
1766 ; GFX10-NEXT: s_cselect_b32 s2, -1, 0
1767 ; GFX10-NEXT: s_cmp_gt_u32 s3, 2
1768 ; GFX10-NEXT: s_cselect_b32 s3, -1, 0
1769 ; GFX10-NEXT: s_and_b32 s2, s2, s3
1770 ; GFX10-NEXT: v_mov_b32_e32 v1, s2
1771 ; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
1772 ; GFX10-NEXT: s_endpgm
1773 %c0 = icmp ugt i32 %a, 1
1774 %c1 = icmp ugt i32 %b, 2
1775 %src = and i1 %c0, %c1
1776 %result = call i32 @llvm.amdgcn.icmp.i1(i1 %src, i1 false, i32 33)
1777 store i32 %result, ptr addrspace(1) %out
1778 ret void
1779 }
1781 define amdgpu_ps void @test_intr_icmp_i32_invalid_cc(ptr addrspace(1) %out, i32 %src) {
1782 ; SDAG-GFX11-LABEL: test_intr_icmp_i32_invalid_cc:
1783 ; SDAG-GFX11: ; %bb.0:
1784 ; SDAG-GFX11-NEXT: s_endpgm
1785 ;
1786 ; SDAG-GFX10-LABEL: test_intr_icmp_i32_invalid_cc:
1787 ; SDAG-GFX10: ; %bb.0:
1788 ; SDAG-GFX10-NEXT: s_endpgm
1789 ;
1790 ; GISEL-GFX11-LABEL: test_intr_icmp_i32_invalid_cc:
1791 ; GISEL-GFX11: ; %bb.0:
1792 ; GISEL-GFX11-NEXT: global_store_b32 v[0:1], v0, off
1793 ; GISEL-GFX11-NEXT: s_nop 0
1794 ; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
1795 ; GISEL-GFX11-NEXT: s_endpgm
1796 ;
1797 ; GISEL-GFX10-LABEL: test_intr_icmp_i32_invalid_cc:
1798 ; GISEL-GFX10: ; %bb.0:
1799 ; GISEL-GFX10-NEXT: global_store_dword v[0:1], v0, off
1800 ; GISEL-GFX10-NEXT: s_endpgm
1801 %result = call i32 @llvm.amdgcn.icmp.i32(i32 %src, i32 100, i32 9999)
1802 store i32 %result, ptr addrspace(1) %out
1803 ret void
1804 }
1806 attributes #0 = { nounwind readnone convergent }
1807 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
1808 ; GCN: {{.*}}