| blob | 0ad454482c873d4dd55e7183aa12ba02b908da06 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefixes=VERDE %s
3 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefixes=PREGFX10 %s
4 ;RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefixes=GFX10 %s
5 ;RUN: llc < %s -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs | FileCheck -check-prefixes=GFX11 %s
7 define amdgpu_ps void @tbuffer_store(ptr addrspace(8) inreg, <4 x float>, <4 x float>, <4 x float>) {
8 ; VERDE-LABEL: tbuffer_store:
9 ; VERDE: ; %bb.0: ; %main_body
10 ; VERDE-NEXT: v_mov_b32_e32 v12, 0
11 ; VERDE-NEXT: tbuffer_store_format_xyzw v[0:3], v12, s[0:3], 0 format:[BUF_DATA_FORMAT_16_16_16_16,BUF_NUM_FORMAT_USCALED] idxen
12 ; VERDE-NEXT: tbuffer_store_format_xyzw v[4:7], v12, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_SSCALED] idxen glc
13 ; VERDE-NEXT: tbuffer_store_format_xyzw v[8:11], v12, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen slc
14 ; VERDE-NEXT: tbuffer_store_format_xyzw v[8:11], v12, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen glc
15 ; VERDE-NEXT: s_endpgm
16 ;
17 ; PREGFX10-LABEL: tbuffer_store:
18 ; PREGFX10: ; %bb.0: ; %main_body
19 ; PREGFX10-NEXT: v_mov_b32_e32 v12, 0
20 ; PREGFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v12, s[0:3], 0 format:[BUF_DATA_FORMAT_16_16_16_16,BUF_NUM_FORMAT_USCALED] idxen
21 ; PREGFX10-NEXT: tbuffer_store_format_xyzw v[4:7], v12, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_SSCALED] idxen glc
22 ; PREGFX10-NEXT: tbuffer_store_format_xyzw v[8:11], v12, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen slc
23 ; PREGFX10-NEXT: tbuffer_store_format_xyzw v[8:11], v12, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen glc
24 ; PREGFX10-NEXT: s_endpgm
25 ;
26 ; GFX10-LABEL: tbuffer_store:
27 ; GFX10: ; %bb.0: ; %main_body
28 ; GFX10-NEXT: v_mov_b32_e32 v12, 0
29 ; GFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v12, s[0:3], 0 format:[BUF_FMT_10_10_10_2_UNORM] idxen
30 ; GFX10-NEXT: tbuffer_store_format_xyzw v[4:7], v12, s[0:3], 0 format:[BUF_FMT_8_8_8_8_SINT] idxen glc
31 ; GFX10-NEXT: tbuffer_store_format_xyzw v[8:11], v12, s[0:3], 0 format:78 idxen slc
32 ; GFX10-NEXT: tbuffer_store_format_xyzw v[8:11], v12, s[0:3], 0 format:78 idxen glc dlc
33 ; GFX10-NEXT: s_endpgm
34 ;
35 ; GFX11-LABEL: tbuffer_store:
36 ; GFX11: ; %bb.0: ; %main_body
37 ; GFX11-NEXT: v_mov_b32_e32 v12, 0
38 ; GFX11-NEXT: s_clause 0x3
39 ; GFX11-NEXT: tbuffer_store_format_xyzw v[0:3], v12, s[0:3], 0 format:[BUF_FMT_8_8_8_8_USCALED] idxen
40 ; GFX11-NEXT: tbuffer_store_format_xyzw v[4:7], v12, s[0:3], 0 format:[BUF_FMT_32_32_32_32_UINT] idxen glc
41 ; GFX11-NEXT: tbuffer_store_format_xyzw v[8:11], v12, s[0:3], 0 format:78 idxen slc
42 ; GFX11-NEXT: tbuffer_store_format_xyzw v[8:11], v12, s[0:3], 0 format:78 idxen glc dlc
43 ; GFX11-NEXT: s_nop 0
44 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
45 ; GFX11-NEXT: s_endpgm
46 main_body:
47 %in1 = bitcast <4 x float> %1 to <4 x i32>
48 %in2 = bitcast <4 x float> %2 to <4 x i32>
49 %in3 = bitcast <4 x float> %3 to <4 x i32>
50 call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4i32(<4 x i32> %in1, ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 44, i32 0)
51 call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4i32(<4 x i32> %in2, ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 61, i32 1)
52 call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4i32(<4 x i32> %in3, ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 78, i32 2)
53 call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4f32(<4 x float> %3, ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 78, i32 5)
54 ret void
55 }
57 define amdgpu_ps void @tbuffer_store_immoffs(ptr addrspace(8) inreg, <4 x float>) {
58 ; VERDE-LABEL: tbuffer_store_immoffs:
59 ; VERDE: ; %bb.0: ; %main_body
60 ; VERDE-NEXT: v_mov_b32_e32 v4, 0
61 ; VERDE-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_DATA_FORMAT_16_16,BUF_NUM_FORMAT_FLOAT] idxen offset:42
62 ; VERDE-NEXT: s_endpgm
63 ;
64 ; PREGFX10-LABEL: tbuffer_store_immoffs:
65 ; PREGFX10: ; %bb.0: ; %main_body
66 ; PREGFX10-NEXT: v_mov_b32_e32 v4, 0
67 ; PREGFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_DATA_FORMAT_16_16,BUF_NUM_FORMAT_FLOAT] idxen offset:42
68 ; PREGFX10-NEXT: s_endpgm
69 ;
70 ; GFX10-LABEL: tbuffer_store_immoffs:
71 ; GFX10: ; %bb.0: ; %main_body
72 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
73 ; GFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:117 idxen offset:42
74 ; GFX10-NEXT: s_endpgm
75 ;
76 ; GFX11-LABEL: tbuffer_store_immoffs:
77 ; GFX11: ; %bb.0: ; %main_body
78 ; GFX11-NEXT: v_mov_b32_e32 v4, 0
79 ; GFX11-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:117 idxen offset:42
80 ; GFX11-NEXT: s_nop 0
81 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
82 ; GFX11-NEXT: s_endpgm
83 main_body:
84 %in1 = bitcast <4 x float> %1 to <4 x i32>
85 call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4i32(<4 x i32> %in1, ptr addrspace(8) %0, i32 0, i32 42, i32 0, i32 117, i32 0)
86 ret void
87 }
89 define amdgpu_ps void @tbuffer_store_scalar_and_imm_offs(ptr addrspace(8) inreg, <4 x float> %vdata, i32 inreg %soffset) {
90 ; VERDE-LABEL: tbuffer_store_scalar_and_imm_offs:
91 ; VERDE: ; %bb.0: ; %main_body
92 ; VERDE-NEXT: v_mov_b32_e32 v4, 0
93 ; VERDE-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], s4 format:[BUF_DATA_FORMAT_16_16,BUF_NUM_FORMAT_FLOAT] idxen offset:42
94 ; VERDE-NEXT: s_endpgm
95 ;
96 ; PREGFX10-LABEL: tbuffer_store_scalar_and_imm_offs:
97 ; PREGFX10: ; %bb.0: ; %main_body
98 ; PREGFX10-NEXT: v_mov_b32_e32 v4, 0
99 ; PREGFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], s4 format:[BUF_DATA_FORMAT_16_16,BUF_NUM_FORMAT_FLOAT] idxen offset:42
100 ; PREGFX10-NEXT: s_endpgm
101 ;
102 ; GFX10-LABEL: tbuffer_store_scalar_and_imm_offs:
103 ; GFX10: ; %bb.0: ; %main_body
104 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
105 ; GFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], s4 format:117 idxen offset:42
106 ; GFX10-NEXT: s_endpgm
107 ;
108 ; GFX11-LABEL: tbuffer_store_scalar_and_imm_offs:
109 ; GFX11: ; %bb.0: ; %main_body
110 ; GFX11-NEXT: v_mov_b32_e32 v4, 0
111 ; GFX11-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], s4 format:117 idxen offset:42
112 ; GFX11-NEXT: s_nop 0
113 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
114 ; GFX11-NEXT: s_endpgm
115 main_body:
116 %in1 = bitcast <4 x float> %vdata to <4 x i32>
117 call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4i32(<4 x i32> %in1, ptr addrspace(8) %0, i32 0, i32 42, i32 %soffset, i32 117, i32 0)
118 ret void
119 }
121 define amdgpu_ps void @buffer_store_idx(ptr addrspace(8) inreg, <4 x float> %vdata, i32 %vindex) {
122 ; VERDE-LABEL: buffer_store_idx:
123 ; VERDE: ; %bb.0: ; %main_body
124 ; VERDE-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_USCALED] idxen
125 ; VERDE-NEXT: s_endpgm
126 ;
127 ; PREGFX10-LABEL: buffer_store_idx:
128 ; PREGFX10: ; %bb.0: ; %main_body
129 ; PREGFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_USCALED] idxen
130 ; PREGFX10-NEXT: s_endpgm
131 ;
132 ; GFX10-LABEL: buffer_store_idx:
133 ; GFX10: ; %bb.0: ; %main_body
134 ; GFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SSCALED] idxen
135 ; GFX10-NEXT: s_endpgm
136 ;
137 ; GFX11-LABEL: buffer_store_idx:
138 ; GFX11: ; %bb.0: ; %main_body
139 ; GFX11-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_FMT_8_8_8_8_SINT] idxen
140 ; GFX11-NEXT: s_nop 0
141 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
142 ; GFX11-NEXT: s_endpgm
143 main_body:
144 %in1 = bitcast <4 x float> %vdata to <4 x i32>
145 call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4i32(<4 x i32> %in1, ptr addrspace(8) %0, i32 %vindex, i32 0, i32 0, i32 47, i32 0)
146 ret void
147 }
149 define amdgpu_ps void @buffer_store_ofs(ptr addrspace(8) inreg, <4 x float> %vdata, i32 %voffset) {
150 ; VERDE-LABEL: buffer_store_ofs:
151 ; VERDE: ; %bb.0: ; %main_body
152 ; VERDE-NEXT: s_mov_b32 s4, 0
153 ; VERDE-NEXT: v_mov_b32_e32 v5, v4
154 ; VERDE-NEXT: v_mov_b32_e32 v4, s4
155 ; VERDE-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_DATA_FORMAT_8_8,BUF_NUM_FORMAT_FLOAT] idxen offen
156 ; VERDE-NEXT: s_endpgm
157 ;
158 ; PREGFX10-LABEL: buffer_store_ofs:
159 ; PREGFX10: ; %bb.0: ; %main_body
160 ; PREGFX10-NEXT: s_mov_b32 s4, 0
161 ; PREGFX10-NEXT: v_mov_b32_e32 v5, v4
162 ; PREGFX10-NEXT: v_mov_b32_e32 v4, s4
163 ; PREGFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_DATA_FORMAT_8_8,BUF_NUM_FORMAT_FLOAT] idxen offen
164 ; PREGFX10-NEXT: s_endpgm
165 ;
166 ; GFX10-LABEL: buffer_store_ofs:
167 ; GFX10: ; %bb.0: ; %main_body
168 ; GFX10-NEXT: s_mov_b32 s4, 0
169 ; GFX10-NEXT: v_mov_b32_e32 v5, v4
170 ; GFX10-NEXT: v_mov_b32_e32 v4, s4
171 ; GFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:115 idxen offen
172 ; GFX10-NEXT: s_endpgm
173 ;
174 ; GFX11-LABEL: buffer_store_ofs:
175 ; GFX11: ; %bb.0: ; %main_body
176 ; GFX11-NEXT: s_mov_b32 s4, 0
177 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
178 ; GFX11-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, s4
179 ; GFX11-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:115 idxen offen
180 ; GFX11-NEXT: s_nop 0
181 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
182 ; GFX11-NEXT: s_endpgm
183 main_body:
184 %in1 = bitcast <4 x float> %vdata to <4 x i32>
185 call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4i32(<4 x i32> %in1, ptr addrspace(8) %0, i32 0, i32 %voffset, i32 0, i32 115, i32 0)
186 ret void
187 }
189 define amdgpu_ps void @buffer_store_both(ptr addrspace(8) inreg, <4 x float> %vdata, i32 %vindex, i32 %voffset) {
190 ; VERDE-LABEL: buffer_store_both:
191 ; VERDE: ; %bb.0: ; %main_body
192 ; VERDE-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_UINT] idxen offen
193 ; VERDE-NEXT: s_endpgm
194 ;
195 ; PREGFX10-LABEL: buffer_store_both:
196 ; PREGFX10: ; %bb.0: ; %main_body
197 ; PREGFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_UINT] idxen offen
198 ; PREGFX10-NEXT: s_endpgm
199 ;
200 ; GFX10-LABEL: buffer_store_both:
201 ; GFX10: ; %bb.0: ; %main_body
202 ; GFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_FMT_16_16_16_16_SINT] idxen offen
203 ; GFX10-NEXT: s_endpgm
204 ;
205 ; GFX11-LABEL: buffer_store_both:
206 ; GFX11: ; %bb.0: ; %main_body
207 ; GFX11-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:70 idxen offen
208 ; GFX11-NEXT: s_nop 0
209 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
210 ; GFX11-NEXT: s_endpgm
211 main_body:
212 %in1 = bitcast <4 x float> %vdata to <4 x i32>
213 call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4i32(<4 x i32> %in1, ptr addrspace(8) %0, i32 %vindex, i32 %voffset, i32 0, i32 70, i32 0)
214 ret void
215 }
217 define amdgpu_ps void @buffer_store_wait(ptr addrspace(8) inreg, <4 x float> %vdata, i32 %vindex.1, i32 %vindex.2, i32 %vindex.3) {
218 ; VERDE-LABEL: buffer_store_wait:
219 ; VERDE: ; %bb.0: ; %main_body
220 ; VERDE-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_SSCALED] idxen
221 ; VERDE-NEXT: s_waitcnt expcnt(0)
222 ; VERDE-NEXT: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen
223 ; VERDE-NEXT: s_waitcnt vmcnt(0)
224 ; VERDE-NEXT: tbuffer_store_format_xyzw v[0:3], v6, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_USCALED] idxen
225 ; VERDE-NEXT: s_endpgm
226 ;
227 ; PREGFX10-LABEL: buffer_store_wait:
228 ; PREGFX10: ; %bb.0: ; %main_body
229 ; PREGFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_SSCALED] idxen
230 ; PREGFX10-NEXT: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen
231 ; PREGFX10-NEXT: s_waitcnt vmcnt(0)
232 ; PREGFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v6, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_USCALED] idxen
233 ; PREGFX10-NEXT: s_endpgm
234 ;
235 ; GFX10-LABEL: buffer_store_wait:
236 ; GFX10: ; %bb.0: ; %main_body
237 ; GFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_FMT_32_32_SINT] idxen
238 ; GFX10-NEXT: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen
239 ; GFX10-NEXT: s_waitcnt vmcnt(0)
240 ; GFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v6, s[0:3], 0 format:[BUF_FMT_10_10_10_2_USCALED] idxen
241 ; GFX10-NEXT: s_endpgm
242 ;
243 ; GFX11-LABEL: buffer_store_wait:
244 ; GFX11: ; %bb.0: ; %main_body
245 ; GFX11-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_FMT_32_32_32_32_FLOAT] idxen
246 ; GFX11-NEXT: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen
247 ; GFX11-NEXT: s_waitcnt vmcnt(0)
248 ; GFX11-NEXT: tbuffer_store_format_xyzw v[0:3], v6, s[0:3], 0 format:[BUF_FMT_8_8_8_8_UINT] idxen
249 ; GFX11-NEXT: s_nop 0
250 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
251 ; GFX11-NEXT: s_endpgm
252 main_body:
253 %in1 = bitcast <4 x float> %vdata to <4 x i32>
254 call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4i32(<4 x i32> %in1, ptr addrspace(8) %0, i32 %vindex.1, i32 0, i32 0, i32 63, i32 0)
255 %data = call <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.format.v4f32(ptr addrspace(8) %0, i32 %vindex.2, i32 0, i32 0, i32 0)
256 %data.i = bitcast <4 x float> %data to <4 x i32>
257 call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4i32(<4 x i32> %data.i, ptr addrspace(8) %0, i32 %vindex.3, i32 0, i32 0, i32 46, i32 0)
258 ret void
259 }
261 define amdgpu_ps void @buffer_store_x1(ptr addrspace(8) inreg %rsrc, float %data, i32 %vindex) {
262 ; VERDE-LABEL: buffer_store_x1:
263 ; VERDE: ; %bb.0: ; %main_body
264 ; VERDE-NEXT: tbuffer_store_format_x v0, v1, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_FLOAT] idxen
265 ; VERDE-NEXT: s_endpgm
266 ;
267 ; PREGFX10-LABEL: buffer_store_x1:
268 ; PREGFX10: ; %bb.0: ; %main_body
269 ; PREGFX10-NEXT: tbuffer_store_format_x v0, v1, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_FLOAT] idxen
270 ; PREGFX10-NEXT: s_endpgm
271 ;
272 ; GFX10-LABEL: buffer_store_x1:
273 ; GFX10: ; %bb.0: ; %main_body
274 ; GFX10-NEXT: tbuffer_store_format_x v0, v1, s[0:3], 0 format:125 idxen
275 ; GFX10-NEXT: s_endpgm
276 ;
277 ; GFX11-LABEL: buffer_store_x1:
278 ; GFX11: ; %bb.0: ; %main_body
279 ; GFX11-NEXT: tbuffer_store_format_x v0, v1, s[0:3], 0 format:125 idxen
280 ; GFX11-NEXT: s_nop 0
281 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
282 ; GFX11-NEXT: s_endpgm
283 main_body:
284 %data.i = bitcast float %data to i32
285 call void @llvm.amdgcn.struct.ptr.tbuffer.store.i32(i32 %data.i, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 125, i32 0)
286 ret void
287 }
289 define amdgpu_ps void @buffer_store_x2(ptr addrspace(8) inreg %rsrc, <2 x float> %data, i32 %vindex) {
290 ; VERDE-LABEL: buffer_store_x2:
291 ; VERDE: ; %bb.0: ; %main_body
292 ; VERDE-NEXT: tbuffer_store_format_xy v[0:1], v2, s[0:3], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
293 ; VERDE-NEXT: s_endpgm
294 ;
295 ; PREGFX10-LABEL: buffer_store_x2:
296 ; PREGFX10: ; %bb.0: ; %main_body
297 ; PREGFX10-NEXT: tbuffer_store_format_xy v[0:1], v2, s[0:3], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
298 ; PREGFX10-NEXT: s_endpgm
299 ;
300 ; GFX10-LABEL: buffer_store_x2:
301 ; GFX10: ; %bb.0: ; %main_body
302 ; GFX10-NEXT: tbuffer_store_format_xy v[0:1], v2, s[0:3], 0 format:[BUF_FMT_10_11_11_SSCALED] idxen
303 ; GFX10-NEXT: s_endpgm
304 ;
305 ; GFX11-LABEL: buffer_store_x2:
306 ; GFX11: ; %bb.0: ; %main_body
307 ; GFX11-NEXT: tbuffer_store_format_xy v[0:1], v2, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM] idxen
308 ; GFX11-NEXT: s_nop 0
309 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
310 ; GFX11-NEXT: s_endpgm
311 main_body:
312 %data.i = bitcast <2 x float> %data to <2 x i32>
313 call void @llvm.amdgcn.struct.ptr.tbuffer.store.v2i32(<2 x i32> %data.i, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 33, i32 0)
314 ret void
315 }
317 define amdgpu_ps void @buffer_store_voffset_large_12bit(ptr addrspace(8) inreg %rsrc, <4 x float> %data) {
318 ; VERDE-LABEL: buffer_store_voffset_large_12bit:
319 ; VERDE: ; %bb.0: ; %main_body
320 ; VERDE-NEXT: v_mov_b32_e32 v4, 0
321 ; VERDE-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_SSCALED] idxen offset:4092
322 ; VERDE-NEXT: s_endpgm
323 ;
324 ; PREGFX10-LABEL: buffer_store_voffset_large_12bit:
325 ; PREGFX10: ; %bb.0: ; %main_body
326 ; PREGFX10-NEXT: v_mov_b32_e32 v4, 0
327 ; PREGFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_SSCALED] idxen offset:4092
328 ; PREGFX10-NEXT: s_endpgm
329 ;
330 ; GFX10-LABEL: buffer_store_voffset_large_12bit:
331 ; GFX10: ; %bb.0: ; %main_body
332 ; GFX10-NEXT: v_mov_b32_e32 v4, 0
333 ; GFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_FMT_32_32_SINT] idxen offset:4092
334 ; GFX10-NEXT: s_endpgm
335 ;
336 ; GFX11-LABEL: buffer_store_voffset_large_12bit:
337 ; GFX11: ; %bb.0: ; %main_body
338 ; GFX11-NEXT: v_mov_b32_e32 v4, 0
339 ; GFX11-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_FMT_32_32_32_32_FLOAT] idxen offset:4092
340 ; GFX11-NEXT: s_nop 0
341 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
342 ; GFX11-NEXT: s_endpgm
343 main_body:
344 call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4f32(<4 x float> %data, ptr addrspace(8) %rsrc, i32 0, i32 4092, i32 0, i32 63, i32 0)
345 ret void
346 }
348 define amdgpu_ps void @buffer_store_voffset_large_13bit(ptr addrspace(8) inreg %rsrc, <4 x float> %data) {
349 ; VERDE-LABEL: buffer_store_voffset_large_13bit:
350 ; VERDE: ; %bb.0: ; %main_body
351 ; VERDE-NEXT: s_mov_b32 s4, 0
352 ; VERDE-NEXT: v_mov_b32_e32 v5, 0x1000
353 ; VERDE-NEXT: v_mov_b32_e32 v4, s4
354 ; VERDE-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_SSCALED] idxen offen offset:4092
355 ; VERDE-NEXT: s_endpgm
356 ;
357 ; PREGFX10-LABEL: buffer_store_voffset_large_13bit:
358 ; PREGFX10: ; %bb.0: ; %main_body
359 ; PREGFX10-NEXT: s_mov_b32 s4, 0
360 ; PREGFX10-NEXT: v_mov_b32_e32 v5, 0x1000
361 ; PREGFX10-NEXT: v_mov_b32_e32 v4, s4
362 ; PREGFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_SSCALED] idxen offen offset:4092
363 ; PREGFX10-NEXT: s_endpgm
364 ;
365 ; GFX10-LABEL: buffer_store_voffset_large_13bit:
366 ; GFX10: ; %bb.0: ; %main_body
367 ; GFX10-NEXT: s_mov_b32 s4, 0
368 ; GFX10-NEXT: v_mov_b32_e32 v5, 0x1000
369 ; GFX10-NEXT: v_mov_b32_e32 v4, s4
370 ; GFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_FMT_32_32_SINT] idxen offen offset:4092
371 ; GFX10-NEXT: s_endpgm
372 ;
373 ; GFX11-LABEL: buffer_store_voffset_large_13bit:
374 ; GFX11: ; %bb.0: ; %main_body
375 ; GFX11-NEXT: s_mov_b32 s4, 0
376 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
377 ; GFX11-NEXT: v_dual_mov_b32 v5, 0x1000 :: v_dual_mov_b32 v4, s4
378 ; GFX11-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_FMT_32_32_32_32_FLOAT] idxen offen offset:4092
379 ; GFX11-NEXT: s_nop 0
380 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
381 ; GFX11-NEXT: s_endpgm
382 main_body:
383 call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4f32(<4 x float> %data, ptr addrspace(8) %rsrc, i32 0, i32 8188, i32 0, i32 63, i32 0)
384 ret void
385 }
387 define amdgpu_ps void @buffer_store_voffset_large_16bit(ptr addrspace(8) inreg %rsrc, <4 x float> %data) {
388 ; VERDE-LABEL: buffer_store_voffset_large_16bit:
389 ; VERDE: ; %bb.0: ; %main_body
390 ; VERDE-NEXT: s_mov_b32 s4, 0
391 ; VERDE-NEXT: v_mov_b32_e32 v5, 0xf000
392 ; VERDE-NEXT: v_mov_b32_e32 v4, s4
393 ; VERDE-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_SSCALED] idxen offen offset:4092
394 ; VERDE-NEXT: s_endpgm
395 ;
396 ; PREGFX10-LABEL: buffer_store_voffset_large_16bit:
397 ; PREGFX10: ; %bb.0: ; %main_body
398 ; PREGFX10-NEXT: s_mov_b32 s4, 0
399 ; PREGFX10-NEXT: v_mov_b32_e32 v5, 0xf000
400 ; PREGFX10-NEXT: v_mov_b32_e32 v4, s4
401 ; PREGFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_SSCALED] idxen offen offset:4092
402 ; PREGFX10-NEXT: s_endpgm
403 ;
404 ; GFX10-LABEL: buffer_store_voffset_large_16bit:
405 ; GFX10: ; %bb.0: ; %main_body
406 ; GFX10-NEXT: s_mov_b32 s4, 0
407 ; GFX10-NEXT: v_mov_b32_e32 v5, 0xf000
408 ; GFX10-NEXT: v_mov_b32_e32 v4, s4
409 ; GFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_FMT_32_32_SINT] idxen offen offset:4092
410 ; GFX10-NEXT: s_endpgm
411 ;
412 ; GFX11-LABEL: buffer_store_voffset_large_16bit:
413 ; GFX11: ; %bb.0: ; %main_body
414 ; GFX11-NEXT: s_mov_b32 s4, 0
415 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
416 ; GFX11-NEXT: v_dual_mov_b32 v5, 0xf000 :: v_dual_mov_b32 v4, s4
417 ; GFX11-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_FMT_32_32_32_32_FLOAT] idxen offen offset:4092
418 ; GFX11-NEXT: s_nop 0
419 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
420 ; GFX11-NEXT: s_endpgm
421 main_body:
422 call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4f32(<4 x float> %data, ptr addrspace(8) %rsrc, i32 0, i32 65532, i32 0, i32 63, i32 0)
423 ret void
424 }
426 define amdgpu_ps void @buffer_store_voffset_large_23bit(ptr addrspace(8) inreg %rsrc, <4 x float> %data) {
427 ; VERDE-LABEL: buffer_store_voffset_large_23bit:
428 ; VERDE: ; %bb.0: ; %main_body
429 ; VERDE-NEXT: s_mov_b32 s4, 0
430 ; VERDE-NEXT: v_mov_b32_e32 v5, 0x7ff000
431 ; VERDE-NEXT: v_mov_b32_e32 v4, s4
432 ; VERDE-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_SSCALED] idxen offen offset:4092
433 ; VERDE-NEXT: s_endpgm
434 ;
435 ; PREGFX10-LABEL: buffer_store_voffset_large_23bit:
436 ; PREGFX10: ; %bb.0: ; %main_body
437 ; PREGFX10-NEXT: s_mov_b32 s4, 0
438 ; PREGFX10-NEXT: v_mov_b32_e32 v5, 0x7ff000
439 ; PREGFX10-NEXT: v_mov_b32_e32 v4, s4
440 ; PREGFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_SSCALED] idxen offen offset:4092
441 ; PREGFX10-NEXT: s_endpgm
442 ;
443 ; GFX10-LABEL: buffer_store_voffset_large_23bit:
444 ; GFX10: ; %bb.0: ; %main_body
445 ; GFX10-NEXT: s_mov_b32 s4, 0
446 ; GFX10-NEXT: v_mov_b32_e32 v5, 0x7ff000
447 ; GFX10-NEXT: v_mov_b32_e32 v4, s4
448 ; GFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_FMT_32_32_SINT] idxen offen offset:4092
449 ; GFX10-NEXT: s_endpgm
450 ;
451 ; GFX11-LABEL: buffer_store_voffset_large_23bit:
452 ; GFX11: ; %bb.0: ; %main_body
453 ; GFX11-NEXT: s_mov_b32 s4, 0
454 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
455 ; GFX11-NEXT: v_dual_mov_b32 v5, 0x7ff000 :: v_dual_mov_b32 v4, s4
456 ; GFX11-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_FMT_32_32_32_32_FLOAT] idxen offen offset:4092
457 ; GFX11-NEXT: s_nop 0
458 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
459 ; GFX11-NEXT: s_endpgm
460 main_body:
461 call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4f32(<4 x float> %data, ptr addrspace(8) %rsrc, i32 0, i32 8388604, i32 0, i32 63, i32 0)
462 ret void
463 }
465 define amdgpu_ps void @buffer_store_voffset_large_24bit(ptr addrspace(8) inreg %rsrc, <4 x float> %data) {
466 ; VERDE-LABEL: buffer_store_voffset_large_24bit:
467 ; VERDE: ; %bb.0: ; %main_body
468 ; VERDE-NEXT: s_mov_b32 s4, 0
469 ; VERDE-NEXT: v_mov_b32_e32 v5, 0xfff000
470 ; VERDE-NEXT: v_mov_b32_e32 v4, s4
471 ; VERDE-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_SSCALED] idxen offen offset:4092
472 ; VERDE-NEXT: s_endpgm
473 ;
474 ; PREGFX10-LABEL: buffer_store_voffset_large_24bit:
475 ; PREGFX10: ; %bb.0: ; %main_body
476 ; PREGFX10-NEXT: s_mov_b32 s4, 0
477 ; PREGFX10-NEXT: v_mov_b32_e32 v5, 0xfff000
478 ; PREGFX10-NEXT: v_mov_b32_e32 v4, s4
479 ; PREGFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_SSCALED] idxen offen offset:4092
480 ; PREGFX10-NEXT: s_endpgm
481 ;
482 ; GFX10-LABEL: buffer_store_voffset_large_24bit:
483 ; GFX10: ; %bb.0: ; %main_body
484 ; GFX10-NEXT: s_mov_b32 s4, 0
485 ; GFX10-NEXT: v_mov_b32_e32 v5, 0xfff000
486 ; GFX10-NEXT: v_mov_b32_e32 v4, s4
487 ; GFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_FMT_32_32_SINT] idxen offen offset:4092
488 ; GFX10-NEXT: s_endpgm
489 ;
490 ; GFX11-LABEL: buffer_store_voffset_large_24bit:
491 ; GFX11: ; %bb.0: ; %main_body
492 ; GFX11-NEXT: s_mov_b32 s4, 0
493 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
494 ; GFX11-NEXT: v_dual_mov_b32 v5, 0xfff000 :: v_dual_mov_b32 v4, s4
495 ; GFX11-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_FMT_32_32_32_32_FLOAT] idxen offen offset:4092
496 ; GFX11-NEXT: s_nop 0
497 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
498 ; GFX11-NEXT: s_endpgm
499 main_body:
500 call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4f32(<4 x float> %data, ptr addrspace(8) %rsrc, i32 0, i32 16777212, i32 0, i32 63, i32 0)
501 ret void
502 }
504 declare void @llvm.amdgcn.struct.ptr.tbuffer.store.i32(i32, ptr addrspace(8), i32, i32, i32, i32, i32) #0
505 declare void @llvm.amdgcn.struct.ptr.tbuffer.store.v2i32(<2 x i32>, ptr addrspace(8), i32, i32, i32, i32, i32) #0
506 declare void @llvm.amdgcn.struct.ptr.tbuffer.store.v4i32(<4 x i32>, ptr addrspace(8), i32, i32, i32, i32, i32) #0
507 declare void @llvm.amdgcn.struct.ptr.tbuffer.store.v4f32(<4 x float>, ptr addrspace(8), i32, i32, i32, i32, i32) #0
508 declare <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.format.v4f32(ptr addrspace(8), i32, i32, i32, i32) #1
510 attributes #0 = { nounwind }
511 attributes #1 = { nounwind readonly }