| blob | 671ead6127308dd1605a68e805d75c4560a13979 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx704 < %s | FileCheck --check-prefixes=GFX7CHECK,GFX7SELDAG %s
3 ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx704 < %s | FileCheck --check-prefixes=GFX7CHECK,GFX7GLISEL %s
4 ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx803 < %s | FileCheck --check-prefixes=GFX8CHECK,GFX8SELDAG %s
5 ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx803 < %s | FileCheck --check-prefixes=GFX8CHECK,GFX8GLISEL %s
6 ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx908 < %s | FileCheck --check-prefixes=GFX9CHECK,GFX9SELDAG %s
7 ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx908 < %s | FileCheck --check-prefixes=GFX9CHECK,GFX9GLISEL %s
8 ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1031 < %s | FileCheck --check-prefixes=GFX10CHECK,GFX10SELDAG %s
9 ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1031 < %s | FileCheck --check-prefixes=GFX10CHECK,GFX10GLISEL %s
10 ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck --check-prefixes=GFX11CHECK,GFX11SELDAG %s
11 ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck --check-prefixes=GFX11CHECK,GFX11GLISEL %s
13 define amdgpu_kernel void @sgpr_isnan_f16(ptr addrspace(1) %out, half %x) {
14 ; GFX7SELDAG-LABEL: sgpr_isnan_f16:
15 ; GFX7SELDAG: ; %bb.0:
16 ; GFX7SELDAG-NEXT: s_load_dword s4, s[0:1], 0xb
17 ; GFX7SELDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
18 ; GFX7SELDAG-NEXT: s_mov_b32 s3, 0xf000
19 ; GFX7SELDAG-NEXT: s_mov_b32 s2, -1
20 ; GFX7SELDAG-NEXT: s_waitcnt lgkmcnt(0)
21 ; GFX7SELDAG-NEXT: s_and_b32 s4, s4, 0x7fff
22 ; GFX7SELDAG-NEXT: s_cmpk_gt_i32 s4, 0x7c00
23 ; GFX7SELDAG-NEXT: s_cselect_b64 s[4:5], -1, 0
24 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[4:5]
25 ; GFX7SELDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
26 ; GFX7SELDAG-NEXT: s_endpgm
27 ;
28 ; GFX7GLISEL-LABEL: sgpr_isnan_f16:
29 ; GFX7GLISEL: ; %bb.0:
30 ; GFX7GLISEL-NEXT: s_load_dword s3, s[0:1], 0xb
31 ; GFX7GLISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
32 ; GFX7GLISEL-NEXT: s_mov_b32 s2, -1
33 ; GFX7GLISEL-NEXT: s_waitcnt lgkmcnt(0)
34 ; GFX7GLISEL-NEXT: s_and_b32 s3, s3, 0x7fff
35 ; GFX7GLISEL-NEXT: s_and_b32 s3, 0xffff, s3
36 ; GFX7GLISEL-NEXT: s_cmpk_gt_u32 s3, 0x7c00
37 ; GFX7GLISEL-NEXT: s_cselect_b32 s3, 1, 0
38 ; GFX7GLISEL-NEXT: s_bfe_i32 s3, s3, 0x10000
39 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v0, s3
40 ; GFX7GLISEL-NEXT: s_mov_b32 s3, 0xf000
41 ; GFX7GLISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
42 ; GFX7GLISEL-NEXT: s_endpgm
43 ;
44 ; GFX8CHECK-LABEL: sgpr_isnan_f16:
45 ; GFX8CHECK: ; %bb.0:
46 ; GFX8CHECK-NEXT: s_load_dword s2, s[0:1], 0x2c
47 ; GFX8CHECK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
48 ; GFX8CHECK-NEXT: s_waitcnt lgkmcnt(0)
49 ; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[2:3], s2, 3
50 ; GFX8CHECK-NEXT: v_mov_b32_e32 v0, s0
51 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[2:3]
52 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, s1
53 ; GFX8CHECK-NEXT: flat_store_dword v[0:1], v2
54 ; GFX8CHECK-NEXT: s_endpgm
55 ;
56 ; GFX9CHECK-LABEL: sgpr_isnan_f16:
57 ; GFX9CHECK: ; %bb.0:
58 ; GFX9CHECK-NEXT: s_load_dword s4, s[0:1], 0x2c
59 ; GFX9CHECK-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
60 ; GFX9CHECK-NEXT: v_mov_b32_e32 v0, 0
61 ; GFX9CHECK-NEXT: s_waitcnt lgkmcnt(0)
62 ; GFX9CHECK-NEXT: v_cmp_class_f16_e64 s[0:1], s4, 3
63 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v1, 0, -1, s[0:1]
64 ; GFX9CHECK-NEXT: global_store_dword v0, v1, s[2:3]
65 ; GFX9CHECK-NEXT: s_endpgm
66 ;
67 ; GFX10CHECK-LABEL: sgpr_isnan_f16:
68 ; GFX10CHECK: ; %bb.0:
69 ; GFX10CHECK-NEXT: s_clause 0x1
70 ; GFX10CHECK-NEXT: s_load_dword s2, s[0:1], 0x2c
71 ; GFX10CHECK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
72 ; GFX10CHECK-NEXT: v_mov_b32_e32 v0, 0
73 ; GFX10CHECK-NEXT: s_waitcnt lgkmcnt(0)
74 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s2, s2, 3
75 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
76 ; GFX10CHECK-NEXT: global_store_dword v0, v1, s[0:1]
77 ; GFX10CHECK-NEXT: s_endpgm
78 ;
79 ; GFX11CHECK-LABEL: sgpr_isnan_f16:
80 ; GFX11CHECK: ; %bb.0:
81 ; GFX11CHECK-NEXT: s_clause 0x1
82 ; GFX11CHECK-NEXT: s_load_b32 s2, s[0:1], 0x2c
83 ; GFX11CHECK-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
84 ; GFX11CHECK-NEXT: v_mov_b32_e32 v0, 0
85 ; GFX11CHECK-NEXT: s_waitcnt lgkmcnt(0)
86 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s2, s2, 3
87 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
88 ; GFX11CHECK-NEXT: global_store_b32 v0, v1, s[0:1]
89 ; GFX11CHECK-NEXT: s_nop 0
90 ; GFX11CHECK-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
91 ; GFX11CHECK-NEXT: s_endpgm
92 %result = call i1 @llvm.is.fpclass.f16(half %x, i32 3)
93 %sext = sext i1 %result to i32
94 store i32 %sext, ptr addrspace(1) %out, align 4
95 ret void
96 }
98 define i1 @zeromask_f16(half %x) nounwind {
99 ; GFX7CHECK-LABEL: zeromask_f16:
100 ; GFX7CHECK: ; %bb.0:
101 ; GFX7CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
102 ; GFX7CHECK-NEXT: v_mov_b32_e32 v0, 0
103 ; GFX7CHECK-NEXT: s_setpc_b64 s[30:31]
104 ;
105 ; GFX8CHECK-LABEL: zeromask_f16:
106 ; GFX8CHECK: ; %bb.0:
107 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
108 ; GFX8CHECK-NEXT: v_mov_b32_e32 v0, 0
109 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
110 ;
111 ; GFX9CHECK-LABEL: zeromask_f16:
112 ; GFX9CHECK: ; %bb.0:
113 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
114 ; GFX9CHECK-NEXT: v_mov_b32_e32 v0, 0
115 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
116 ;
117 ; GFX10CHECK-LABEL: zeromask_f16:
118 ; GFX10CHECK: ; %bb.0:
119 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
120 ; GFX10CHECK-NEXT: v_mov_b32_e32 v0, 0
121 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
122 ;
123 ; GFX11CHECK-LABEL: zeromask_f16:
124 ; GFX11CHECK: ; %bb.0:
125 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
126 ; GFX11CHECK-NEXT: v_mov_b32_e32 v0, 0
127 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
128 %1 = call i1 @llvm.is.fpclass.f16(half %x, i32 0)
129 ret i1 %1
130 }
132 ; FIXME: DAG and GlobalISel return different values for i1 true
133 define i1 @allflags_f16(half %x) nounwind {
134 ; GFX7CHECK-LABEL: allflags_f16:
135 ; GFX7CHECK: ; %bb.0:
136 ; GFX7CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
137 ; GFX7CHECK-NEXT: v_mov_b32_e32 v0, 1
138 ; GFX7CHECK-NEXT: s_setpc_b64 s[30:31]
139 ;
140 ; GFX8CHECK-LABEL: allflags_f16:
141 ; GFX8CHECK: ; %bb.0:
142 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
143 ; GFX8CHECK-NEXT: v_mov_b32_e32 v0, 1
144 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
145 ;
146 ; GFX9CHECK-LABEL: allflags_f16:
147 ; GFX9CHECK: ; %bb.0:
148 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
149 ; GFX9CHECK-NEXT: v_mov_b32_e32 v0, 1
150 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
151 ;
152 ; GFX10CHECK-LABEL: allflags_f16:
153 ; GFX10CHECK: ; %bb.0:
154 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
155 ; GFX10CHECK-NEXT: v_mov_b32_e32 v0, 1
156 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
157 ;
158 ; GFX11CHECK-LABEL: allflags_f16:
159 ; GFX11CHECK: ; %bb.0:
160 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
161 ; GFX11CHECK-NEXT: v_mov_b32_e32 v0, 1
162 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
163 %1 = call i1 @llvm.is.fpclass.f16(half %x, i32 1023) ; 0x3ff
164 ret i1 %1
165 }
167 define i1 @snan_f16(half %x) nounwind {
168 ; GFX7SELDAG-LABEL: snan_f16:
169 ; GFX7SELDAG: ; %bb.0:
170 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
171 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
172 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7e00
173 ; GFX7SELDAG-NEXT: s_movk_i32 s5, 0x7c00
174 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
175 ; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
176 ; GFX7SELDAG-NEXT: v_cmp_lt_i32_e64 s[4:5], s5, v0
177 ; GFX7SELDAG-NEXT: s_and_b64 s[4:5], s[4:5], vcc
178 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
179 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
180 ;
181 ; GFX7GLISEL-LABEL: snan_f16:
182 ; GFX7GLISEL: ; %bb.0:
183 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
184 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
185 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
186 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
187 ; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v0, v1
188 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7e00
189 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], v0, v1
190 ; GFX7GLISEL-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
191 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
192 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
193 ;
194 ; GFX8CHECK-LABEL: snan_f16:
195 ; GFX8CHECK: ; %bb.0:
196 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
197 ; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 1
198 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
199 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
200 ;
201 ; GFX9CHECK-LABEL: snan_f16:
202 ; GFX9CHECK: ; %bb.0:
203 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
204 ; GFX9CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 1
205 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
206 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
207 ;
208 ; GFX10CHECK-LABEL: snan_f16:
209 ; GFX10CHECK: ; %bb.0:
210 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
211 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 1
212 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
213 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
214 ;
215 ; GFX11CHECK-LABEL: snan_f16:
216 ; GFX11CHECK: ; %bb.0:
217 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
218 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 1
219 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
220 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
221 %1 = call i1 @llvm.is.fpclass.f16(half %x, i32 1) ; 0x001
222 ret i1 %1
223 }
225 define i1 @qnan_f16(half %x) nounwind {
226 ; GFX7SELDAG-LABEL: qnan_f16:
227 ; GFX7SELDAG: ; %bb.0:
228 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
229 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
230 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7dff
231 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
232 ; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
233 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
234 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
235 ;
236 ; GFX7GLISEL-LABEL: qnan_f16:
237 ; GFX7GLISEL: ; %bb.0:
238 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
239 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
240 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
241 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7e00
242 ; GFX7GLISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
243 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
244 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
245 ;
246 ; GFX8CHECK-LABEL: qnan_f16:
247 ; GFX8CHECK: ; %bb.0:
248 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
249 ; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 2
250 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
251 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
252 ;
253 ; GFX9CHECK-LABEL: qnan_f16:
254 ; GFX9CHECK: ; %bb.0:
255 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
256 ; GFX9CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 2
257 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
258 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
259 ;
260 ; GFX10CHECK-LABEL: qnan_f16:
261 ; GFX10CHECK: ; %bb.0:
262 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
263 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 2
264 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
265 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
266 ;
267 ; GFX11CHECK-LABEL: qnan_f16:
268 ; GFX11CHECK: ; %bb.0:
269 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
270 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 2
271 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
272 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
273 %1 = call i1 @llvm.is.fpclass.f16(half %x, i32 2) ; 0x002
274 ret i1 %1
275 }
277 define i1 @posinf_f16(half %x) nounwind {
278 ; GFX7SELDAG-LABEL: posinf_f16:
279 ; GFX7SELDAG: ; %bb.0:
280 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
281 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
282 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
283 ; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, s4, v0
284 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
285 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
286 ;
287 ; GFX7GLISEL-LABEL: posinf_f16:
288 ; GFX7GLISEL: ; %bb.0:
289 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
290 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
291 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
292 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
293 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
294 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
295 ;
296 ; GFX8CHECK-LABEL: posinf_f16:
297 ; GFX8CHECK: ; %bb.0:
298 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
299 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x200
300 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
301 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
302 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
303 ;
304 ; GFX9CHECK-LABEL: posinf_f16:
305 ; GFX9CHECK: ; %bb.0:
306 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
307 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x200
308 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
309 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
310 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
311 ;
312 ; GFX10CHECK-LABEL: posinf_f16:
313 ; GFX10CHECK: ; %bb.0:
314 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
315 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x200
316 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
317 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
318 ;
319 ; GFX11CHECK-LABEL: posinf_f16:
320 ; GFX11CHECK: ; %bb.0:
321 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
322 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x200
323 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
324 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
325 %1 = call i1 @llvm.is.fpclass.f16(half %x, i32 512) ; 0x200
326 ret i1 %1
327 }
329 define i1 @neginf_f16(half %x) nounwind {
330 ; GFX7SELDAG-LABEL: neginf_f16:
331 ; GFX7SELDAG: ; %bb.0:
332 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
333 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
334 ; GFX7SELDAG-NEXT: s_mov_b32 s4, 0xfc00
335 ; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, s4, v0
336 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
337 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
338 ;
339 ; GFX7GLISEL-LABEL: neginf_f16:
340 ; GFX7GLISEL: ; %bb.0:
341 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
342 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
343 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0xfc00
344 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
345 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
346 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
347 ;
348 ; GFX8CHECK-LABEL: neginf_f16:
349 ; GFX8CHECK: ; %bb.0:
350 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
351 ; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 4
352 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
353 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
354 ;
355 ; GFX9CHECK-LABEL: neginf_f16:
356 ; GFX9CHECK: ; %bb.0:
357 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
358 ; GFX9CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 4
359 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
360 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
361 ;
362 ; GFX10CHECK-LABEL: neginf_f16:
363 ; GFX10CHECK: ; %bb.0:
364 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
365 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 4
366 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
367 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
368 ;
369 ; GFX11CHECK-LABEL: neginf_f16:
370 ; GFX11CHECK: ; %bb.0:
371 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
372 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 4
373 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
374 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
375 %1 = call i1 @llvm.is.fpclass.f16(half %x, i32 4) ; 0x004
376 ret i1 %1
377 }
379 define i1 @posnormal_f16(half %x) nounwind {
380 ; GFX7SELDAG-LABEL: posnormal_f16:
381 ; GFX7SELDAG: ; %bb.0:
382 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
383 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
384 ; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x7800
385 ; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
386 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
387 ; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
388 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
389 ; GFX7SELDAG-NEXT: v_cmp_lt_i32_e64 s[4:5], -1, v1
390 ; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s6, v0
391 ; GFX7SELDAG-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
392 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
393 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
394 ;
395 ; GFX7GLISEL-LABEL: posnormal_f16:
396 ; GFX7GLISEL: ; %bb.0:
397 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
398 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
399 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
400 ; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0xffff, v1
401 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v0, v2
402 ; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v1
403 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
404 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
405 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
406 ; GFX7GLISEL-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
407 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
408 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
409 ;
410 ; GFX8CHECK-LABEL: posnormal_f16:
411 ; GFX8CHECK: ; %bb.0:
412 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
413 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x100
414 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
415 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
416 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
417 ;
418 ; GFX9CHECK-LABEL: posnormal_f16:
419 ; GFX9CHECK: ; %bb.0:
420 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
421 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x100
422 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
423 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
424 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
425 ;
426 ; GFX10CHECK-LABEL: posnormal_f16:
427 ; GFX10CHECK: ; %bb.0:
428 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
429 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x100
430 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
431 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
432 ;
433 ; GFX11CHECK-LABEL: posnormal_f16:
434 ; GFX11CHECK: ; %bb.0:
435 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
436 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x100
437 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
438 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
439 %1 = call i1 @llvm.is.fpclass.f16(half %x, i32 256) ; 0x100
440 ret i1 %1
441 }
443 define i1 @negnormal_f16(half %x) nounwind {
444 ; GFX7SELDAG-LABEL: negnormal_f16:
445 ; GFX7SELDAG: ; %bb.0:
446 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
447 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
448 ; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x7800
449 ; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
450 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
451 ; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
452 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
453 ; GFX7SELDAG-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v1
454 ; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s6, v0
455 ; GFX7SELDAG-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
456 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
457 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
458 ;
459 ; GFX7GLISEL-LABEL: negnormal_f16:
460 ; GFX7GLISEL: ; %bb.0:
461 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
462 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
463 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
464 ; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0xffff, v1
465 ; GFX7GLISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], v0, v2
466 ; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v1
467 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
468 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
469 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
470 ; GFX7GLISEL-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
471 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
472 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
473 ;
474 ; GFX8CHECK-LABEL: negnormal_f16:
475 ; GFX8CHECK: ; %bb.0:
476 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
477 ; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 8
478 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
479 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
480 ;
481 ; GFX9CHECK-LABEL: negnormal_f16:
482 ; GFX9CHECK: ; %bb.0:
483 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
484 ; GFX9CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 8
485 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
486 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
487 ;
488 ; GFX10CHECK-LABEL: negnormal_f16:
489 ; GFX10CHECK: ; %bb.0:
490 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
491 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 8
492 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
493 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
494 ;
495 ; GFX11CHECK-LABEL: negnormal_f16:
496 ; GFX11CHECK: ; %bb.0:
497 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
498 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 8
499 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
500 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
501 %1 = call i1 @llvm.is.fpclass.f16(half %x, i32 8) ; 0x008
502 ret i1 %1
503 }
505 define i1 @possubnormal_f16(half %x) nounwind {
506 ; GFX7SELDAG-LABEL: possubnormal_f16:
507 ; GFX7SELDAG: ; %bb.0:
508 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
509 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
510 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x3ff
511 ; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, -1, v0
512 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
513 ; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
514 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
515 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
516 ;
517 ; GFX7GLISEL-LABEL: possubnormal_f16:
518 ; GFX7GLISEL: ; %bb.0:
519 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
520 ; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 1, v0
521 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
522 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x3ff
523 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
524 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
525 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
526 ;
527 ; GFX8CHECK-LABEL: possubnormal_f16:
528 ; GFX8CHECK: ; %bb.0:
529 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
530 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x80
531 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
532 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
533 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
534 ;
535 ; GFX9CHECK-LABEL: possubnormal_f16:
536 ; GFX9CHECK: ; %bb.0:
537 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
538 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x80
539 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
540 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
541 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
542 ;
543 ; GFX10CHECK-LABEL: possubnormal_f16:
544 ; GFX10CHECK: ; %bb.0:
545 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
546 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x80
547 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
548 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
549 ;
550 ; GFX11CHECK-LABEL: possubnormal_f16:
551 ; GFX11CHECK: ; %bb.0:
552 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
553 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x80
554 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
555 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
556 %1 = call i1 @llvm.is.fpclass.f16(half %x, i32 128) ; 0x080
557 ret i1 %1
558 }
560 define i1 @negsubnormal_f16(half %x) nounwind {
561 ; GFX7SELDAG-LABEL: negsubnormal_f16:
562 ; GFX7SELDAG: ; %bb.0:
563 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
564 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
565 ; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
566 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
567 ; GFX7SELDAG-NEXT: v_add_i32_e64 v0, s[4:5], -1, v0
568 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x3ff
569 ; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1
570 ; GFX7SELDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], s4, v0
571 ; GFX7SELDAG-NEXT: s_and_b64 s[4:5], s[4:5], vcc
572 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
573 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
574 ;
575 ; GFX7GLISEL-LABEL: negsubnormal_f16:
576 ; GFX7GLISEL: ; %bb.0:
577 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
578 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
579 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
580 ; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0xffff, v1
581 ; GFX7GLISEL-NEXT: v_cmp_ne_u32_e32 vcc, v0, v2
582 ; GFX7GLISEL-NEXT: v_subrev_i32_e64 v0, s[4:5], 1, v1
583 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
584 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x3ff
585 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], v0, v1
586 ; GFX7GLISEL-NEXT: s_and_b64 s[4:5], s[4:5], vcc
587 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
588 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
589 ;
590 ; GFX8CHECK-LABEL: negsubnormal_f16:
591 ; GFX8CHECK: ; %bb.0:
592 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
593 ; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 16
594 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
595 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
596 ;
597 ; GFX9CHECK-LABEL: negsubnormal_f16:
598 ; GFX9CHECK: ; %bb.0:
599 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
600 ; GFX9CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 16
601 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
602 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
603 ;
604 ; GFX10CHECK-LABEL: negsubnormal_f16:
605 ; GFX10CHECK: ; %bb.0:
606 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
607 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 16
608 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
609 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
610 ;
611 ; GFX11CHECK-LABEL: negsubnormal_f16:
612 ; GFX11CHECK: ; %bb.0:
613 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
614 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 16
615 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
616 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
617 %1 = call i1 @llvm.is.fpclass.f16(half %x, i32 16) ; 0x010
618 ret i1 %1
619 }
621 define i1 @poszero_f16(half %x) nounwind {
622 ; GFX7SELDAG-LABEL: poszero_f16:
623 ; GFX7SELDAG: ; %bb.0:
624 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
625 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
626 ; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
627 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
628 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
629 ;
630 ; GFX7GLISEL-LABEL: poszero_f16:
631 ; GFX7GLISEL: ; %bb.0:
632 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
633 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
634 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
635 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
636 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
637 ;
638 ; GFX8CHECK-LABEL: poszero_f16:
639 ; GFX8CHECK: ; %bb.0:
640 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
641 ; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 64
642 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
643 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
644 ;
645 ; GFX9CHECK-LABEL: poszero_f16:
646 ; GFX9CHECK: ; %bb.0:
647 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
648 ; GFX9CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 64
649 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
650 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
651 ;
652 ; GFX10CHECK-LABEL: poszero_f16:
653 ; GFX10CHECK: ; %bb.0:
654 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
655 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 64
656 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
657 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
658 ;
659 ; GFX11CHECK-LABEL: poszero_f16:
660 ; GFX11CHECK: ; %bb.0:
661 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
662 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 64
663 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
664 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
665 %1 = call i1 @llvm.is.fpclass.f16(half %x, i32 64) ; 0x040
666 ret i1 %1
667 }
669 define i1 @negzero_f16(half %x) nounwind {
670 ; GFX7SELDAG-LABEL: negzero_f16:
671 ; GFX7SELDAG: ; %bb.0:
672 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
673 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
674 ; GFX7SELDAG-NEXT: s_mov_b32 s4, 0x8000
675 ; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, s4, v0
676 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
677 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
678 ;
679 ; GFX7GLISEL-LABEL: negzero_f16:
680 ; GFX7GLISEL: ; %bb.0:
681 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
682 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
683 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x8000
684 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
685 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
686 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
687 ;
688 ; GFX8CHECK-LABEL: negzero_f16:
689 ; GFX8CHECK: ; %bb.0:
690 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
691 ; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 32
692 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
693 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
694 ;
695 ; GFX9CHECK-LABEL: negzero_f16:
696 ; GFX9CHECK: ; %bb.0:
697 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
698 ; GFX9CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 32
699 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
700 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
701 ;
702 ; GFX10CHECK-LABEL: negzero_f16:
703 ; GFX10CHECK: ; %bb.0:
704 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
705 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 32
706 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
707 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
708 ;
709 ; GFX11CHECK-LABEL: negzero_f16:
710 ; GFX11CHECK: ; %bb.0:
711 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
712 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 32
713 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
714 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
715 %1 = call i1 @llvm.is.fpclass.f16(half %x, i32 32) ; 0x020
716 ret i1 %1
717 }
719 define i1 @posfinite_f16(half %x) nounwind {
720 ; GFX7SELDAG-LABEL: posfinite_f16:
721 ; GFX7SELDAG: ; %bb.0:
722 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
723 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
724 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
725 ; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
726 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
727 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
728 ;
729 ; GFX7GLISEL-LABEL: posfinite_f16:
730 ; GFX7GLISEL: ; %bb.0:
731 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
732 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
733 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
734 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
735 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
736 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
737 ;
738 ; GFX8CHECK-LABEL: posfinite_f16:
739 ; GFX8CHECK: ; %bb.0:
740 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
741 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x1c0
742 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
743 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
744 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
745 ;
746 ; GFX9CHECK-LABEL: posfinite_f16:
747 ; GFX9CHECK: ; %bb.0:
748 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
749 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x1c0
750 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
751 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
752 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
753 ;
754 ; GFX10CHECK-LABEL: posfinite_f16:
755 ; GFX10CHECK: ; %bb.0:
756 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
757 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x1c0
758 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
759 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
760 ;
761 ; GFX11CHECK-LABEL: posfinite_f16:
762 ; GFX11CHECK: ; %bb.0:
763 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
764 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x1c0
765 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
766 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
767 %1 = call i1 @llvm.is.fpclass.f16(half %x, i32 448) ; 0x1c0
768 ret i1 %1
769 }
771 define i1 @negfinite_f16(half %x) nounwind {
772 ; GFX7SELDAG-LABEL: negfinite_f16:
773 ; GFX7SELDAG: ; %bb.0:
774 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
775 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
776 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
777 ; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
778 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
779 ; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1
780 ; GFX7SELDAG-NEXT: v_cmp_gt_i32_e64 s[4:5], s4, v0
781 ; GFX7SELDAG-NEXT: s_and_b64 s[4:5], s[4:5], vcc
782 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
783 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
784 ;
785 ; GFX7GLISEL-LABEL: negfinite_f16:
786 ; GFX7GLISEL: ; %bb.0:
787 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
788 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
789 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
790 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
791 ; GFX7GLISEL-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
792 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v0, 0x7c00
793 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], v1, v0
794 ; GFX7GLISEL-NEXT: s_and_b64 s[4:5], s[4:5], vcc
795 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
796 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
797 ;
798 ; GFX8CHECK-LABEL: negfinite_f16:
799 ; GFX8CHECK: ; %bb.0:
800 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
801 ; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 56
802 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
803 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
804 ;
805 ; GFX9CHECK-LABEL: negfinite_f16:
806 ; GFX9CHECK: ; %bb.0:
807 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
808 ; GFX9CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 56
809 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
810 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
811 ;
812 ; GFX10CHECK-LABEL: negfinite_f16:
813 ; GFX10CHECK: ; %bb.0:
814 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
815 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 56
816 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
817 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
818 ;
819 ; GFX11CHECK-LABEL: negfinite_f16:
820 ; GFX11CHECK: ; %bb.0:
821 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
822 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 56
823 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
824 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
825 %1 = call i1 @llvm.is.fpclass.f16(half %x, i32 56) ; 0x038
826 ret i1 %1
827 }
829 define i1 @isnan_f16(half %x) nounwind {
830 ; GFX7SELDAG-LABEL: isnan_f16:
831 ; GFX7SELDAG: ; %bb.0:
832 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
833 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
834 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
835 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
836 ; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
837 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
838 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
839 ;
840 ; GFX7GLISEL-LABEL: isnan_f16:
841 ; GFX7GLISEL: ; %bb.0:
842 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
843 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
844 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
845 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
846 ; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v0, v1
847 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
848 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
849 ;
850 ; GFX8CHECK-LABEL: isnan_f16:
851 ; GFX8CHECK: ; %bb.0:
852 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
853 ; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 3
854 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
855 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
856 ;
857 ; GFX9CHECK-LABEL: isnan_f16:
858 ; GFX9CHECK: ; %bb.0:
859 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
860 ; GFX9CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 3
861 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
862 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
863 ;
864 ; GFX10CHECK-LABEL: isnan_f16:
865 ; GFX10CHECK: ; %bb.0:
866 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
867 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 3
868 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
869 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
870 ;
871 ; GFX11CHECK-LABEL: isnan_f16:
872 ; GFX11CHECK: ; %bb.0:
873 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
874 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 3
875 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
876 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
877 %1 = call i1 @llvm.is.fpclass.f16(half %x, i32 3) ; nan
878 ret i1 %1
879 }
881 define i1 @not_isnan_f16(half %x) {
882 ; GFX7SELDAG-LABEL: not_isnan_f16:
883 ; GFX7SELDAG: ; %bb.0:
884 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
885 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
886 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c01
887 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
888 ; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
889 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
890 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
891 ;
892 ; GFX7GLISEL-LABEL: not_isnan_f16:
893 ; GFX7GLISEL: ; %bb.0:
894 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
895 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
896 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
897 ; GFX7GLISEL-NEXT: s_movk_i32 s4, 0x7c00
898 ; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
899 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s4, v0
900 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
901 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
902 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
903 ;
904 ; GFX8CHECK-LABEL: not_isnan_f16:
905 ; GFX8CHECK: ; %bb.0:
906 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
907 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x3fc
908 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
909 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
910 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
911 ;
912 ; GFX9CHECK-LABEL: not_isnan_f16:
913 ; GFX9CHECK: ; %bb.0:
914 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
915 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x3fc
916 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
917 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
918 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
919 ;
920 ; GFX10CHECK-LABEL: not_isnan_f16:
921 ; GFX10CHECK: ; %bb.0:
922 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
923 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x3fc
924 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
925 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
926 ;
927 ; GFX11CHECK-LABEL: not_isnan_f16:
928 ; GFX11CHECK: ; %bb.0:
929 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
930 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x3fc
931 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
932 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
933 %class = call i1 @llvm.is.fpclass.f16(half %x, i32 1020) ; ~nan
934 ret i1 %class
935 }
937 define <2 x i1> @isnan_v2f16(<2 x half> %x) nounwind {
938 ; GFX7SELDAG-LABEL: isnan_v2f16:
939 ; GFX7SELDAG: ; %bb.0:
940 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
941 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
942 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
943 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
944 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
945 ; GFX7SELDAG-NEXT: v_and_b32_e32 v1, 0x7fff, v1
946 ; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
947 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
948 ; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v1
949 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
950 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
951 ;
952 ; GFX7GLISEL-LABEL: isnan_v2f16:
953 ; GFX7GLISEL: ; %bb.0:
954 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
955 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
956 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
957 ; GFX7GLISEL-NEXT: s_movk_i32 s4, 0x7c00
958 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v1
959 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
960 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s4, v0
961 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
962 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s4, v1
963 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
964 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
965 ;
966 ; GFX8CHECK-LABEL: isnan_v2f16:
967 ; GFX8CHECK: ; %bb.0:
968 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
969 ; GFX8CHECK-NEXT: v_lshrrev_b32_e32 v1, 16, v0
970 ; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 3
971 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
972 ; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v1, 3
973 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
974 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
975 ;
976 ; GFX9CHECK-LABEL: isnan_v2f16:
977 ; GFX9CHECK: ; %bb.0:
978 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
979 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 3
980 ; GFX9CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 3
981 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
982 ; GFX9CHECK-NEXT: v_cmp_class_f16_sdwa s[4:5], v0, v1 src0_sel:WORD_1 src1_sel:DWORD
983 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
984 ; GFX9CHECK-NEXT: v_mov_b32_e32 v0, v2
985 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
986 ;
987 ; GFX10CHECK-LABEL: isnan_v2f16:
988 ; GFX10CHECK: ; %bb.0:
989 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
990 ; GFX10CHECK-NEXT: v_mov_b32_e32 v1, 3
991 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 3
992 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
993 ; GFX10CHECK-NEXT: v_cmp_class_f16_sdwa s4, v0, v1 src0_sel:WORD_1 src1_sel:DWORD
994 ; GFX10CHECK-NEXT: v_mov_b32_e32 v0, v2
995 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
996 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
997 ;
998 ; GFX11CHECK-LABEL: isnan_v2f16:
999 ; GFX11CHECK: ; %bb.0:
1000 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1001 ; GFX11CHECK-NEXT: v_lshrrev_b32_e32 v1, 16, v0
1002 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 3
1003 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
1004 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v1, 3
1005 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
1006 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
1007 %1 = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> %x, i32 3) ; nan
1008 ret <2 x i1> %1
1009 }
1011 define <3 x i1> @isnan_v3f16(<3 x half> %x) nounwind {
1012 ; GFX7SELDAG-LABEL: isnan_v3f16:
1013 ; GFX7SELDAG: ; %bb.0:
1014 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1015 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
1016 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
1017 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v2, v2
1018 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
1019 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
1020 ; GFX7SELDAG-NEXT: v_and_b32_e32 v1, 0x7fff, v1
1021 ; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
1022 ; GFX7SELDAG-NEXT: v_and_b32_e32 v2, 0x7fff, v2
1023 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1024 ; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v1
1025 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
1026 ; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v2
1027 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
1028 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
1029 ;
1030 ; GFX7GLISEL-LABEL: isnan_v3f16:
1031 ; GFX7GLISEL: ; %bb.0:
1032 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1033 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
1034 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
1035 ; GFX7GLISEL-NEXT: s_movk_i32 s4, 0x7c00
1036 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v1
1037 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
1038 ; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0x7fff, v2
1039 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s4, v0
1040 ; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
1041 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1042 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s4, v1
1043 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
1044 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s4, v2
1045 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
1046 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
1047 ;
1048 ; GFX8SELDAG-LABEL: isnan_v3f16:
1049 ; GFX8SELDAG: ; %bb.0:
1050 ; GFX8SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1051 ; GFX8SELDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
1052 ; GFX8SELDAG-NEXT: v_cmp_u_f16_e32 vcc, v2, v2
1053 ; GFX8SELDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
1054 ; GFX8SELDAG-NEXT: v_cmp_u_f16_e32 vcc, v0, v0
1055 ; GFX8SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1056 ; GFX8SELDAG-NEXT: v_cmp_u_f16_e32 vcc, v1, v1
1057 ; GFX8SELDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
1058 ; GFX8SELDAG-NEXT: v_mov_b32_e32 v1, v3
1059 ; GFX8SELDAG-NEXT: s_setpc_b64 s[30:31]
1060 ;
1061 ; GFX8GLISEL-LABEL: isnan_v3f16:
1062 ; GFX8GLISEL: ; %bb.0:
1063 ; GFX8GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1064 ; GFX8GLISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
1065 ; GFX8GLISEL-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 3
1066 ; GFX8GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
1067 ; GFX8GLISEL-NEXT: v_cmp_class_f16_e64 s[4:5], v2, 3
1068 ; GFX8GLISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5]
1069 ; GFX8GLISEL-NEXT: v_cmp_class_f16_e64 s[4:5], v1, 3
1070 ; GFX8GLISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
1071 ; GFX8GLISEL-NEXT: v_mov_b32_e32 v1, v3
1072 ; GFX8GLISEL-NEXT: s_setpc_b64 s[30:31]
1073 ;
1074 ; GFX9SELDAG-LABEL: isnan_v3f16:
1075 ; GFX9SELDAG: ; %bb.0:
1076 ; GFX9SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1077 ; GFX9SELDAG-NEXT: v_cmp_u_f16_sdwa s[4:5], v0, v0 src0_sel:WORD_1 src1_sel:WORD_1
1078 ; GFX9SELDAG-NEXT: v_cmp_u_f16_e32 vcc, v0, v0
1079 ; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5]
1080 ; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1081 ; GFX9SELDAG-NEXT: v_cmp_u_f16_e32 vcc, v1, v1
1082 ; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
1083 ; GFX9SELDAG-NEXT: v_mov_b32_e32 v1, v3
1084 ; GFX9SELDAG-NEXT: s_setpc_b64 s[30:31]
1085 ;
1086 ; GFX9GLISEL-LABEL: isnan_v3f16:
1087 ; GFX9GLISEL: ; %bb.0:
1088 ; GFX9GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1089 ; GFX9GLISEL-NEXT: v_mov_b32_e32 v2, 3
1090 ; GFX9GLISEL-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 3
1091 ; GFX9GLISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
1092 ; GFX9GLISEL-NEXT: v_cmp_class_f16_sdwa s[4:5], v0, v2 src0_sel:WORD_1 src1_sel:DWORD
1093 ; GFX9GLISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5]
1094 ; GFX9GLISEL-NEXT: v_cmp_class_f16_e64 s[4:5], v1, 3
1095 ; GFX9GLISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
1096 ; GFX9GLISEL-NEXT: v_mov_b32_e32 v0, v4
1097 ; GFX9GLISEL-NEXT: v_mov_b32_e32 v1, v3
1098 ; GFX9GLISEL-NEXT: s_setpc_b64 s[30:31]
1099 ;
1100 ; GFX10SELDAG-LABEL: isnan_v3f16:
1101 ; GFX10SELDAG: ; %bb.0:
1102 ; GFX10SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1103 ; GFX10SELDAG-NEXT: v_cmp_u_f16_sdwa s4, v0, v0 src0_sel:WORD_1 src1_sel:WORD_1
1104 ; GFX10SELDAG-NEXT: v_cmp_u_f16_e32 vcc_lo, v0, v0
1105 ; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
1106 ; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
1107 ; GFX10SELDAG-NEXT: v_cmp_u_f16_e32 vcc_lo, v1, v1
1108 ; GFX10SELDAG-NEXT: v_mov_b32_e32 v1, v3
1109 ; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
1110 ; GFX10SELDAG-NEXT: s_setpc_b64 s[30:31]
1111 ;
1112 ; GFX10GLISEL-LABEL: isnan_v3f16:
1113 ; GFX10GLISEL: ; %bb.0:
1114 ; GFX10GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1115 ; GFX10GLISEL-NEXT: v_mov_b32_e32 v2, 3
1116 ; GFX10GLISEL-NEXT: v_cmp_class_f16_e64 s4, v0, 3
1117 ; GFX10GLISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4
1118 ; GFX10GLISEL-NEXT: v_cmp_class_f16_sdwa s4, v0, v2 src0_sel:WORD_1 src1_sel:DWORD
1119 ; GFX10GLISEL-NEXT: v_mov_b32_e32 v0, v4
1120 ; GFX10GLISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
1121 ; GFX10GLISEL-NEXT: v_cmp_class_f16_e64 s4, v1, 3
1122 ; GFX10GLISEL-NEXT: v_mov_b32_e32 v1, v3
1123 ; GFX10GLISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
1124 ; GFX10GLISEL-NEXT: s_setpc_b64 s[30:31]
1125 ;
1126 ; GFX11SELDAG-LABEL: isnan_v3f16:
1127 ; GFX11SELDAG: ; %bb.0:
1128 ; GFX11SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1129 ; GFX11SELDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v0
1130 ; GFX11SELDAG-NEXT: v_cmp_u_f16_e32 vcc_lo, v0, v0
1131 ; GFX11SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
1132 ; GFX11SELDAG-NEXT: v_cmp_u_f16_e32 vcc_lo, v2, v2
1133 ; GFX11SELDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
1134 ; GFX11SELDAG-NEXT: v_cmp_u_f16_e32 vcc_lo, v1, v1
1135 ; GFX11SELDAG-NEXT: v_mov_b32_e32 v1, v3
1136 ; GFX11SELDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
1137 ; GFX11SELDAG-NEXT: s_setpc_b64 s[30:31]
1138 ;
1139 ; GFX11GLISEL-LABEL: isnan_v3f16:
1140 ; GFX11GLISEL: ; %bb.0:
1141 ; GFX11GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1142 ; GFX11GLISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
1143 ; GFX11GLISEL-NEXT: v_cmp_class_f16_e64 s0, v0, 3
1144 ; GFX11GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
1145 ; GFX11GLISEL-NEXT: v_cmp_class_f16_e64 s0, v2, 3
1146 ; GFX11GLISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
1147 ; GFX11GLISEL-NEXT: v_cmp_class_f16_e64 s0, v1, 3
1148 ; GFX11GLISEL-NEXT: v_mov_b32_e32 v1, v3
1149 ; GFX11GLISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
1150 ; GFX11GLISEL-NEXT: s_setpc_b64 s[30:31]
1151 %1 = call <3 x i1> @llvm.is.fpclass.v3f16(<3 x half> %x, i32 3) ; nan
1152 ret <3 x i1> %1
1153 }
1155 define <4 x i1> @isnan_v4f16(<4 x half> %x) nounwind {
1156 ; GFX7SELDAG-LABEL: isnan_v4f16:
1157 ; GFX7SELDAG: ; %bb.0:
1158 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1159 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
1160 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
1161 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v2, v2
1162 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v3, v3
1163 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
1164 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
1165 ; GFX7SELDAG-NEXT: v_and_b32_e32 v1, 0x7fff, v1
1166 ; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
1167 ; GFX7SELDAG-NEXT: v_and_b32_e32 v2, 0x7fff, v2
1168 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1169 ; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v1
1170 ; GFX7SELDAG-NEXT: v_and_b32_e32 v3, 0x7fff, v3
1171 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
1172 ; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v2
1173 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
1174 ; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v3
1175 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
1176 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
1177 ;
1178 ; GFX7GLISEL-LABEL: isnan_v4f16:
1179 ; GFX7GLISEL: ; %bb.0:
1180 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1181 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
1182 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
1183 ; GFX7GLISEL-NEXT: s_movk_i32 s4, 0x7c00
1184 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v1
1185 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
1186 ; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0x7fff, v2
1187 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s4, v0
1188 ; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
1189 ; GFX7GLISEL-NEXT: v_and_b32_e32 v3, 0x7fff, v3
1190 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1191 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s4, v1
1192 ; GFX7GLISEL-NEXT: v_and_b32_e32 v3, 0xffff, v3
1193 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
1194 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s4, v2
1195 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
1196 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s4, v3
1197 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
1198 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
1199 ;
1200 ; GFX8SELDAG-LABEL: isnan_v4f16:
1201 ; GFX8SELDAG: ; %bb.0:
1202 ; GFX8SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1203 ; GFX8SELDAG-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 3
1204 ; GFX8SELDAG-NEXT: v_lshrrev_b32_e32 v3, 16, v0
1205 ; GFX8SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
1206 ; GFX8SELDAG-NEXT: v_cmp_class_f16_e64 s[4:5], v1, 3
1207 ; GFX8SELDAG-NEXT: v_lshrrev_b32_e32 v4, 16, v1
1208 ; GFX8SELDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
1209 ; GFX8SELDAG-NEXT: v_cmp_class_f16_e64 s[4:5], v3, 3
1210 ; GFX8SELDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
1211 ; GFX8SELDAG-NEXT: v_cmp_class_f16_e64 s[4:5], v4, 3
1212 ; GFX8SELDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5]
1213 ; GFX8SELDAG-NEXT: s_setpc_b64 s[30:31]
1214 ;
1215 ; GFX8GLISEL-LABEL: isnan_v4f16:
1216 ; GFX8GLISEL: ; %bb.0:
1217 ; GFX8GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1218 ; GFX8GLISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
1219 ; GFX8GLISEL-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 3
1220 ; GFX8GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
1221 ; GFX8GLISEL-NEXT: v_cmp_class_f16_e64 s[4:5], v2, 3
1222 ; GFX8GLISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v1
1223 ; GFX8GLISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
1224 ; GFX8GLISEL-NEXT: v_cmp_class_f16_e64 s[4:5], v1, 3
1225 ; GFX8GLISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
1226 ; GFX8GLISEL-NEXT: v_cmp_class_f16_e64 s[4:5], v3, 3
1227 ; GFX8GLISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5]
1228 ; GFX8GLISEL-NEXT: v_mov_b32_e32 v1, v4
1229 ; GFX8GLISEL-NEXT: s_setpc_b64 s[30:31]
1230 ;
1231 ; GFX9SELDAG-LABEL: isnan_v4f16:
1232 ; GFX9SELDAG: ; %bb.0:
1233 ; GFX9SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1234 ; GFX9SELDAG-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 3
1235 ; GFX9SELDAG-NEXT: v_mov_b32_e32 v3, 3
1236 ; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[4:5]
1237 ; GFX9SELDAG-NEXT: v_cmp_class_f16_e64 s[4:5], v1, 3
1238 ; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
1239 ; GFX9SELDAG-NEXT: v_cmp_class_f16_sdwa s[4:5], v0, v3 src0_sel:WORD_1 src1_sel:DWORD
1240 ; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
1241 ; GFX9SELDAG-NEXT: v_cmp_class_f16_sdwa s[4:5], v1, v3 src0_sel:WORD_1 src1_sel:DWORD
1242 ; GFX9SELDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5]
1243 ; GFX9SELDAG-NEXT: v_mov_b32_e32 v0, v5
1244 ; GFX9SELDAG-NEXT: v_mov_b32_e32 v1, v4
1245 ; GFX9SELDAG-NEXT: s_setpc_b64 s[30:31]
1246 ;
1247 ; GFX9GLISEL-LABEL: isnan_v4f16:
1248 ; GFX9GLISEL: ; %bb.0:
1249 ; GFX9GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1250 ; GFX9GLISEL-NEXT: v_mov_b32_e32 v3, 3
1251 ; GFX9GLISEL-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 3
1252 ; GFX9GLISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
1253 ; GFX9GLISEL-NEXT: v_cmp_class_f16_sdwa s[4:5], v0, v3 src0_sel:WORD_1 src1_sel:DWORD
1254 ; GFX9GLISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[4:5]
1255 ; GFX9GLISEL-NEXT: v_cmp_class_f16_e64 s[4:5], v1, 3
1256 ; GFX9GLISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
1257 ; GFX9GLISEL-NEXT: v_cmp_class_f16_sdwa s[4:5], v1, v3 src0_sel:WORD_1 src1_sel:DWORD
1258 ; GFX9GLISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5]
1259 ; GFX9GLISEL-NEXT: v_mov_b32_e32 v0, v4
1260 ; GFX9GLISEL-NEXT: v_mov_b32_e32 v1, v5
1261 ; GFX9GLISEL-NEXT: s_setpc_b64 s[30:31]
1262 ;
1263 ; GFX10SELDAG-LABEL: isnan_v4f16:
1264 ; GFX10SELDAG: ; %bb.0:
1265 ; GFX10SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1266 ; GFX10SELDAG-NEXT: v_mov_b32_e32 v2, 3
1267 ; GFX10SELDAG-NEXT: v_cmp_class_f16_e64 s5, v0, 3
1268 ; GFX10SELDAG-NEXT: v_cmp_class_f16_sdwa s4, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
1269 ; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, s5
1270 ; GFX10SELDAG-NEXT: v_cmp_class_f16_sdwa s5, v0, v2 src0_sel:WORD_1 src1_sel:DWORD
1271 ; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
1272 ; GFX10SELDAG-NEXT: v_mov_b32_e32 v0, v4
1273 ; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1, s5
1274 ; GFX10SELDAG-NEXT: v_cmp_class_f16_e64 s5, v1, 3
1275 ; GFX10SELDAG-NEXT: v_mov_b32_e32 v1, v5
1276 ; GFX10SELDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, s5
1277 ; GFX10SELDAG-NEXT: s_setpc_b64 s[30:31]
1278 ;
1279 ; GFX10GLISEL-LABEL: isnan_v4f16:
1280 ; GFX10GLISEL: ; %bb.0:
1281 ; GFX10GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1282 ; GFX10GLISEL-NEXT: v_mov_b32_e32 v3, 3
1283 ; GFX10GLISEL-NEXT: v_cmp_class_f16_e64 s4, v0, 3
1284 ; GFX10GLISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4
1285 ; GFX10GLISEL-NEXT: v_cmp_class_f16_sdwa s4, v0, v3 src0_sel:WORD_1 src1_sel:DWORD
1286 ; GFX10GLISEL-NEXT: v_mov_b32_e32 v0, v4
1287 ; GFX10GLISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, s4
1288 ; GFX10GLISEL-NEXT: v_cmp_class_f16_e64 s4, v1, 3
1289 ; GFX10GLISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
1290 ; GFX10GLISEL-NEXT: v_cmp_class_f16_sdwa s4, v1, v3 src0_sel:WORD_1 src1_sel:DWORD
1291 ; GFX10GLISEL-NEXT: v_mov_b32_e32 v1, v5
1292 ; GFX10GLISEL-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
1293 ; GFX10GLISEL-NEXT: s_setpc_b64 s[30:31]
1294 ;
1295 ; GFX11CHECK-LABEL: isnan_v4f16:
1296 ; GFX11CHECK: ; %bb.0:
1297 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1298 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 3
1299 ; GFX11CHECK-NEXT: v_lshrrev_b32_e32 v3, 16, v0
1300 ; GFX11CHECK-NEXT: v_lshrrev_b32_e32 v4, 16, v1
1301 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
1302 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v1, 3
1303 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
1304 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v3, 3
1305 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
1306 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v4, 3
1307 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, s0
1308 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
1309 %1 = call <4 x i1> @llvm.is.fpclass.v4f16(<4 x half> %x, i32 3) ; nan
1310 ret <4 x i1> %1
1311 }
1313 define i1 @isnan_f16_strictfp(half %x) strictfp nounwind {
1314 ; GFX7SELDAG-LABEL: isnan_f16_strictfp:
1315 ; GFX7SELDAG: ; %bb.0:
1316 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1317 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
1318 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
1319 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
1320 ; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
1321 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1322 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
1323 ;
1324 ; GFX7GLISEL-LABEL: isnan_f16_strictfp:
1325 ; GFX7GLISEL: ; %bb.0:
1326 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1327 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
1328 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
1329 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
1330 ; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v0, v1
1331 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1332 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
1333 ;
1334 ; GFX8CHECK-LABEL: isnan_f16_strictfp:
1335 ; GFX8CHECK: ; %bb.0:
1336 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1337 ; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 3
1338 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
1339 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
1340 ;
1341 ; GFX9CHECK-LABEL: isnan_f16_strictfp:
1342 ; GFX9CHECK: ; %bb.0:
1343 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1344 ; GFX9CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 3
1345 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
1346 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
1347 ;
1348 ; GFX10CHECK-LABEL: isnan_f16_strictfp:
1349 ; GFX10CHECK: ; %bb.0:
1350 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1351 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 3
1352 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
1353 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
1354 ;
1355 ; GFX11CHECK-LABEL: isnan_f16_strictfp:
1356 ; GFX11CHECK: ; %bb.0:
1357 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1358 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 3
1359 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
1360 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
1361 %1 = call i1 @llvm.is.fpclass.f16(half %x, i32 3) strictfp ; nan
1362 ret i1 %1
1363 }
1365 define i1 @isinf_f16(half %x) nounwind {
1366 ; GFX7SELDAG-LABEL: isinf_f16:
1367 ; GFX7SELDAG: ; %bb.0:
1368 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1369 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
1370 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
1371 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
1372 ; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, s4, v0
1373 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1374 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
1375 ;
1376 ; GFX7GLISEL-LABEL: isinf_f16:
1377 ; GFX7GLISEL: ; %bb.0:
1378 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1379 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
1380 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
1381 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
1382 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
1383 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1384 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
1385 ;
1386 ; GFX8CHECK-LABEL: isinf_f16:
1387 ; GFX8CHECK: ; %bb.0:
1388 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1389 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x204
1390 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
1391 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1392 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
1393 ;
1394 ; GFX9CHECK-LABEL: isinf_f16:
1395 ; GFX9CHECK: ; %bb.0:
1396 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1397 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x204
1398 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
1399 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1400 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
1401 ;
1402 ; GFX10CHECK-LABEL: isinf_f16:
1403 ; GFX10CHECK: ; %bb.0:
1404 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1405 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x204
1406 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
1407 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
1408 ;
1409 ; GFX11CHECK-LABEL: isinf_f16:
1410 ; GFX11CHECK: ; %bb.0:
1411 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1412 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x204
1413 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
1414 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
1415 %1 = call i1 @llvm.is.fpclass.f16(half %x, i32 516) ; 0x204 = "inf"
1416 ret i1 %1
1417 }
1419 define i1 @isfinite_f16(half %x) nounwind {
1420 ; GFX7SELDAG-LABEL: isfinite_f16:
1421 ; GFX7SELDAG: ; %bb.0:
1422 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1423 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
1424 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
1425 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
1426 ; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
1427 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1428 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
1429 ;
1430 ; GFX7GLISEL-LABEL: isfinite_f16:
1431 ; GFX7GLISEL: ; %bb.0:
1432 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1433 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
1434 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
1435 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
1436 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
1437 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1438 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
1439 ;
1440 ; GFX8CHECK-LABEL: isfinite_f16:
1441 ; GFX8CHECK: ; %bb.0:
1442 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1443 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x1f8
1444 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
1445 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1446 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
1447 ;
1448 ; GFX9CHECK-LABEL: isfinite_f16:
1449 ; GFX9CHECK: ; %bb.0:
1450 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1451 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x1f8
1452 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
1453 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1454 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
1455 ;
1456 ; GFX10CHECK-LABEL: isfinite_f16:
1457 ; GFX10CHECK: ; %bb.0:
1458 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1459 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x1f8
1460 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
1461 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
1462 ;
1463 ; GFX11CHECK-LABEL: isfinite_f16:
1464 ; GFX11CHECK: ; %bb.0:
1465 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1466 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x1f8
1467 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
1468 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
1469 %1 = call i1 @llvm.is.fpclass.f16(half %x, i32 504) ; 0x1f8 = "finite"
1470 ret i1 %1
1471 }
1473 define i1 @issubnormal_or_zero_f16(half %x) {
1474 ; GFX7SELDAG-LABEL: issubnormal_or_zero_f16:
1475 ; GFX7SELDAG: ; %bb.0: ; %entry
1476 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1477 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
1478 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7c00, v0
1479 ; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
1480 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1481 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
1482 ;
1483 ; GFX7GLISEL-LABEL: issubnormal_or_zero_f16:
1484 ; GFX7GLISEL: ; %bb.0: ; %entry
1485 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1486 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7c00, v0
1487 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
1488 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
1489 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1490 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
1491 ;
1492 ; GFX8CHECK-LABEL: issubnormal_or_zero_f16:
1493 ; GFX8CHECK: ; %bb.0: ; %entry
1494 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1495 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0xf0
1496 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
1497 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1498 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
1499 ;
1500 ; GFX9CHECK-LABEL: issubnormal_or_zero_f16:
1501 ; GFX9CHECK: ; %bb.0: ; %entry
1502 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1503 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0xf0
1504 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
1505 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1506 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
1507 ;
1508 ; GFX10CHECK-LABEL: issubnormal_or_zero_f16:
1509 ; GFX10CHECK: ; %bb.0: ; %entry
1510 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1511 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0xf0
1512 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
1513 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
1514 ;
1515 ; GFX11CHECK-LABEL: issubnormal_or_zero_f16:
1516 ; GFX11CHECK: ; %bb.0: ; %entry
1517 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1518 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0xf0
1519 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
1520 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
1521 entry:
1522 %class = tail call i1 @llvm.is.fpclass.f16(half %x, i32 240) ; 0xf0 = "subnormal|zero"
1523 ret i1 %class
1524 }
1526 define i1 @not_issubnormal_or_zero_f16(half %x) {
1527 ; GFX7SELDAG-LABEL: not_issubnormal_or_zero_f16:
1528 ; GFX7SELDAG: ; %bb.0: ; %entry
1529 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1530 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
1531 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7c00, v0
1532 ; GFX7SELDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
1533 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1534 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
1535 ;
1536 ; GFX7GLISEL-LABEL: not_issubnormal_or_zero_f16:
1537 ; GFX7GLISEL: ; %bb.0: ; %entry
1538 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1539 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
1540 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0
1541 ; GFX7GLISEL-NEXT: s_movk_i32 s4, 0x7c00
1542 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, s4, v1
1543 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], s4, v1
1544 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
1545 ; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0
1546 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
1547 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
1548 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
1549 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
1550 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
1551 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
1552 ;
1553 ; GFX8CHECK-LABEL: not_issubnormal_or_zero_f16:
1554 ; GFX8CHECK: ; %bb.0: ; %entry
1555 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1556 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x30f
1557 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
1558 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1559 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
1560 ;
1561 ; GFX9CHECK-LABEL: not_issubnormal_or_zero_f16:
1562 ; GFX9CHECK: ; %bb.0: ; %entry
1563 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1564 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x30f
1565 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
1566 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1567 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
1568 ;
1569 ; GFX10CHECK-LABEL: not_issubnormal_or_zero_f16:
1570 ; GFX10CHECK: ; %bb.0: ; %entry
1571 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1572 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x30f
1573 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
1574 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
1575 ;
1576 ; GFX11CHECK-LABEL: not_issubnormal_or_zero_f16:
1577 ; GFX11CHECK: ; %bb.0: ; %entry
1578 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1579 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x30f
1580 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
1581 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
1582 entry:
1583 %class = tail call i1 @llvm.is.fpclass.f16(half %x, i32 783) ; ~0xf0 = "~(subnormal|zero)"
1584 ret i1 %class
1585 }
1587 define i1 @isnormal_f16(half %x) {
1588 ; GFX7SELDAG-LABEL: isnormal_f16:
1589 ; GFX7SELDAG: ; %bb.0:
1590 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1591 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
1592 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7800
1593 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
1594 ; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
1595 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
1596 ; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
1597 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1598 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
1599 ;
1600 ; GFX7GLISEL-LABEL: isnormal_f16:
1601 ; GFX7GLISEL: ; %bb.0:
1602 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1603 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
1604 ; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0
1605 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
1606 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
1607 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
1608 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1609 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
1610 ;
1611 ; GFX8CHECK-LABEL: isnormal_f16:
1612 ; GFX8CHECK: ; %bb.0:
1613 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1614 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x108
1615 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
1616 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1617 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
1618 ;
1619 ; GFX9CHECK-LABEL: isnormal_f16:
1620 ; GFX9CHECK: ; %bb.0:
1621 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1622 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x108
1623 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
1624 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1625 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
1626 ;
1627 ; GFX10CHECK-LABEL: isnormal_f16:
1628 ; GFX10CHECK: ; %bb.0:
1629 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1630 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x108
1631 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
1632 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
1633 ;
1634 ; GFX11CHECK-LABEL: isnormal_f16:
1635 ; GFX11CHECK: ; %bb.0:
1636 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1637 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x108
1638 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
1639 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
1640 %class = tail call i1 @llvm.is.fpclass.f16(half %x, i32 264) ; 0x108 = "normal"
1641 ret i1 %class
1642 }
1644 define i1 @not_isnormal_f16(half %x) {
1645 ; GFX7SELDAG-LABEL: not_isnormal_f16:
1646 ; GFX7SELDAG: ; %bb.0:
1647 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1648 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
1649 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x77ff
1650 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
1651 ; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
1652 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
1653 ; GFX7SELDAG-NEXT: v_cmp_lt_u32_e32 vcc, s4, v0
1654 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1655 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
1656 ;
1657 ; GFX7GLISEL-LABEL: not_isnormal_f16:
1658 ; GFX7GLISEL: ; %bb.0:
1659 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1660 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
1661 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7c00, v0
1662 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
1663 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
1664 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v1
1665 ; GFX7GLISEL-NEXT: s_movk_i32 s6, 0x7c00
1666 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, v0
1667 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
1668 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s6, v0
1669 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
1670 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
1671 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
1672 ;
1673 ; GFX8CHECK-LABEL: not_isnormal_f16:
1674 ; GFX8CHECK: ; %bb.0:
1675 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1676 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x2f7
1677 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
1678 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1679 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
1680 ;
1681 ; GFX9CHECK-LABEL: not_isnormal_f16:
1682 ; GFX9CHECK: ; %bb.0:
1683 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1684 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x2f7
1685 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
1686 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1687 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
1688 ;
1689 ; GFX10CHECK-LABEL: not_isnormal_f16:
1690 ; GFX10CHECK: ; %bb.0:
1691 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1692 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x2f7
1693 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
1694 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
1695 ;
1696 ; GFX11CHECK-LABEL: not_isnormal_f16:
1697 ; GFX11CHECK: ; %bb.0:
1698 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1699 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x2f7
1700 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
1701 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
1702 %class = tail call i1 @llvm.is.fpclass.f16(half %x, i32 759) ; ~0x108 = "~normal"
1703 ret i1 %class
1704 }
1706 define i1 @not_is_plus_normal_f16(half %x) {
1707 ; GFX7SELDAG-LABEL: not_is_plus_normal_f16:
1708 ; GFX7SELDAG: ; %bb.0:
1709 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1710 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
1711 ; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x77ff
1712 ; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
1713 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
1714 ; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
1715 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
1716 ; GFX7SELDAG-NEXT: v_cmp_gt_i32_e64 s[4:5], 0, v1
1717 ; GFX7SELDAG-NEXT: v_cmp_lt_u32_e32 vcc, s6, v0
1718 ; GFX7SELDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
1719 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
1720 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
1721 ;
1722 ; GFX7GLISEL-LABEL: not_is_plus_normal_f16:
1723 ; GFX7GLISEL: ; %bb.0:
1724 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1725 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
1726 ; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0xffff, v0
1727 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7c00, v0
1728 ; GFX7GLISEL-NEXT: v_and_b32_e32 v3, 0xffff, v1
1729 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
1730 ; GFX7GLISEL-NEXT: s_movk_i32 s8, 0x7c00
1731 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
1732 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], s8, v3
1733 ; GFX7GLISEL-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
1734 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s8, v3
1735 ; GFX7GLISEL-NEXT: s_or_b64 s[6:7], s[6:7], vcc
1736 ; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v1
1737 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
1738 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
1739 ; GFX7GLISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], v2, v3
1740 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
1741 ; GFX7GLISEL-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
1742 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5]
1743 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
1744 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
1745 ;
1746 ; GFX8CHECK-LABEL: not_is_plus_normal_f16:
1747 ; GFX8CHECK: ; %bb.0:
1748 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1749 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x2ff
1750 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
1751 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1752 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
1753 ;
1754 ; GFX9CHECK-LABEL: not_is_plus_normal_f16:
1755 ; GFX9CHECK: ; %bb.0:
1756 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1757 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x2ff
1758 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
1759 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1760 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
1761 ;
1762 ; GFX10CHECK-LABEL: not_is_plus_normal_f16:
1763 ; GFX10CHECK: ; %bb.0:
1764 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1765 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x2ff
1766 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
1767 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
1768 ;
1769 ; GFX11CHECK-LABEL: not_is_plus_normal_f16:
1770 ; GFX11CHECK: ; %bb.0:
1771 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1772 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x2ff
1773 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
1774 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
1775 %class = tail call i1 @llvm.is.fpclass.f16(half %x, i32 767) ; ~0x100 = ~"+normal"
1776 ret i1 %class
1777 }
1779 define i1 @not_is_neg_normal_f16(half %x) {
1780 ; GFX7SELDAG-LABEL: not_is_neg_normal_f16:
1781 ; GFX7SELDAG: ; %bb.0:
1782 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1783 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
1784 ; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x77ff
1785 ; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
1786 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
1787 ; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
1788 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
1789 ; GFX7SELDAG-NEXT: v_cmp_lt_i32_e64 s[4:5], -1, v1
1790 ; GFX7SELDAG-NEXT: v_cmp_lt_u32_e32 vcc, s6, v0
1791 ; GFX7SELDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
1792 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
1793 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
1794 ;
1795 ; GFX7GLISEL-LABEL: not_is_neg_normal_f16:
1796 ; GFX7GLISEL: ; %bb.0:
1797 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1798 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
1799 ; GFX7GLISEL-NEXT: v_and_b32_e32 v2, 0xffff, v0
1800 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7c00, v0
1801 ; GFX7GLISEL-NEXT: v_and_b32_e32 v3, 0xffff, v1
1802 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
1803 ; GFX7GLISEL-NEXT: s_movk_i32 s8, 0x7c00
1804 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
1805 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], s8, v3
1806 ; GFX7GLISEL-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
1807 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s8, v3
1808 ; GFX7GLISEL-NEXT: s_or_b64 s[6:7], s[6:7], vcc
1809 ; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v1
1810 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
1811 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
1812 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v2, v3
1813 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
1814 ; GFX7GLISEL-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
1815 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5]
1816 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
1817 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
1818 ;
1819 ; GFX8CHECK-LABEL: not_is_neg_normal_f16:
1820 ; GFX8CHECK: ; %bb.0:
1821 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1822 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x3f7
1823 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
1824 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1825 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
1826 ;
1827 ; GFX9CHECK-LABEL: not_is_neg_normal_f16:
1828 ; GFX9CHECK: ; %bb.0:
1829 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1830 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x3f7
1831 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
1832 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1833 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
1834 ;
1835 ; GFX10CHECK-LABEL: not_is_neg_normal_f16:
1836 ; GFX10CHECK: ; %bb.0:
1837 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1838 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x3f7
1839 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
1840 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
1841 ;
1842 ; GFX11CHECK-LABEL: not_is_neg_normal_f16:
1843 ; GFX11CHECK: ; %bb.0:
1844 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1845 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x3f7
1846 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
1847 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
1848 %class = tail call i1 @llvm.is.fpclass.f16(half %x, i32 1015) ; ~0x008 = ~"-normal"
1849 ret i1 %class
1850 }
1852 define i1 @issubnormal_f16(half %x) {
1853 ; GFX7SELDAG-LABEL: issubnormal_f16:
1854 ; GFX7SELDAG: ; %bb.0:
1855 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1856 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
1857 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x3ff
1858 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
1859 ; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, -1, v0
1860 ; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
1861 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1862 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
1863 ;
1864 ; GFX7GLISEL-LABEL: issubnormal_f16:
1865 ; GFX7GLISEL: ; %bb.0:
1866 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1867 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
1868 ; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 1, v0
1869 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
1870 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x3ff
1871 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
1872 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1873 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
1874 ;
1875 ; GFX8CHECK-LABEL: issubnormal_f16:
1876 ; GFX8CHECK: ; %bb.0:
1877 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1878 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x90
1879 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
1880 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1881 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
1882 ;
1883 ; GFX9CHECK-LABEL: issubnormal_f16:
1884 ; GFX9CHECK: ; %bb.0:
1885 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1886 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x90
1887 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
1888 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1889 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
1890 ;
1891 ; GFX10CHECK-LABEL: issubnormal_f16:
1892 ; GFX10CHECK: ; %bb.0:
1893 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1894 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x90
1895 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
1896 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
1897 ;
1898 ; GFX11CHECK-LABEL: issubnormal_f16:
1899 ; GFX11CHECK: ; %bb.0:
1900 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1901 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x90
1902 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
1903 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
1904 %class = tail call i1 @llvm.is.fpclass.f16(half %x, i32 144) ; 0x90 = "subnormal"
1905 ret i1 %class
1906 }
1908 define i1 @not_issubnormal_f16(half %x) {
1909 ; GFX7SELDAG-LABEL: not_issubnormal_f16:
1910 ; GFX7SELDAG: ; %bb.0:
1911 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1912 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
1913 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x3fe
1914 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
1915 ; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, -1, v0
1916 ; GFX7SELDAG-NEXT: v_cmp_lt_u32_e32 vcc, s4, v0
1917 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1918 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
1919 ;
1920 ; GFX7GLISEL-LABEL: not_issubnormal_f16:
1921 ; GFX7GLISEL: ; %bb.0:
1922 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1923 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
1924 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0
1925 ; GFX7GLISEL-NEXT: s_movk_i32 s6, 0x7c00
1926 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
1927 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, v1
1928 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
1929 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s6, v1
1930 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
1931 ; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0
1932 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
1933 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
1934 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
1935 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
1936 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
1937 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
1938 ;
1939 ; GFX8CHECK-LABEL: not_issubnormal_f16:
1940 ; GFX8CHECK: ; %bb.0:
1941 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1942 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x36f
1943 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
1944 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1945 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
1946 ;
1947 ; GFX9CHECK-LABEL: not_issubnormal_f16:
1948 ; GFX9CHECK: ; %bb.0:
1949 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1950 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x36f
1951 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
1952 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1953 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
1954 ;
1955 ; GFX10CHECK-LABEL: not_issubnormal_f16:
1956 ; GFX10CHECK: ; %bb.0:
1957 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1958 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x36f
1959 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
1960 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
1961 ;
1962 ; GFX11CHECK-LABEL: not_issubnormal_f16:
1963 ; GFX11CHECK: ; %bb.0:
1964 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1965 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x36f
1966 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
1967 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
1968 %class = tail call i1 @llvm.is.fpclass.f16(half %x, i32 879) ; ~0x90 = ~"subnormal"
1969 ret i1 %class
1970 }
1972 define i1 @iszero_f16(half %x) {
1973 ; GFX7SELDAG-LABEL: iszero_f16:
1974 ; GFX7SELDAG: ; %bb.0:
1975 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1976 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
1977 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
1978 ; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
1979 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1980 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
1981 ;
1982 ; GFX7GLISEL-LABEL: iszero_f16:
1983 ; GFX7GLISEL: ; %bb.0:
1984 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1985 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
1986 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
1987 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
1988 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1989 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
1990 ;
1991 ; GFX8CHECK-LABEL: iszero_f16:
1992 ; GFX8CHECK: ; %bb.0:
1993 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1994 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x60
1995 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
1996 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
1997 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
1998 ;
1999 ; GFX9CHECK-LABEL: iszero_f16:
2000 ; GFX9CHECK: ; %bb.0:
2001 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2002 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x60
2003 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
2004 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2005 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
2006 ;
2007 ; GFX10CHECK-LABEL: iszero_f16:
2008 ; GFX10CHECK: ; %bb.0:
2009 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2010 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x60
2011 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
2012 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
2013 ;
2014 ; GFX11CHECK-LABEL: iszero_f16:
2015 ; GFX11CHECK: ; %bb.0:
2016 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2017 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x60
2018 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
2019 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
2020 %class = tail call i1 @llvm.is.fpclass.f16(half %x, i32 96) ; 0x60 = "zero"
2021 ret i1 %class
2022 }
2024 define i1 @not_iszero_f16(half %x) {
2025 ; GFX7SELDAG-LABEL: not_iszero_f16:
2026 ; GFX7SELDAG: ; %bb.0:
2027 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2028 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2029 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
2030 ; GFX7SELDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
2031 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2032 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
2033 ;
2034 ; GFX7GLISEL-LABEL: not_iszero_f16:
2035 ; GFX7GLISEL: ; %bb.0:
2036 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2037 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
2038 ; GFX7GLISEL-NEXT: v_subrev_i32_e32 v1, vcc, 1, v0
2039 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
2040 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
2041 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2
2042 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0
2043 ; GFX7GLISEL-NEXT: s_movk_i32 s6, 0x7c00
2044 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, v1
2045 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
2046 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s6, v1
2047 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
2048 ; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0
2049 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
2050 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
2051 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
2052 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
2053 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2054 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
2055 ;
2056 ; GFX8CHECK-LABEL: not_iszero_f16:
2057 ; GFX8CHECK: ; %bb.0:
2058 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2059 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x39f
2060 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
2061 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2062 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
2063 ;
2064 ; GFX9CHECK-LABEL: not_iszero_f16:
2065 ; GFX9CHECK: ; %bb.0:
2066 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2067 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x39f
2068 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
2069 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2070 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
2071 ;
2072 ; GFX10CHECK-LABEL: not_iszero_f16:
2073 ; GFX10CHECK: ; %bb.0:
2074 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2075 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x39f
2076 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
2077 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
2078 ;
2079 ; GFX11CHECK-LABEL: not_iszero_f16:
2080 ; GFX11CHECK: ; %bb.0:
2081 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2082 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x39f
2083 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
2084 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
2085 %class = tail call i1 @llvm.is.fpclass.f16(half %x, i32 927) ; ~0x60 = ~"zero"
2086 ret i1 %class
2087 }
2089 define i1 @ispositive_f16(half %x) {
2090 ; GFX7SELDAG-LABEL: ispositive_f16:
2091 ; GFX7SELDAG: ; %bb.0:
2092 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2093 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2094 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c01
2095 ; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
2096 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2097 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
2098 ;
2099 ; GFX7GLISEL-LABEL: ispositive_f16:
2100 ; GFX7GLISEL: ; %bb.0:
2101 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2102 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
2103 ; GFX7GLISEL-NEXT: s_movk_i32 s4, 0x7c00
2104 ; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
2105 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s4, v0
2106 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
2107 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2108 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
2109 ;
2110 ; GFX8CHECK-LABEL: ispositive_f16:
2111 ; GFX8CHECK: ; %bb.0:
2112 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2113 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x3c0
2114 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
2115 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2116 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
2117 ;
2118 ; GFX9CHECK-LABEL: ispositive_f16:
2119 ; GFX9CHECK: ; %bb.0:
2120 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2121 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x3c0
2122 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
2123 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2124 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
2125 ;
2126 ; GFX10CHECK-LABEL: ispositive_f16:
2127 ; GFX10CHECK: ; %bb.0:
2128 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2129 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x3c0
2130 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
2131 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
2132 ;
2133 ; GFX11CHECK-LABEL: ispositive_f16:
2134 ; GFX11CHECK: ; %bb.0:
2135 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2136 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x3c0
2137 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
2138 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
2139 %class = tail call i1 @llvm.is.fpclass.f16(half %x, i32 960) ; fcPositive
2140 ret i1 %class
2141 }
2143 define i1 @not_ispositive_f16(half %x) {
2144 ; GFX7SELDAG-LABEL: not_ispositive_f16:
2145 ; GFX7SELDAG: ; %bb.0:
2146 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2147 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2148 ; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x7c00
2149 ; GFX7SELDAG-NEXT: s_mov_b32 s7, 0xfc00
2150 ; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
2151 ; GFX7SELDAG-NEXT: v_and_b32_e32 v2, 0x7fff, v0
2152 ; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1
2153 ; GFX7SELDAG-NEXT: v_cmp_gt_i32_e64 s[4:5], s6, v2
2154 ; GFX7SELDAG-NEXT: s_and_b64 s[4:5], s[4:5], vcc
2155 ; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, s7, v0
2156 ; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
2157 ; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s6, v2
2158 ; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
2159 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2160 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
2161 ;
2162 ; GFX7GLISEL-LABEL: not_ispositive_f16:
2163 ; GFX7GLISEL: ; %bb.0:
2164 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2165 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
2166 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
2167 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
2168 ; GFX7GLISEL-NEXT: s_movk_i32 s6, 0x7c00
2169 ; GFX7GLISEL-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
2170 ; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], s6, v1
2171 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0xfc00
2172 ; GFX7GLISEL-NEXT: s_and_b64 s[4:5], s[4:5], vcc
2173 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v2
2174 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
2175 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s6, v1
2176 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
2177 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2178 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
2179 ;
2180 ; GFX8CHECK-LABEL: not_ispositive_f16:
2181 ; GFX8CHECK: ; %bb.0:
2182 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2183 ; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 63
2184 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2185 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
2186 ;
2187 ; GFX9CHECK-LABEL: not_ispositive_f16:
2188 ; GFX9CHECK: ; %bb.0:
2189 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2190 ; GFX9CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 63
2191 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2192 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
2193 ;
2194 ; GFX10CHECK-LABEL: not_ispositive_f16:
2195 ; GFX10CHECK: ; %bb.0:
2196 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2197 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 63
2198 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
2199 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
2200 ;
2201 ; GFX11CHECK-LABEL: not_ispositive_f16:
2202 ; GFX11CHECK: ; %bb.0:
2203 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2204 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 63
2205 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
2206 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
2207 %class = tail call i1 @llvm.is.fpclass.f16(half %x, i32 63) ; ~fcPositive
2208 ret i1 %class
2209 }
2211 define i1 @isnegative_f16(half %x) {
2212 ; GFX7SELDAG-LABEL: isnegative_f16:
2213 ; GFX7SELDAG: ; %bb.0:
2214 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2215 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2216 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
2217 ; GFX7SELDAG-NEXT: s_mov_b32 s6, 0xfc00
2218 ; GFX7SELDAG-NEXT: v_bfe_i32 v1, v0, 0, 16
2219 ; GFX7SELDAG-NEXT: v_and_b32_e32 v2, 0x7fff, v0
2220 ; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1
2221 ; GFX7SELDAG-NEXT: v_cmp_gt_i32_e64 s[4:5], s4, v2
2222 ; GFX7SELDAG-NEXT: s_and_b64 s[4:5], s[4:5], vcc
2223 ; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, s6, v0
2224 ; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
2225 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2226 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
2227 ;
2228 ; GFX7GLISEL-LABEL: isnegative_f16:
2229 ; GFX7GLISEL: ; %bb.0:
2230 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2231 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
2232 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
2233 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
2234 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
2235 ; GFX7GLISEL-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1
2236 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], v1, v2
2237 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0xfc00
2238 ; GFX7GLISEL-NEXT: s_and_b64 s[4:5], s[4:5], vcc
2239 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
2240 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
2241 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2242 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
2243 ;
2244 ; GFX8CHECK-LABEL: isnegative_f16:
2245 ; GFX8CHECK: ; %bb.0:
2246 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2247 ; GFX8CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 60
2248 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2249 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
2250 ;
2251 ; GFX9CHECK-LABEL: isnegative_f16:
2252 ; GFX9CHECK: ; %bb.0:
2253 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2254 ; GFX9CHECK-NEXT: v_cmp_class_f16_e64 s[4:5], v0, 60
2255 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2256 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
2257 ;
2258 ; GFX10CHECK-LABEL: isnegative_f16:
2259 ; GFX10CHECK: ; %bb.0:
2260 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2261 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 60
2262 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
2263 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
2264 ;
2265 ; GFX11CHECK-LABEL: isnegative_f16:
2266 ; GFX11CHECK: ; %bb.0:
2267 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2268 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 60
2269 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
2270 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
2271 %class = tail call i1 @llvm.is.fpclass.f16(half %x, i32 60) ; fcNegative
2272 ret i1 %class
2273 }
2275 define i1 @not_isnegative_f16(half %x) {
2276 ; GFX7SELDAG-LABEL: not_isnegative_f16:
2277 ; GFX7SELDAG: ; %bb.0:
2278 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2279 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2280 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c01
2281 ; GFX7SELDAG-NEXT: s_movk_i32 s5, 0x7c00
2282 ; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
2283 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
2284 ; GFX7SELDAG-NEXT: v_cmp_lt_i32_e64 s[4:5], s5, v0
2285 ; GFX7SELDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
2286 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2287 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
2288 ;
2289 ; GFX7GLISEL-LABEL: not_isnegative_f16:
2290 ; GFX7GLISEL: ; %bb.0:
2291 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2292 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0
2293 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
2294 ; GFX7GLISEL-NEXT: s_movk_i32 s6, 0x7c00
2295 ; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, s6, v0
2296 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, v0
2297 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v1
2298 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
2299 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s6, v0
2300 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
2301 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2302 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
2303 ;
2304 ; GFX8CHECK-LABEL: not_isnegative_f16:
2305 ; GFX8CHECK: ; %bb.0:
2306 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2307 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x3c3
2308 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
2309 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2310 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
2311 ;
2312 ; GFX9CHECK-LABEL: not_isnegative_f16:
2313 ; GFX9CHECK: ; %bb.0:
2314 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2315 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x3c3
2316 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
2317 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2318 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
2319 ;
2320 ; GFX10CHECK-LABEL: not_isnegative_f16:
2321 ; GFX10CHECK: ; %bb.0:
2322 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2323 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x3c3
2324 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
2325 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
2326 ;
2327 ; GFX11CHECK-LABEL: not_isnegative_f16:
2328 ; GFX11CHECK: ; %bb.0:
2329 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2330 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x3c3
2331 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
2332 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
2333 %class = tail call i1 @llvm.is.fpclass.f16(half %x, i32 963) ; ~fcNegative
2334 ret i1 %class
2335 }
2337 define i1 @iszero_or_nan_f16(half %x) {
2338 ; GFX7SELDAG-LABEL: iszero_or_nan_f16:
2339 ; GFX7SELDAG: ; %bb.0: ; %entry
2340 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2341 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2342 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
2343 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
2344 ; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
2345 ; GFX7SELDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0
2346 ; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
2347 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2348 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
2349 ;
2350 ; GFX7GLISEL-LABEL: iszero_or_nan_f16:
2351 ; GFX7GLISEL: ; %bb.0: ; %entry
2352 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2353 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
2354 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
2355 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
2356 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
2357 ; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v0, v1
2358 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
2359 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2360 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
2361 ;
2362 ; GFX8CHECK-LABEL: iszero_or_nan_f16:
2363 ; GFX8CHECK: ; %bb.0: ; %entry
2364 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2365 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x63
2366 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
2367 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2368 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
2369 ;
2370 ; GFX9CHECK-LABEL: iszero_or_nan_f16:
2371 ; GFX9CHECK: ; %bb.0: ; %entry
2372 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2373 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x63
2374 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
2375 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2376 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
2377 ;
2378 ; GFX10CHECK-LABEL: iszero_or_nan_f16:
2379 ; GFX10CHECK: ; %bb.0: ; %entry
2380 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2381 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x63
2382 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
2383 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
2384 ;
2385 ; GFX11CHECK-LABEL: iszero_or_nan_f16:
2386 ; GFX11CHECK: ; %bb.0: ; %entry
2387 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2388 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x63
2389 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
2390 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
2391 entry:
2392 %0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 99) ; 0x60|0x3 = "zero|nan"
2393 ret i1 %0
2394 }
2396 define i1 @iszero_or_nan_f_daz(half %x) #0 {
2397 ; GFX7SELDAG-LABEL: iszero_or_nan_f_daz:
2398 ; GFX7SELDAG: ; %bb.0: ; %entry
2399 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2400 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2401 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
2402 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
2403 ; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
2404 ; GFX7SELDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0
2405 ; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
2406 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2407 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
2408 ;
2409 ; GFX7GLISEL-LABEL: iszero_or_nan_f_daz:
2410 ; GFX7GLISEL: ; %bb.0: ; %entry
2411 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2412 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
2413 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
2414 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
2415 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
2416 ; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v0, v1
2417 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
2418 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2419 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
2420 ;
2421 ; GFX8CHECK-LABEL: iszero_or_nan_f_daz:
2422 ; GFX8CHECK: ; %bb.0: ; %entry
2423 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2424 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x63
2425 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
2426 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2427 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
2428 ;
2429 ; GFX9CHECK-LABEL: iszero_or_nan_f_daz:
2430 ; GFX9CHECK: ; %bb.0: ; %entry
2431 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2432 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x63
2433 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
2434 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2435 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
2436 ;
2437 ; GFX10CHECK-LABEL: iszero_or_nan_f_daz:
2438 ; GFX10CHECK: ; %bb.0: ; %entry
2439 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2440 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x63
2441 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
2442 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
2443 ;
2444 ; GFX11CHECK-LABEL: iszero_or_nan_f_daz:
2445 ; GFX11CHECK: ; %bb.0: ; %entry
2446 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2447 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x63
2448 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
2449 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
2450 entry:
2451 %0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 99) ; 0x60|0x3 = "zero|nan"
2452 ret i1 %0
2453 }
2455 define i1 @iszero_or_nan_f_maybe_daz(half %x) #1 {
2456 ; GFX7SELDAG-LABEL: iszero_or_nan_f_maybe_daz:
2457 ; GFX7SELDAG: ; %bb.0: ; %entry
2458 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2459 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2460 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
2461 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
2462 ; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
2463 ; GFX7SELDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0
2464 ; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
2465 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2466 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
2467 ;
2468 ; GFX7GLISEL-LABEL: iszero_or_nan_f_maybe_daz:
2469 ; GFX7GLISEL: ; %bb.0: ; %entry
2470 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2471 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
2472 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
2473 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
2474 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
2475 ; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v0, v1
2476 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
2477 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2478 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
2479 ;
2480 ; GFX8CHECK-LABEL: iszero_or_nan_f_maybe_daz:
2481 ; GFX8CHECK: ; %bb.0: ; %entry
2482 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2483 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x63
2484 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
2485 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2486 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
2487 ;
2488 ; GFX9CHECK-LABEL: iszero_or_nan_f_maybe_daz:
2489 ; GFX9CHECK: ; %bb.0: ; %entry
2490 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2491 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x63
2492 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
2493 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2494 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
2495 ;
2496 ; GFX10CHECK-LABEL: iszero_or_nan_f_maybe_daz:
2497 ; GFX10CHECK: ; %bb.0: ; %entry
2498 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2499 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x63
2500 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
2501 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
2502 ;
2503 ; GFX11CHECK-LABEL: iszero_or_nan_f_maybe_daz:
2504 ; GFX11CHECK: ; %bb.0: ; %entry
2505 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2506 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x63
2507 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
2508 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
2509 entry:
2510 %0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 99) ; 0x60|0x3 = "zero|nan"
2511 ret i1 %0
2512 }
2514 define i1 @not_iszero_or_nan_f16(half %x) {
2515 ; GFX7SELDAG-LABEL: not_iszero_or_nan_f16:
2516 ; GFX7SELDAG: ; %bb.0: ; %entry
2517 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2518 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2519 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c01
2520 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
2521 ; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
2522 ; GFX7SELDAG-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0
2523 ; GFX7SELDAG-NEXT: s_and_b64 s[4:5], s[4:5], vcc
2524 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2525 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
2526 ;
2527 ; GFX7GLISEL-LABEL: not_iszero_or_nan_f16:
2528 ; GFX7GLISEL: ; %bb.0: ; %entry
2529 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2530 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
2531 ; GFX7GLISEL-NEXT: v_subrev_i32_e32 v1, vcc, 1, v0
2532 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
2533 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
2534 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2
2535 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0
2536 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
2537 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v2
2538 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
2539 ; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0
2540 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
2541 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
2542 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
2543 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
2544 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2545 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
2546 ;
2547 ; GFX8CHECK-LABEL: not_iszero_or_nan_f16:
2548 ; GFX8CHECK: ; %bb.0: ; %entry
2549 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2550 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x39c
2551 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
2552 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2553 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
2554 ;
2555 ; GFX9CHECK-LABEL: not_iszero_or_nan_f16:
2556 ; GFX9CHECK: ; %bb.0: ; %entry
2557 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2558 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x39c
2559 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
2560 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2561 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
2562 ;
2563 ; GFX10CHECK-LABEL: not_iszero_or_nan_f16:
2564 ; GFX10CHECK: ; %bb.0: ; %entry
2565 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2566 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x39c
2567 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
2568 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
2569 ;
2570 ; GFX11CHECK-LABEL: not_iszero_or_nan_f16:
2571 ; GFX11CHECK: ; %bb.0: ; %entry
2572 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2573 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x39c
2574 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
2575 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
2576 entry:
2577 %0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 924) ; ~0x60 = "~(zero|nan)"
2578 ret i1 %0
2579 }
2581 define i1 @not_iszero_or_nan_f_daz(half %x) #0 {
2582 ; GFX7SELDAG-LABEL: not_iszero_or_nan_f_daz:
2583 ; GFX7SELDAG: ; %bb.0: ; %entry
2584 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2585 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2586 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c01
2587 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
2588 ; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
2589 ; GFX7SELDAG-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0
2590 ; GFX7SELDAG-NEXT: s_and_b64 s[4:5], s[4:5], vcc
2591 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2592 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
2593 ;
2594 ; GFX7GLISEL-LABEL: not_iszero_or_nan_f_daz:
2595 ; GFX7GLISEL: ; %bb.0: ; %entry
2596 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2597 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
2598 ; GFX7GLISEL-NEXT: v_subrev_i32_e32 v1, vcc, 1, v0
2599 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
2600 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
2601 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2
2602 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0
2603 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
2604 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v2
2605 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
2606 ; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0
2607 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
2608 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
2609 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
2610 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
2611 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2612 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
2613 ;
2614 ; GFX8CHECK-LABEL: not_iszero_or_nan_f_daz:
2615 ; GFX8CHECK: ; %bb.0: ; %entry
2616 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2617 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x39c
2618 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
2619 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2620 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
2621 ;
2622 ; GFX9CHECK-LABEL: not_iszero_or_nan_f_daz:
2623 ; GFX9CHECK: ; %bb.0: ; %entry
2624 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2625 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x39c
2626 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
2627 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2628 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
2629 ;
2630 ; GFX10CHECK-LABEL: not_iszero_or_nan_f_daz:
2631 ; GFX10CHECK: ; %bb.0: ; %entry
2632 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2633 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x39c
2634 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
2635 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
2636 ;
2637 ; GFX11CHECK-LABEL: not_iszero_or_nan_f_daz:
2638 ; GFX11CHECK: ; %bb.0: ; %entry
2639 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2640 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x39c
2641 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
2642 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
2643 entry:
2644 %0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 924) ; ~(0x60|0x3) = "~(zero|nan)"
2645 ret i1 %0
2646 }
2648 define i1 @not_iszero_or_nan_f_maybe_daz(half %x) #1 {
2649 ; GFX7SELDAG-LABEL: not_iszero_or_nan_f_maybe_daz:
2650 ; GFX7SELDAG: ; %bb.0: ; %entry
2651 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2652 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2653 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c01
2654 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
2655 ; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
2656 ; GFX7SELDAG-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0
2657 ; GFX7SELDAG-NEXT: s_and_b64 s[4:5], s[4:5], vcc
2658 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2659 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
2660 ;
2661 ; GFX7GLISEL-LABEL: not_iszero_or_nan_f_maybe_daz:
2662 ; GFX7GLISEL: ; %bb.0: ; %entry
2663 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2664 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
2665 ; GFX7GLISEL-NEXT: v_subrev_i32_e32 v1, vcc, 1, v0
2666 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
2667 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
2668 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2
2669 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0
2670 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
2671 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v2
2672 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
2673 ; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0
2674 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
2675 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
2676 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
2677 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
2678 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2679 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
2680 ;
2681 ; GFX8CHECK-LABEL: not_iszero_or_nan_f_maybe_daz:
2682 ; GFX8CHECK: ; %bb.0: ; %entry
2683 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2684 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x39c
2685 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
2686 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2687 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
2688 ;
2689 ; GFX9CHECK-LABEL: not_iszero_or_nan_f_maybe_daz:
2690 ; GFX9CHECK: ; %bb.0: ; %entry
2691 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2692 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x39c
2693 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
2694 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2695 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
2696 ;
2697 ; GFX10CHECK-LABEL: not_iszero_or_nan_f_maybe_daz:
2698 ; GFX10CHECK: ; %bb.0: ; %entry
2699 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2700 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x39c
2701 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
2702 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
2703 ;
2704 ; GFX11CHECK-LABEL: not_iszero_or_nan_f_maybe_daz:
2705 ; GFX11CHECK: ; %bb.0: ; %entry
2706 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2707 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x39c
2708 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
2709 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
2710 entry:
2711 %0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 924) ; ~(0x60|0x3) = "~(zero|nan)"
2712 ret i1 %0
2713 }
2715 define i1 @iszero_or_qnan_f16(half %x) {
2716 ; GFX7SELDAG-LABEL: iszero_or_qnan_f16:
2717 ; GFX7SELDAG: ; %bb.0: ; %entry
2718 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2719 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2720 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7dff
2721 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
2722 ; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
2723 ; GFX7SELDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0
2724 ; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
2725 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2726 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
2727 ;
2728 ; GFX7GLISEL-LABEL: iszero_or_qnan_f16:
2729 ; GFX7GLISEL: ; %bb.0: ; %entry
2730 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2731 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
2732 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
2733 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7e00
2734 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
2735 ; GFX7GLISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v1
2736 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
2737 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2738 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
2739 ;
2740 ; GFX8CHECK-LABEL: iszero_or_qnan_f16:
2741 ; GFX8CHECK: ; %bb.0: ; %entry
2742 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2743 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x62
2744 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
2745 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2746 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
2747 ;
2748 ; GFX9CHECK-LABEL: iszero_or_qnan_f16:
2749 ; GFX9CHECK: ; %bb.0: ; %entry
2750 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2751 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x62
2752 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
2753 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2754 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
2755 ;
2756 ; GFX10CHECK-LABEL: iszero_or_qnan_f16:
2757 ; GFX10CHECK: ; %bb.0: ; %entry
2758 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2759 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x62
2760 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
2761 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
2762 ;
2763 ; GFX11CHECK-LABEL: iszero_or_qnan_f16:
2764 ; GFX11CHECK: ; %bb.0: ; %entry
2765 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2766 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x62
2767 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
2768 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
2769 entry:
2770 %0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 98) ; 0x60|0x2 = "zero|qnan"
2771 ret i1 %0
2772 }
2774 define i1 @iszero_or_snan_f16(half %x) {
2775 ; GFX7SELDAG-LABEL: iszero_or_snan_f16:
2776 ; GFX7SELDAG: ; %bb.0: ; %entry
2777 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2778 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2779 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7e00
2780 ; GFX7SELDAG-NEXT: s_movk_i32 s5, 0x7c00
2781 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
2782 ; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
2783 ; GFX7SELDAG-NEXT: v_cmp_lt_i32_e64 s[4:5], s5, v0
2784 ; GFX7SELDAG-NEXT: s_and_b64 s[4:5], s[4:5], vcc
2785 ; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
2786 ; GFX7SELDAG-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
2787 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2788 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
2789 ;
2790 ; GFX7GLISEL-LABEL: iszero_or_snan_f16:
2791 ; GFX7GLISEL: ; %bb.0: ; %entry
2792 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2793 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
2794 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
2795 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
2796 ; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v0, v1
2797 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7e00
2798 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[6:7], v0, v1
2799 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
2800 ; GFX7GLISEL-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7]
2801 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
2802 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2803 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
2804 ;
2805 ; GFX8CHECK-LABEL: iszero_or_snan_f16:
2806 ; GFX8CHECK: ; %bb.0: ; %entry
2807 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2808 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x61
2809 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
2810 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2811 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
2812 ;
2813 ; GFX9CHECK-LABEL: iszero_or_snan_f16:
2814 ; GFX9CHECK: ; %bb.0: ; %entry
2815 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2816 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x61
2817 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
2818 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2819 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
2820 ;
2821 ; GFX10CHECK-LABEL: iszero_or_snan_f16:
2822 ; GFX10CHECK: ; %bb.0: ; %entry
2823 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2824 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x61
2825 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
2826 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
2827 ;
2828 ; GFX11CHECK-LABEL: iszero_or_snan_f16:
2829 ; GFX11CHECK: ; %bb.0: ; %entry
2830 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2831 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x61
2832 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
2833 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
2834 entry:
2835 %0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 97) ; 0x60|0x1 = "zero|snan"
2836 ret i1 %0
2837 }
2839 define i1 @not_iszero_or_qnan_f16(half %x) {
2840 ; GFX7SELDAG-LABEL: not_iszero_or_qnan_f16:
2841 ; GFX7SELDAG: ; %bb.0: ; %entry
2842 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2843 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2844 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7e00
2845 ; GFX7SELDAG-NEXT: s_movk_i32 s8, 0x7c00
2846 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
2847 ; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
2848 ; GFX7SELDAG-NEXT: v_cmp_lt_i32_e64 s[4:5], s8, v0
2849 ; GFX7SELDAG-NEXT: s_and_b64 s[6:7], s[4:5], vcc
2850 ; GFX7SELDAG-NEXT: v_add_i32_e64 v1, s[4:5], -1, v0
2851 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x3ff
2852 ; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, s8, v0
2853 ; GFX7SELDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], s4, v1
2854 ; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
2855 ; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
2856 ; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
2857 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
2858 ; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x7800
2859 ; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s6, v0
2860 ; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
2861 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2862 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
2863 ;
2864 ; GFX7GLISEL-LABEL: not_iszero_or_qnan_f16:
2865 ; GFX7GLISEL: ; %bb.0: ; %entry
2866 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2867 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
2868 ; GFX7GLISEL-NEXT: v_subrev_i32_e32 v1, vcc, 1, v0
2869 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
2870 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
2871 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2
2872 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0
2873 ; GFX7GLISEL-NEXT: s_movk_i32 s8, 0x7c00
2874 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], s8, v1
2875 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7e00
2876 ; GFX7GLISEL-NEXT: s_or_b64 s[6:7], vcc, s[4:5]
2877 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, s8, v1
2878 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], v1, v2
2879 ; GFX7GLISEL-NEXT: s_and_b64 s[4:5], vcc, s[4:5]
2880 ; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0
2881 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
2882 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
2883 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5]
2884 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
2885 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
2886 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2887 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
2888 ;
2889 ; GFX8CHECK-LABEL: not_iszero_or_qnan_f16:
2890 ; GFX8CHECK: ; %bb.0: ; %entry
2891 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2892 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x39d
2893 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
2894 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2895 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
2896 ;
2897 ; GFX9CHECK-LABEL: not_iszero_or_qnan_f16:
2898 ; GFX9CHECK: ; %bb.0: ; %entry
2899 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2900 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x39d
2901 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
2902 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2903 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
2904 ;
2905 ; GFX10CHECK-LABEL: not_iszero_or_qnan_f16:
2906 ; GFX10CHECK: ; %bb.0: ; %entry
2907 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2908 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x39d
2909 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
2910 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
2911 ;
2912 ; GFX11CHECK-LABEL: not_iszero_or_qnan_f16:
2913 ; GFX11CHECK: ; %bb.0: ; %entry
2914 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2915 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x39d
2916 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
2917 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
2918 entry:
2919 %0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 925) ; ~(0x60|0x2) = "~(zero|qnan)"
2920 ret i1 %0
2921 }
2923 define i1 @not_iszero_or_snan_f16(half %x) {
2924 ; GFX7SELDAG-LABEL: not_iszero_or_snan_f16:
2925 ; GFX7SELDAG: ; %bb.0: ; %entry
2926 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2927 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2928 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
2929 ; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x7dff
2930 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
2931 ; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, s4, v0
2932 ; GFX7SELDAG-NEXT: v_add_i32_e64 v1, s[4:5], -1, v0
2933 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x3ff
2934 ; GFX7SELDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], s4, v1
2935 ; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
2936 ; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s6, v0
2937 ; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
2938 ; GFX7SELDAG-NEXT: v_add_i32_e32 v0, vcc, 0xfffffc00, v0
2939 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
2940 ; GFX7SELDAG-NEXT: s_movk_i32 s6, 0x7800
2941 ; GFX7SELDAG-NEXT: v_cmp_gt_u32_e32 vcc, s6, v0
2942 ; GFX7SELDAG-NEXT: s_or_b64 s[4:5], s[4:5], vcc
2943 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2944 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
2945 ;
2946 ; GFX7GLISEL-LABEL: not_iszero_or_snan_f16:
2947 ; GFX7GLISEL: ; %bb.0: ; %entry
2948 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2949 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
2950 ; GFX7GLISEL-NEXT: v_subrev_i32_e32 v1, vcc, 1, v0
2951 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
2952 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x3ff
2953 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2
2954 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0
2955 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00
2956 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v2
2957 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7e00
2958 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
2959 ; GFX7GLISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2
2960 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
2961 ; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0
2962 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
2963 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800
2964 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
2965 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc
2966 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
2967 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
2968 ;
2969 ; GFX8CHECK-LABEL: not_iszero_or_snan_f16:
2970 ; GFX8CHECK: ; %bb.0: ; %entry
2971 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2972 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x39e
2973 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
2974 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2975 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
2976 ;
2977 ; GFX9CHECK-LABEL: not_iszero_or_snan_f16:
2978 ; GFX9CHECK: ; %bb.0: ; %entry
2979 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2980 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x39e
2981 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
2982 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
2983 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
2984 ;
2985 ; GFX10CHECK-LABEL: not_iszero_or_snan_f16:
2986 ; GFX10CHECK: ; %bb.0: ; %entry
2987 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2988 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x39e
2989 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
2990 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
2991 ;
2992 ; GFX11CHECK-LABEL: not_iszero_or_snan_f16:
2993 ; GFX11CHECK: ; %bb.0: ; %entry
2994 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2995 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x39e
2996 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
2997 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
2998 entry:
2999 %0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 926) ; ~(0x60|0x1) = "~(zero|snan)"
3000 ret i1 %0
3001 }
3003 define i1 @isinf_or_nan_f16(half %x) {
3004 ; GFX7SELDAG-LABEL: isinf_or_nan_f16:
3005 ; GFX7SELDAG: ; %bb.0: ; %entry
3006 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3007 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
3008 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7bff
3009 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
3010 ; GFX7SELDAG-NEXT: v_cmp_lt_i32_e32 vcc, s4, v0
3011 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
3012 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
3013 ;
3014 ; GFX7GLISEL-LABEL: isinf_or_nan_f16:
3015 ; GFX7GLISEL: ; %bb.0: ; %entry
3016 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3017 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
3018 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
3019 ; GFX7GLISEL-NEXT: s_movk_i32 s4, 0x7c00
3020 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, s4, v0
3021 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], s4, v0
3022 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
3023 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
3024 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
3025 ;
3026 ; GFX8CHECK-LABEL: isinf_or_nan_f16:
3027 ; GFX8CHECK: ; %bb.0: ; %entry
3028 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3029 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x207
3030 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
3031 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
3032 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
3033 ;
3034 ; GFX9CHECK-LABEL: isinf_or_nan_f16:
3035 ; GFX9CHECK: ; %bb.0: ; %entry
3036 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3037 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x207
3038 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
3039 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
3040 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
3041 ;
3042 ; GFX10CHECK-LABEL: isinf_or_nan_f16:
3043 ; GFX10CHECK: ; %bb.0: ; %entry
3044 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3045 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x207
3046 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
3047 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
3048 ;
3049 ; GFX11CHECK-LABEL: isinf_or_nan_f16:
3050 ; GFX11CHECK: ; %bb.0: ; %entry
3051 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3052 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x207
3053 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
3054 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
3055 entry:
3056 %0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 519) ; 0x204|0x3 = "inf|nan"
3057 ret i1 %0
3058 }
3060 define i1 @not_isinf_or_nan_f16(half %x) {
3061 ; GFX7SELDAG-LABEL: not_isinf_or_nan_f16:
3062 ; GFX7SELDAG: ; %bb.0: ; %entry
3063 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3064 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
3065 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
3066 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
3067 ; GFX7SELDAG-NEXT: v_cmp_gt_i32_e32 vcc, s4, v0
3068 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
3069 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
3070 ;
3071 ; GFX7GLISEL-LABEL: not_isinf_or_nan_f16:
3072 ; GFX7GLISEL: ; %bb.0: ; %entry
3073 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3074 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
3075 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
3076 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
3077 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1
3078 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
3079 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
3080 ;
3081 ; GFX8CHECK-LABEL: not_isinf_or_nan_f16:
3082 ; GFX8CHECK: ; %bb.0: ; %entry
3083 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3084 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x1f8
3085 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
3086 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
3087 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
3088 ;
3089 ; GFX9CHECK-LABEL: not_isinf_or_nan_f16:
3090 ; GFX9CHECK: ; %bb.0: ; %entry
3091 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3092 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x1f8
3093 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
3094 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
3095 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
3096 ;
3097 ; GFX10CHECK-LABEL: not_isinf_or_nan_f16:
3098 ; GFX10CHECK: ; %bb.0: ; %entry
3099 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3100 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x1f8
3101 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
3102 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
3103 ;
3104 ; GFX11CHECK-LABEL: not_isinf_or_nan_f16:
3105 ; GFX11CHECK: ; %bb.0: ; %entry
3106 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3107 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x1f8
3108 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
3109 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
3110 entry:
3111 %0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 504) ; ~(0x204|0x3) = "~(inf|nan)"
3112 ret i1 %0
3113 }
3115 define i1 @isfinite_or_nan_f(half %x) {
3116 ; GFX7SELDAG-LABEL: isfinite_or_nan_f:
3117 ; GFX7SELDAG: ; %bb.0: ; %entry
3118 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3119 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
3120 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
3121 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
3122 ; GFX7SELDAG-NEXT: v_cmp_ne_u32_e32 vcc, s4, v0
3123 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
3124 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
3125 ;
3126 ; GFX7GLISEL-LABEL: isfinite_or_nan_f:
3127 ; GFX7GLISEL: ; %bb.0: ; %entry
3128 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3129 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
3130 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
3131 ; GFX7GLISEL-NEXT: s_movk_i32 s4, 0x7c00
3132 ; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, s4, v0
3133 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], s4, v0
3134 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
3135 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
3136 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
3137 ;
3138 ; GFX8CHECK-LABEL: isfinite_or_nan_f:
3139 ; GFX8CHECK: ; %bb.0: ; %entry
3140 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3141 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x1fb
3142 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
3143 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
3144 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
3145 ;
3146 ; GFX9CHECK-LABEL: isfinite_or_nan_f:
3147 ; GFX9CHECK: ; %bb.0: ; %entry
3148 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3149 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x1fb
3150 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
3151 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
3152 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
3153 ;
3154 ; GFX10CHECK-LABEL: isfinite_or_nan_f:
3155 ; GFX10CHECK: ; %bb.0: ; %entry
3156 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3157 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x1fb
3158 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
3159 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
3160 ;
3161 ; GFX11CHECK-LABEL: isfinite_or_nan_f:
3162 ; GFX11CHECK: ; %bb.0: ; %entry
3163 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3164 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x1fb
3165 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
3166 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
3167 entry:
3168 %0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 507) ; 0x1f8|0x3 = "finite|nan"
3169 ret i1 %0
3170 }
3172 define i1 @not_isfinite_or_nan_f(half %x) {
3173 ; GFX7SELDAG-LABEL: not_isfinite_or_nan_f:
3174 ; GFX7SELDAG: ; %bb.0: ; %entry
3175 ; GFX7SELDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3176 ; GFX7SELDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
3177 ; GFX7SELDAG-NEXT: s_movk_i32 s4, 0x7c00
3178 ; GFX7SELDAG-NEXT: v_and_b32_e32 v0, 0x7fff, v0
3179 ; GFX7SELDAG-NEXT: v_cmp_eq_u32_e32 vcc, s4, v0
3180 ; GFX7SELDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
3181 ; GFX7SELDAG-NEXT: s_setpc_b64 s[30:31]
3182 ;
3183 ; GFX7GLISEL-LABEL: not_isfinite_or_nan_f:
3184 ; GFX7GLISEL: ; %bb.0: ; %entry
3185 ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3186 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0
3187 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
3188 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00
3189 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1
3190 ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
3191 ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31]
3192 ;
3193 ; GFX8CHECK-LABEL: not_isfinite_or_nan_f:
3194 ; GFX8CHECK: ; %bb.0: ; %entry
3195 ; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3196 ; GFX8CHECK-NEXT: v_mov_b32_e32 v1, 0x204
3197 ; GFX8CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
3198 ; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
3199 ; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
3200 ;
3201 ; GFX9CHECK-LABEL: not_isfinite_or_nan_f:
3202 ; GFX9CHECK: ; %bb.0: ; %entry
3203 ; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3204 ; GFX9CHECK-NEXT: v_mov_b32_e32 v1, 0x204
3205 ; GFX9CHECK-NEXT: v_cmp_class_f16_e32 vcc, v0, v1
3206 ; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
3207 ; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
3208 ;
3209 ; GFX10CHECK-LABEL: not_isfinite_or_nan_f:
3210 ; GFX10CHECK: ; %bb.0: ; %entry
3211 ; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3212 ; GFX10CHECK-NEXT: v_cmp_class_f16_e64 s4, v0, 0x204
3213 ; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
3214 ; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
3215 ;
3216 ; GFX11CHECK-LABEL: not_isfinite_or_nan_f:
3217 ; GFX11CHECK: ; %bb.0: ; %entry
3218 ; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
3219 ; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 0x204
3220 ; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
3221 ; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
3222 entry:
3223 %0 = tail call i1 @llvm.is.fpclass.f16(half %x, i32 516) ; ~(0x1f8|0x3) = "~(finite|nan)"
3224 ret i1 %0
3225 }
3227 declare i1 @llvm.is.fpclass.f16(half, i32)
3228 declare <2 x i1> @llvm.is.fpclass.v2f16(<2 x half>, i32)
3229 declare <3 x i1> @llvm.is.fpclass.v3f16(<3 x half>, i32)
3230 declare <4 x i1> @llvm.is.fpclass.v4f16(<4 x half>, i32)
3232 ; Assume DAZ
3233 attributes #0 = { "denormal-fp-math"="ieee,preserve-sign" }
3235 ; Maybe daz
3236 attributes #1 = { "denormal-fp-math"="ieee,dynamic" }