| blob | 2e9197dfd3d9d8f6e5b29a0df648e4ab9bb184c8 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2 ; RUN: llc -march=amdgcn -mcpu=tahiti < %s | FileCheck --check-prefixes=GFX6 %s
3 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GFX89,GFX8 %s
4 ; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GFX89,GFX9 %s
5 ; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GFX11 %s
6 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefixes=R600 %s
8 define amdgpu_kernel void @round_f32(ptr addrspace(1) %out, float %x) #0 {
9 ; GFX6-LABEL: round_f32:
10 ; GFX6: ; %bb.0:
11 ; GFX6-NEXT: s_load_dword s6, s[0:1], 0xb
12 ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
13 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
14 ; GFX6-NEXT: s_mov_b32 s2, -1
15 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
16 ; GFX6-NEXT: v_trunc_f32_e32 v0, s6
17 ; GFX6-NEXT: v_sub_f32_e32 v1, s6, v0
18 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, 0.5
19 ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[4:5]
20 ; GFX6-NEXT: s_brev_b32 s4, -2
21 ; GFX6-NEXT: v_mov_b32_e32 v2, s6
22 ; GFX6-NEXT: v_bfi_b32 v1, s4, v1, v2
23 ; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
24 ; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
25 ; GFX6-NEXT: s_endpgm
26 ;
27 ; GFX8-LABEL: round_f32:
28 ; GFX8: ; %bb.0:
29 ; GFX8-NEXT: s_load_dword s6, s[0:1], 0x2c
30 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
31 ; GFX8-NEXT: s_mov_b32 s3, 0xf000
32 ; GFX8-NEXT: s_mov_b32 s2, -1
33 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
34 ; GFX8-NEXT: v_trunc_f32_e32 v0, s6
35 ; GFX8-NEXT: v_sub_f32_e32 v1, s6, v0
36 ; GFX8-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, 0.5
37 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[4:5]
38 ; GFX8-NEXT: s_brev_b32 s4, -2
39 ; GFX8-NEXT: v_mov_b32_e32 v2, s6
40 ; GFX8-NEXT: v_bfi_b32 v1, s4, v1, v2
41 ; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
42 ; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0
43 ; GFX8-NEXT: s_endpgm
44 ;
45 ; GFX9-LABEL: round_f32:
46 ; GFX9: ; %bb.0:
47 ; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c
48 ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
49 ; GFX9-NEXT: s_mov_b32 s7, 0xf000
50 ; GFX9-NEXT: s_mov_b32 s6, -1
51 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
52 ; GFX9-NEXT: v_trunc_f32_e32 v0, s2
53 ; GFX9-NEXT: v_sub_f32_e32 v1, s2, v0
54 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, 0.5
55 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[0:1]
56 ; GFX9-NEXT: s_brev_b32 s0, -2
57 ; GFX9-NEXT: v_mov_b32_e32 v2, s2
58 ; GFX9-NEXT: v_bfi_b32 v1, s0, v1, v2
59 ; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
60 ; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0
61 ; GFX9-NEXT: s_endpgm
62 ;
63 ; GFX11-LABEL: round_f32:
64 ; GFX11: ; %bb.0:
65 ; GFX11-NEXT: s_clause 0x1
66 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
67 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
68 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
69 ; GFX11-NEXT: v_trunc_f32_e32 v0, s2
70 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
71 ; GFX11-NEXT: v_sub_f32_e32 v1, s2, v0
72 ; GFX11-NEXT: v_cmp_ge_f32_e64 s3, |v1|, 0.5
73 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
74 ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s3
75 ; GFX11-NEXT: s_mov_b32 s3, 0x31016000
76 ; GFX11-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, s2
77 ; GFX11-NEXT: s_mov_b32 s2, -1
78 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
79 ; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
80 ; GFX11-NEXT: buffer_store_b32 v0, off, s[0:3], 0
81 ; GFX11-NEXT: s_nop 0
82 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
83 ; GFX11-NEXT: s_endpgm
84 ;
85 ; R600-LABEL: round_f32:
86 ; R600: ; %bb.0:
87 ; R600-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]
88 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
89 ; R600-NEXT: CF_END
90 ; R600-NEXT: PAD
91 ; R600-NEXT: ALU clause starting at 4:
92 ; R600-NEXT: TRUNC * T0.W, KC0[2].Z,
93 ; R600-NEXT: ADD * T1.W, KC0[2].Z, -PV.W,
94 ; R600-NEXT: SETGE * T1.W, |PV.W|, 0.5,
95 ; R600-NEXT: BFI_INT * T1.W, literal.x, PV.W, KC0[2].Z,
96 ; R600-NEXT: 2147483647(nan), 0(0.000000e+00)
97 ; R600-NEXT: ADD T0.X, T0.W, PV.W,
98 ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
99 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
100 %result = call float @llvm.round.f32(float %x) #1
101 store float %result, ptr addrspace(1) %out
102 ret void
103 }
105 ; The vector tests are really difficult to verify, since it can be hard to
106 ; predict how the scheduler will order the instructions. We already have
107 ; a test for the scalar case, so the vector tests just check that the
108 ; compiler doesn't crash.
109 define amdgpu_kernel void @round_v2f32(ptr addrspace(1) %out, <2 x float> %in) #0 {
110 ; GFX6-LABEL: round_v2f32:
111 ; GFX6: ; %bb.0:
112 ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
113 ; GFX6-NEXT: s_brev_b32 s8, -2
114 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
115 ; GFX6-NEXT: s_mov_b32 s6, -1
116 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
117 ; GFX6-NEXT: v_trunc_f32_e32 v0, s3
118 ; GFX6-NEXT: v_sub_f32_e32 v1, s3, v0
119 ; GFX6-NEXT: s_mov_b32 s4, s0
120 ; GFX6-NEXT: s_mov_b32 s5, s1
121 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, 0.5
122 ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[0:1]
123 ; GFX6-NEXT: v_mov_b32_e32 v2, s3
124 ; GFX6-NEXT: v_bfi_b32 v1, s8, v1, v2
125 ; GFX6-NEXT: v_add_f32_e32 v1, v0, v1
126 ; GFX6-NEXT: v_trunc_f32_e32 v0, s2
127 ; GFX6-NEXT: v_sub_f32_e32 v2, s2, v0
128 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[0:1], |v2|, 0.5
129 ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[0:1]
130 ; GFX6-NEXT: v_mov_b32_e32 v3, s2
131 ; GFX6-NEXT: v_bfi_b32 v2, s8, v2, v3
132 ; GFX6-NEXT: v_add_f32_e32 v0, v0, v2
133 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
134 ; GFX6-NEXT: s_endpgm
135 ;
136 ; GFX89-LABEL: round_v2f32:
137 ; GFX89: ; %bb.0:
138 ; GFX89-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
139 ; GFX89-NEXT: s_brev_b32 s8, -2
140 ; GFX89-NEXT: s_mov_b32 s7, 0xf000
141 ; GFX89-NEXT: s_mov_b32 s6, -1
142 ; GFX89-NEXT: s_waitcnt lgkmcnt(0)
143 ; GFX89-NEXT: v_trunc_f32_e32 v0, s3
144 ; GFX89-NEXT: v_sub_f32_e32 v1, s3, v0
145 ; GFX89-NEXT: s_mov_b32 s4, s0
146 ; GFX89-NEXT: s_mov_b32 s5, s1
147 ; GFX89-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, 0.5
148 ; GFX89-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[0:1]
149 ; GFX89-NEXT: v_mov_b32_e32 v2, s3
150 ; GFX89-NEXT: v_bfi_b32 v1, s8, v1, v2
151 ; GFX89-NEXT: v_add_f32_e32 v1, v0, v1
152 ; GFX89-NEXT: v_trunc_f32_e32 v0, s2
153 ; GFX89-NEXT: v_sub_f32_e32 v2, s2, v0
154 ; GFX89-NEXT: v_cmp_ge_f32_e64 s[0:1], |v2|, 0.5
155 ; GFX89-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[0:1]
156 ; GFX89-NEXT: v_mov_b32_e32 v3, s2
157 ; GFX89-NEXT: v_bfi_b32 v2, s8, v2, v3
158 ; GFX89-NEXT: v_add_f32_e32 v0, v0, v2
159 ; GFX89-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
160 ; GFX89-NEXT: s_endpgm
161 ;
162 ; GFX11-LABEL: round_v2f32:
163 ; GFX11: ; %bb.0:
164 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
165 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
166 ; GFX11-NEXT: v_trunc_f32_e32 v0, s3
167 ; GFX11-NEXT: v_trunc_f32_e32 v2, s2
168 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
169 ; GFX11-NEXT: v_sub_f32_e32 v1, s3, v0
170 ; GFX11-NEXT: v_sub_f32_e32 v3, s2, v2
171 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
172 ; GFX11-NEXT: v_cmp_ge_f32_e64 s4, |v1|, 0.5
173 ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s4
174 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
175 ; GFX11-NEXT: v_cmp_ge_f32_e64 s4, |v3|, 0.5
176 ; GFX11-NEXT: v_bfi_b32 v1, 0x7fffffff, v1, s3
177 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
178 ; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, s4
179 ; GFX11-NEXT: s_mov_b32 s3, 0x31016000
180 ; GFX11-NEXT: v_add_f32_e32 v1, v0, v1
181 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
182 ; GFX11-NEXT: v_bfi_b32 v3, 0x7fffffff, v3, s2
183 ; GFX11-NEXT: s_mov_b32 s2, -1
184 ; GFX11-NEXT: v_add_f32_e32 v0, v2, v3
185 ; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0
186 ; GFX11-NEXT: s_nop 0
187 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
188 ; GFX11-NEXT: s_endpgm
189 ;
190 ; R600-LABEL: round_v2f32:
191 ; R600: ; %bb.0:
192 ; R600-NEXT: ALU 13, @4, KC0[CB0:0-32], KC1[]
193 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
194 ; R600-NEXT: CF_END
195 ; R600-NEXT: PAD
196 ; R600-NEXT: ALU clause starting at 4:
197 ; R600-NEXT: TRUNC * T0.W, KC0[3].X,
198 ; R600-NEXT: ADD T1.W, KC0[3].X, -PV.W,
199 ; R600-NEXT: TRUNC * T2.W, KC0[2].W,
200 ; R600-NEXT: ADD T3.W, KC0[2].W, -PS,
201 ; R600-NEXT: SETGE * T1.W, |PV.W|, 0.5,
202 ; R600-NEXT: BFI_INT T1.W, literal.x, PS, KC0[3].X,
203 ; R600-NEXT: SETGE * T3.W, |PV.W|, 0.5,
204 ; R600-NEXT: 2147483647(nan), 0(0.000000e+00)
205 ; R600-NEXT: ADD T0.Y, T0.W, PV.W,
206 ; R600-NEXT: BFI_INT * T0.W, literal.x, PS, KC0[2].W,
207 ; R600-NEXT: 2147483647(nan), 0(0.000000e+00)
208 ; R600-NEXT: ADD T0.X, T2.W, PV.W,
209 ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
210 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
211 %result = call <2 x float> @llvm.round.v2f32(<2 x float> %in) #1
212 store <2 x float> %result, ptr addrspace(1) %out
213 ret void
214 }
216 define amdgpu_kernel void @round_v4f32(ptr addrspace(1) %out, <4 x float> %in) #0 {
217 ; GFX6-LABEL: round_v4f32:
218 ; GFX6: ; %bb.0:
219 ; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd
220 ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
221 ; GFX6-NEXT: s_brev_b32 s10, -2
222 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
223 ; GFX6-NEXT: s_mov_b32 s2, -1
224 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
225 ; GFX6-NEXT: v_trunc_f32_e32 v0, s7
226 ; GFX6-NEXT: v_sub_f32_e32 v1, s7, v0
227 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, 0.5
228 ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[8:9]
229 ; GFX6-NEXT: v_mov_b32_e32 v2, s7
230 ; GFX6-NEXT: v_bfi_b32 v1, s10, v1, v2
231 ; GFX6-NEXT: v_add_f32_e32 v3, v0, v1
232 ; GFX6-NEXT: v_trunc_f32_e32 v0, s6
233 ; GFX6-NEXT: v_sub_f32_e32 v1, s6, v0
234 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, 0.5
235 ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[8:9]
236 ; GFX6-NEXT: v_mov_b32_e32 v2, s6
237 ; GFX6-NEXT: v_bfi_b32 v1, s10, v1, v2
238 ; GFX6-NEXT: v_add_f32_e32 v2, v0, v1
239 ; GFX6-NEXT: v_trunc_f32_e32 v0, s5
240 ; GFX6-NEXT: v_sub_f32_e32 v1, s5, v0
241 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[6:7], |v1|, 0.5
242 ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[6:7]
243 ; GFX6-NEXT: v_mov_b32_e32 v4, s5
244 ; GFX6-NEXT: v_bfi_b32 v1, s10, v1, v4
245 ; GFX6-NEXT: v_add_f32_e32 v1, v0, v1
246 ; GFX6-NEXT: v_trunc_f32_e32 v0, s4
247 ; GFX6-NEXT: v_sub_f32_e32 v4, s4, v0
248 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[6:7], |v4|, 0.5
249 ; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s[6:7]
250 ; GFX6-NEXT: v_mov_b32_e32 v5, s4
251 ; GFX6-NEXT: v_bfi_b32 v4, s10, v4, v5
252 ; GFX6-NEXT: v_add_f32_e32 v0, v0, v4
253 ; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
254 ; GFX6-NEXT: s_endpgm
255 ;
256 ; GFX8-LABEL: round_v4f32:
257 ; GFX8: ; %bb.0:
258 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
259 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
260 ; GFX8-NEXT: s_brev_b32 s10, -2
261 ; GFX8-NEXT: s_mov_b32 s3, 0xf000
262 ; GFX8-NEXT: s_mov_b32 s2, -1
263 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
264 ; GFX8-NEXT: v_trunc_f32_e32 v0, s7
265 ; GFX8-NEXT: v_sub_f32_e32 v1, s7, v0
266 ; GFX8-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, 0.5
267 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[8:9]
268 ; GFX8-NEXT: v_mov_b32_e32 v2, s7
269 ; GFX8-NEXT: v_bfi_b32 v1, s10, v1, v2
270 ; GFX8-NEXT: v_add_f32_e32 v3, v0, v1
271 ; GFX8-NEXT: v_trunc_f32_e32 v0, s6
272 ; GFX8-NEXT: v_sub_f32_e32 v1, s6, v0
273 ; GFX8-NEXT: v_cmp_ge_f32_e64 s[8:9], |v1|, 0.5
274 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[8:9]
275 ; GFX8-NEXT: v_mov_b32_e32 v2, s6
276 ; GFX8-NEXT: v_bfi_b32 v1, s10, v1, v2
277 ; GFX8-NEXT: v_add_f32_e32 v2, v0, v1
278 ; GFX8-NEXT: v_trunc_f32_e32 v0, s5
279 ; GFX8-NEXT: v_sub_f32_e32 v1, s5, v0
280 ; GFX8-NEXT: v_cmp_ge_f32_e64 s[6:7], |v1|, 0.5
281 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[6:7]
282 ; GFX8-NEXT: v_mov_b32_e32 v4, s5
283 ; GFX8-NEXT: v_bfi_b32 v1, s10, v1, v4
284 ; GFX8-NEXT: v_add_f32_e32 v1, v0, v1
285 ; GFX8-NEXT: v_trunc_f32_e32 v0, s4
286 ; GFX8-NEXT: v_sub_f32_e32 v4, s4, v0
287 ; GFX8-NEXT: v_cmp_ge_f32_e64 s[6:7], |v4|, 0.5
288 ; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s[6:7]
289 ; GFX8-NEXT: v_mov_b32_e32 v5, s4
290 ; GFX8-NEXT: v_bfi_b32 v4, s10, v4, v5
291 ; GFX8-NEXT: v_add_f32_e32 v0, v0, v4
292 ; GFX8-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
293 ; GFX8-NEXT: s_endpgm
294 ;
295 ; GFX9-LABEL: round_v4f32:
296 ; GFX9: ; %bb.0:
297 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
298 ; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x24
299 ; GFX9-NEXT: s_brev_b32 s2, -2
300 ; GFX9-NEXT: s_mov_b32 s11, 0xf000
301 ; GFX9-NEXT: s_mov_b32 s10, -1
302 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
303 ; GFX9-NEXT: v_trunc_f32_e32 v0, s7
304 ; GFX9-NEXT: v_sub_f32_e32 v1, s7, v0
305 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, 0.5
306 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[0:1]
307 ; GFX9-NEXT: v_mov_b32_e32 v2, s7
308 ; GFX9-NEXT: v_bfi_b32 v1, s2, v1, v2
309 ; GFX9-NEXT: v_add_f32_e32 v3, v0, v1
310 ; GFX9-NEXT: v_trunc_f32_e32 v0, s6
311 ; GFX9-NEXT: v_sub_f32_e32 v1, s6, v0
312 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, 0.5
313 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[0:1]
314 ; GFX9-NEXT: v_mov_b32_e32 v2, s6
315 ; GFX9-NEXT: v_bfi_b32 v1, s2, v1, v2
316 ; GFX9-NEXT: v_add_f32_e32 v2, v0, v1
317 ; GFX9-NEXT: v_trunc_f32_e32 v0, s5
318 ; GFX9-NEXT: v_sub_f32_e32 v1, s5, v0
319 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, 0.5
320 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[0:1]
321 ; GFX9-NEXT: v_mov_b32_e32 v4, s5
322 ; GFX9-NEXT: v_bfi_b32 v1, s2, v1, v4
323 ; GFX9-NEXT: v_add_f32_e32 v1, v0, v1
324 ; GFX9-NEXT: v_trunc_f32_e32 v0, s4
325 ; GFX9-NEXT: v_sub_f32_e32 v4, s4, v0
326 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v4|, 0.5
327 ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s[0:1]
328 ; GFX9-NEXT: v_mov_b32_e32 v5, s4
329 ; GFX9-NEXT: v_bfi_b32 v4, s2, v4, v5
330 ; GFX9-NEXT: v_add_f32_e32 v0, v0, v4
331 ; GFX9-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
332 ; GFX9-NEXT: s_endpgm
333 ;
334 ; GFX11-LABEL: round_v4f32:
335 ; GFX11: ; %bb.0:
336 ; GFX11-NEXT: s_clause 0x1
337 ; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x34
338 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
339 ; GFX11-NEXT: s_mov_b32 s3, 0x31016000
340 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
341 ; GFX11-NEXT: v_trunc_f32_e32 v0, s7
342 ; GFX11-NEXT: v_trunc_f32_e32 v1, s6
343 ; GFX11-NEXT: v_trunc_f32_e32 v4, s5
344 ; GFX11-NEXT: v_trunc_f32_e32 v5, s4
345 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
346 ; GFX11-NEXT: v_dual_sub_f32 v2, s7, v0 :: v_dual_sub_f32 v3, s6, v1
347 ; GFX11-NEXT: v_dual_sub_f32 v6, s5, v4 :: v_dual_sub_f32 v7, s4, v5
348 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
349 ; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v2|, 0.5
350 ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s2
351 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
352 ; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v3|, 0.5
353 ; GFX11-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, s7
354 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
355 ; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, s2
356 ; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v6|, 0.5
357 ; GFX11-NEXT: v_bfi_b32 v8, 0x7fffffff, v3, s6
358 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
359 ; GFX11-NEXT: v_cndmask_b32_e64 v6, 0, 1.0, s2
360 ; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v7|, 0.5
361 ; GFX11-NEXT: v_dual_add_f32 v3, v0, v2 :: v_dual_add_f32 v2, v1, v8
362 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
363 ; GFX11-NEXT: v_bfi_b32 v6, 0x7fffffff, v6, s5
364 ; GFX11-NEXT: v_cndmask_b32_e64 v7, 0, 1.0, s2
365 ; GFX11-NEXT: s_mov_b32 s2, -1
366 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
367 ; GFX11-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, s4
368 ; GFX11-NEXT: v_dual_add_f32 v1, v4, v6 :: v_dual_add_f32 v0, v5, v7
369 ; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0
370 ; GFX11-NEXT: s_nop 0
371 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
372 ; GFX11-NEXT: s_endpgm
373 ;
374 ; R600-LABEL: round_v4f32:
375 ; R600: ; %bb.0:
376 ; R600-NEXT: ALU 25, @4, KC0[CB0:0-32], KC1[]
377 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T0.X, 1
378 ; R600-NEXT: CF_END
379 ; R600-NEXT: PAD
380 ; R600-NEXT: ALU clause starting at 4:
381 ; R600-NEXT: TRUNC * T0.W, KC0[4].X,
382 ; R600-NEXT: ADD T1.W, KC0[4].X, -PV.W,
383 ; R600-NEXT: TRUNC * T2.W, KC0[3].W,
384 ; R600-NEXT: TRUNC T0.Z, KC0[3].Z,
385 ; R600-NEXT: ADD T3.W, KC0[3].W, -PS,
386 ; R600-NEXT: SETGE * T1.W, |PV.W|, 0.5,
387 ; R600-NEXT: BFI_INT T0.Y, literal.x, PS, KC0[4].X,
388 ; R600-NEXT: SETGE T1.Z, |PV.W|, 0.5,
389 ; R600-NEXT: ADD * T1.W, KC0[3].Z, -PV.Z,
390 ; R600-NEXT: 2147483647(nan), 0(0.000000e+00)
391 ; R600-NEXT: TRUNC * T3.W, KC0[3].Y,
392 ; R600-NEXT: ADD T1.Y, KC0[3].Y, -PV.W,
393 ; R600-NEXT: SETGE T2.Z, |T1.W|, 0.5,
394 ; R600-NEXT: BFI_INT T1.W, literal.x, T1.Z, KC0[3].W,
395 ; R600-NEXT: ADD * T4.W, T0.W, T0.Y,
396 ; R600-NEXT: 2147483647(nan), 0(0.000000e+00)
397 ; R600-NEXT: ADD T4.Z, T2.W, PV.W,
398 ; R600-NEXT: BFI_INT T0.W, literal.x, PV.Z, KC0[3].Z,
399 ; R600-NEXT: SETGE * T1.W, |PV.Y|, 0.5,
400 ; R600-NEXT: 2147483647(nan), 0(0.000000e+00)
401 ; R600-NEXT: ADD T4.Y, T0.Z, PV.W,
402 ; R600-NEXT: BFI_INT * T0.W, literal.x, PS, KC0[3].Y,
403 ; R600-NEXT: 2147483647(nan), 0(0.000000e+00)
404 ; R600-NEXT: ADD T4.X, T3.W, PV.W,
405 ; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
406 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
407 %result = call <4 x float> @llvm.round.v4f32(<4 x float> %in) #1
408 store <4 x float> %result, ptr addrspace(1) %out
409 ret void
410 }
412 define amdgpu_kernel void @round_v8f32(ptr addrspace(1) %out, <8 x float> %in) #0 {
413 ; GFX6-LABEL: round_v8f32:
414 ; GFX6: ; %bb.0:
415 ; GFX6-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x11
416 ; GFX6-NEXT: s_brev_b32 s14, -2
417 ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
418 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
419 ; GFX6-NEXT: s_mov_b32 s2, -1
420 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
421 ; GFX6-NEXT: v_trunc_f32_e32 v0, s7
422 ; GFX6-NEXT: v_sub_f32_e32 v1, s7, v0
423 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[12:13], |v1|, 0.5
424 ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[12:13]
425 ; GFX6-NEXT: v_mov_b32_e32 v2, s7
426 ; GFX6-NEXT: v_bfi_b32 v1, s14, v1, v2
427 ; GFX6-NEXT: v_add_f32_e32 v3, v0, v1
428 ; GFX6-NEXT: v_trunc_f32_e32 v0, s6
429 ; GFX6-NEXT: v_sub_f32_e32 v1, s6, v0
430 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[12:13], |v1|, 0.5
431 ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[12:13]
432 ; GFX6-NEXT: v_mov_b32_e32 v2, s6
433 ; GFX6-NEXT: v_bfi_b32 v1, s14, v1, v2
434 ; GFX6-NEXT: v_add_f32_e32 v2, v0, v1
435 ; GFX6-NEXT: v_trunc_f32_e32 v0, s5
436 ; GFX6-NEXT: v_sub_f32_e32 v1, s5, v0
437 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[6:7], |v1|, 0.5
438 ; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[6:7]
439 ; GFX6-NEXT: v_mov_b32_e32 v4, s5
440 ; GFX6-NEXT: v_bfi_b32 v1, s14, v1, v4
441 ; GFX6-NEXT: v_add_f32_e32 v1, v0, v1
442 ; GFX6-NEXT: v_trunc_f32_e32 v0, s4
443 ; GFX6-NEXT: v_sub_f32_e32 v4, s4, v0
444 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[6:7], |v4|, 0.5
445 ; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s[6:7]
446 ; GFX6-NEXT: v_mov_b32_e32 v5, s4
447 ; GFX6-NEXT: v_bfi_b32 v4, s14, v4, v5
448 ; GFX6-NEXT: v_add_f32_e32 v0, v0, v4
449 ; GFX6-NEXT: v_trunc_f32_e32 v4, s11
450 ; GFX6-NEXT: v_sub_f32_e32 v5, s11, v4
451 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[4:5], |v5|, 0.5
452 ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s[4:5]
453 ; GFX6-NEXT: v_mov_b32_e32 v6, s11
454 ; GFX6-NEXT: v_bfi_b32 v5, s14, v5, v6
455 ; GFX6-NEXT: v_add_f32_e32 v7, v4, v5
456 ; GFX6-NEXT: v_trunc_f32_e32 v4, s10
457 ; GFX6-NEXT: v_sub_f32_e32 v5, s10, v4
458 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[4:5], |v5|, 0.5
459 ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s[4:5]
460 ; GFX6-NEXT: v_mov_b32_e32 v6, s10
461 ; GFX6-NEXT: v_bfi_b32 v5, s14, v5, v6
462 ; GFX6-NEXT: v_add_f32_e32 v6, v4, v5
463 ; GFX6-NEXT: v_trunc_f32_e32 v4, s9
464 ; GFX6-NEXT: v_sub_f32_e32 v5, s9, v4
465 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[4:5], |v5|, 0.5
466 ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s[4:5]
467 ; GFX6-NEXT: v_mov_b32_e32 v8, s9
468 ; GFX6-NEXT: v_bfi_b32 v5, s14, v5, v8
469 ; GFX6-NEXT: v_add_f32_e32 v5, v4, v5
470 ; GFX6-NEXT: v_trunc_f32_e32 v4, s8
471 ; GFX6-NEXT: v_sub_f32_e32 v8, s8, v4
472 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[4:5], |v8|, 0.5
473 ; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, 1.0, s[4:5]
474 ; GFX6-NEXT: v_mov_b32_e32 v9, s8
475 ; GFX6-NEXT: v_bfi_b32 v8, s14, v8, v9
476 ; GFX6-NEXT: v_add_f32_e32 v4, v4, v8
477 ; GFX6-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
478 ; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
479 ; GFX6-NEXT: s_endpgm
480 ;
481 ; GFX89-LABEL: round_v8f32:
482 ; GFX89: ; %bb.0:
483 ; GFX89-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x44
484 ; GFX89-NEXT: s_brev_b32 s14, -2
485 ; GFX89-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
486 ; GFX89-NEXT: s_mov_b32 s3, 0xf000
487 ; GFX89-NEXT: s_mov_b32 s2, -1
488 ; GFX89-NEXT: s_waitcnt lgkmcnt(0)
489 ; GFX89-NEXT: v_trunc_f32_e32 v0, s7
490 ; GFX89-NEXT: v_sub_f32_e32 v1, s7, v0
491 ; GFX89-NEXT: v_cmp_ge_f32_e64 s[12:13], |v1|, 0.5
492 ; GFX89-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[12:13]
493 ; GFX89-NEXT: v_mov_b32_e32 v2, s7
494 ; GFX89-NEXT: v_bfi_b32 v1, s14, v1, v2
495 ; GFX89-NEXT: v_add_f32_e32 v3, v0, v1
496 ; GFX89-NEXT: v_trunc_f32_e32 v0, s6
497 ; GFX89-NEXT: v_sub_f32_e32 v1, s6, v0
498 ; GFX89-NEXT: v_cmp_ge_f32_e64 s[12:13], |v1|, 0.5
499 ; GFX89-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[12:13]
500 ; GFX89-NEXT: v_mov_b32_e32 v2, s6
501 ; GFX89-NEXT: v_bfi_b32 v1, s14, v1, v2
502 ; GFX89-NEXT: v_add_f32_e32 v2, v0, v1
503 ; GFX89-NEXT: v_trunc_f32_e32 v0, s5
504 ; GFX89-NEXT: v_sub_f32_e32 v1, s5, v0
505 ; GFX89-NEXT: v_cmp_ge_f32_e64 s[6:7], |v1|, 0.5
506 ; GFX89-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[6:7]
507 ; GFX89-NEXT: v_mov_b32_e32 v4, s5
508 ; GFX89-NEXT: v_bfi_b32 v1, s14, v1, v4
509 ; GFX89-NEXT: v_add_f32_e32 v1, v0, v1
510 ; GFX89-NEXT: v_trunc_f32_e32 v0, s4
511 ; GFX89-NEXT: v_sub_f32_e32 v4, s4, v0
512 ; GFX89-NEXT: v_cmp_ge_f32_e64 s[6:7], |v4|, 0.5
513 ; GFX89-NEXT: v_cndmask_b32_e64 v4, 0, 1.0, s[6:7]
514 ; GFX89-NEXT: v_mov_b32_e32 v5, s4
515 ; GFX89-NEXT: v_bfi_b32 v4, s14, v4, v5
516 ; GFX89-NEXT: v_add_f32_e32 v0, v0, v4
517 ; GFX89-NEXT: v_trunc_f32_e32 v4, s11
518 ; GFX89-NEXT: v_sub_f32_e32 v5, s11, v4
519 ; GFX89-NEXT: v_cmp_ge_f32_e64 s[4:5], |v5|, 0.5
520 ; GFX89-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s[4:5]
521 ; GFX89-NEXT: v_mov_b32_e32 v6, s11
522 ; GFX89-NEXT: v_bfi_b32 v5, s14, v5, v6
523 ; GFX89-NEXT: v_add_f32_e32 v7, v4, v5
524 ; GFX89-NEXT: v_trunc_f32_e32 v4, s10
525 ; GFX89-NEXT: v_sub_f32_e32 v5, s10, v4
526 ; GFX89-NEXT: v_cmp_ge_f32_e64 s[4:5], |v5|, 0.5
527 ; GFX89-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s[4:5]
528 ; GFX89-NEXT: v_mov_b32_e32 v6, s10
529 ; GFX89-NEXT: v_bfi_b32 v5, s14, v5, v6
530 ; GFX89-NEXT: v_add_f32_e32 v6, v4, v5
531 ; GFX89-NEXT: v_trunc_f32_e32 v4, s9
532 ; GFX89-NEXT: v_sub_f32_e32 v5, s9, v4
533 ; GFX89-NEXT: v_cmp_ge_f32_e64 s[4:5], |v5|, 0.5
534 ; GFX89-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s[4:5]
535 ; GFX89-NEXT: v_mov_b32_e32 v8, s9
536 ; GFX89-NEXT: v_bfi_b32 v5, s14, v5, v8
537 ; GFX89-NEXT: v_add_f32_e32 v5, v4, v5
538 ; GFX89-NEXT: v_trunc_f32_e32 v4, s8
539 ; GFX89-NEXT: v_sub_f32_e32 v8, s8, v4
540 ; GFX89-NEXT: v_cmp_ge_f32_e64 s[4:5], |v8|, 0.5
541 ; GFX89-NEXT: v_cndmask_b32_e64 v8, 0, 1.0, s[4:5]
542 ; GFX89-NEXT: v_mov_b32_e32 v9, s8
543 ; GFX89-NEXT: v_bfi_b32 v8, s14, v8, v9
544 ; GFX89-NEXT: v_add_f32_e32 v4, v4, v8
545 ; GFX89-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
546 ; GFX89-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
547 ; GFX89-NEXT: s_endpgm
548 ;
549 ; GFX11-LABEL: round_v8f32:
550 ; GFX11: ; %bb.0:
551 ; GFX11-NEXT: s_clause 0x1
552 ; GFX11-NEXT: s_load_b256 s[4:11], s[0:1], 0x44
553 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
554 ; GFX11-NEXT: s_mov_b32 s3, 0x31016000
555 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
556 ; GFX11-NEXT: v_trunc_f32_e32 v0, s7
557 ; GFX11-NEXT: v_trunc_f32_e32 v1, s6
558 ; GFX11-NEXT: v_trunc_f32_e32 v4, s5
559 ; GFX11-NEXT: v_trunc_f32_e32 v8, s4
560 ; GFX11-NEXT: v_trunc_f32_e32 v5, s11
561 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
562 ; GFX11-NEXT: v_dual_sub_f32 v2, s7, v0 :: v_dual_sub_f32 v3, s6, v1
563 ; GFX11-NEXT: v_sub_f32_e32 v7, s5, v4
564 ; GFX11-NEXT: v_trunc_f32_e32 v9, s9
565 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
566 ; GFX11-NEXT: v_sub_f32_e32 v12, s11, v5
567 ; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v2|, 0.5
568 ; GFX11-NEXT: v_sub_f32_e32 v11, s4, v8
569 ; GFX11-NEXT: v_trunc_f32_e32 v6, s10
570 ; GFX11-NEXT: v_sub_f32_e32 v14, s9, v9
571 ; GFX11-NEXT: v_trunc_f32_e32 v10, s8
572 ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s2
573 ; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v3|, 0.5
574 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
575 ; GFX11-NEXT: v_bfi_b32 v2, 0x7fffffff, v2, s7
576 ; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, s2
577 ; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v7|, 0.5
578 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
579 ; GFX11-NEXT: v_bfi_b32 v16, 0x7fffffff, v3, s6
580 ; GFX11-NEXT: v_cndmask_b32_e64 v7, 0, 1.0, s2
581 ; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v11|, 0.5
582 ; GFX11-NEXT: v_sub_f32_e32 v13, s10, v6
583 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
584 ; GFX11-NEXT: v_dual_add_f32 v3, v0, v2 :: v_dual_add_f32 v2, v1, v16
585 ; GFX11-NEXT: v_bfi_b32 v7, 0x7fffffff, v7, s5
586 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
587 ; GFX11-NEXT: v_cndmask_b32_e64 v11, 0, 1.0, s2
588 ; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v12|, 0.5
589 ; GFX11-NEXT: v_add_f32_e32 v1, v4, v7
590 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
591 ; GFX11-NEXT: v_bfi_b32 v11, 0x7fffffff, v11, s4
592 ; GFX11-NEXT: v_cndmask_b32_e64 v12, 0, 1.0, s2
593 ; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v13|, 0.5
594 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
595 ; GFX11-NEXT: v_bfi_b32 v12, 0x7fffffff, v12, s11
596 ; GFX11-NEXT: v_cndmask_b32_e64 v13, 0, 1.0, s2
597 ; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v14|, 0.5
598 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
599 ; GFX11-NEXT: v_add_f32_e32 v7, v5, v12
600 ; GFX11-NEXT: v_bfi_b32 v13, 0x7fffffff, v13, s10
601 ; GFX11-NEXT: v_sub_f32_e32 v15, s8, v10
602 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
603 ; GFX11-NEXT: v_cndmask_b32_e64 v14, 0, 1.0, s2
604 ; GFX11-NEXT: v_add_f32_e32 v6, v6, v13
605 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
606 ; GFX11-NEXT: v_cmp_ge_f32_e64 s2, |v15|, 0.5
607 ; GFX11-NEXT: v_bfi_b32 v0, 0x7fffffff, v14, s9
608 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
609 ; GFX11-NEXT: v_cndmask_b32_e64 v15, 0, 1.0, s2
610 ; GFX11-NEXT: v_dual_add_f32 v5, v9, v0 :: v_dual_add_f32 v0, v8, v11
611 ; GFX11-NEXT: s_mov_b32 s2, -1
612 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
613 ; GFX11-NEXT: v_bfi_b32 v4, 0x7fffffff, v15, s8
614 ; GFX11-NEXT: v_add_f32_e32 v4, v10, v4
615 ; GFX11-NEXT: s_clause 0x1
616 ; GFX11-NEXT: buffer_store_b128 v[4:7], off, s[0:3], 0 offset:16
617 ; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0
618 ; GFX11-NEXT: s_nop 0
619 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
620 ; GFX11-NEXT: s_endpgm
621 ;
622 ; R600-LABEL: round_v8f32:
623 ; R600: ; %bb.0:
624 ; R600-NEXT: ALU 50, @4, KC0[CB0:0-32], KC1[]
625 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T2.X, 0
626 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XYZW, T1.X, 1
627 ; R600-NEXT: CF_END
628 ; R600-NEXT: ALU clause starting at 4:
629 ; R600-NEXT: TRUNC * T0.W, KC0[6].X,
630 ; R600-NEXT: ADD T0.Z, KC0[6].X, -PV.W,
631 ; R600-NEXT: TRUNC * T1.W, KC0[5].X,
632 ; R600-NEXT: TRUNC * T2.W, KC0[4].W,
633 ; R600-NEXT: ADD T1.Z, KC0[4].W, -PV.W,
634 ; R600-NEXT: ADD T3.W, KC0[5].X, -T1.W,
635 ; R600-NEXT: SETGE * T4.W, |T0.Z|, 0.5,
636 ; R600-NEXT: BFI_INT T0.Y, literal.x, PS, KC0[6].X,
637 ; R600-NEXT: SETGE T0.Z, |PV.W|, 0.5,
638 ; R600-NEXT: SETGE T3.W, |PV.Z|, 0.5,
639 ; R600-NEXT: TRUNC * T4.W, KC0[5].Y,
640 ; R600-NEXT: 2147483647(nan), 0(0.000000e+00)
641 ; R600-NEXT: ADD T1.Y, KC0[5].Y, -PS,
642 ; R600-NEXT: BFI_INT T1.Z, literal.x, PV.W, KC0[4].W,
643 ; R600-NEXT: BFI_INT T3.W, literal.x, PV.Z, KC0[5].X,
644 ; R600-NEXT: TRUNC * T5.W, KC0[4].Z,
645 ; R600-NEXT: 2147483647(nan), 0(0.000000e+00)
646 ; R600-NEXT: TRUNC T0.Z, KC0[4].Y,
647 ; R600-NEXT: TRUNC * T6.W, KC0[5].W,
648 ; R600-NEXT: ADD * T7.W, KC0[4].Z, -T5.W,
649 ; R600-NEXT: TRUNC T0.X, KC0[5].Z,
650 ; R600-NEXT: SETGE T2.Y, |PV.W|, 0.5,
651 ; R600-NEXT: ADD T2.Z, KC0[5].W, -T6.W, BS:VEC_102/SCL_221
652 ; R600-NEXT: ADD T7.W, KC0[4].Y, -T0.Z,
653 ; R600-NEXT: ADD * T3.W, T1.W, T3.W,
654 ; R600-NEXT: SETGE T1.X, |PV.W|, 0.5,
655 ; R600-NEXT: SETGE T4.Y, |PV.Z|, 0.5,
656 ; R600-NEXT: ADD T3.Z, T2.W, T1.Z,
657 ; R600-NEXT: BFI_INT T1.W, literal.x, PV.Y, KC0[4].Z,
658 ; R600-NEXT: ADD * T2.W, KC0[5].Z, -PV.X,
659 ; R600-NEXT: 2147483647(nan), 0(0.000000e+00)
660 ; R600-NEXT: SETGE T2.X, |PS|, 0.5,
661 ; R600-NEXT: ADD T3.Y, T5.W, PV.W,
662 ; R600-NEXT: BFI_INT T1.Z, literal.x, PV.Y, KC0[5].W,
663 ; R600-NEXT: BFI_INT T1.W, literal.x, PV.X, KC0[4].Y,
664 ; R600-NEXT: ADD * T0.W, T0.W, T0.Y,
665 ; R600-NEXT: 2147483647(nan), 0(0.000000e+00)
666 ; R600-NEXT: ADD T3.X, T0.Z, PV.W,
667 ; R600-NEXT: ADD T0.Z, T6.W, PV.Z,
668 ; R600-NEXT: BFI_INT T1.W, literal.x, PV.X, KC0[5].Z,
669 ; R600-NEXT: SETGE * T2.W, |T1.Y|, 0.5,
670 ; R600-NEXT: 2147483647(nan), 0(0.000000e+00)
671 ; R600-NEXT: LSHR T1.X, KC0[2].Y, literal.x,
672 ; R600-NEXT: ADD T0.Y, T0.X, PV.W,
673 ; R600-NEXT: BFI_INT * T1.W, literal.y, PS, KC0[5].Y,
674 ; R600-NEXT: 2(2.802597e-45), 2147483647(nan)
675 ; R600-NEXT: ADD T0.X, T4.W, PV.W,
676 ; R600-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.x,
677 ; R600-NEXT: 16(2.242078e-44), 0(0.000000e+00)
678 ; R600-NEXT: LSHR * T2.X, PV.W, literal.x,
679 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
680 %result = call <8 x float> @llvm.round.v8f32(<8 x float> %in) #1
681 store <8 x float> %result, ptr addrspace(1) %out
682 ret void
683 }
685 define amdgpu_kernel void @round_f16(ptr addrspace(1) %out, i32 %x.arg) #0 {
686 ; GFX6-LABEL: round_f16:
687 ; GFX6: ; %bb.0:
688 ; GFX6-NEXT: s_load_dword s2, s[0:1], 0xb
689 ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
690 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
691 ; GFX6-NEXT: v_cvt_f32_f16_e32 v0, s2
692 ; GFX6-NEXT: v_trunc_f32_e32 v1, v0
693 ; GFX6-NEXT: v_sub_f32_e32 v2, v0, v1
694 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[2:3], |v2|, 0.5
695 ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[2:3]
696 ; GFX6-NEXT: s_brev_b32 s2, -2
697 ; GFX6-NEXT: v_bfi_b32 v0, s2, v2, v0
698 ; GFX6-NEXT: v_add_f32_e32 v0, v1, v0
699 ; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
700 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
701 ; GFX6-NEXT: s_mov_b32 s2, -1
702 ; GFX6-NEXT: buffer_store_short v0, off, s[0:3], 0
703 ; GFX6-NEXT: s_endpgm
704 ;
705 ; GFX8-LABEL: round_f16:
706 ; GFX8: ; %bb.0:
707 ; GFX8-NEXT: s_load_dword s4, s[0:1], 0x2c
708 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
709 ; GFX8-NEXT: v_mov_b32_e32 v0, 0x3c00
710 ; GFX8-NEXT: s_movk_i32 s5, 0x7fff
711 ; GFX8-NEXT: s_mov_b32 s3, 0xf000
712 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
713 ; GFX8-NEXT: v_trunc_f16_e32 v1, s4
714 ; GFX8-NEXT: v_sub_f16_e32 v2, s4, v1
715 ; GFX8-NEXT: v_cmp_ge_f16_e64 vcc, |v2|, 0.5
716 ; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
717 ; GFX8-NEXT: v_mov_b32_e32 v2, s4
718 ; GFX8-NEXT: v_bfi_b32 v0, s5, v0, v2
719 ; GFX8-NEXT: s_mov_b32 s2, -1
720 ; GFX8-NEXT: v_add_f16_e32 v0, v1, v0
721 ; GFX8-NEXT: buffer_store_short v0, off, s[0:3], 0
722 ; GFX8-NEXT: s_endpgm
723 ;
724 ; GFX9-LABEL: round_f16:
725 ; GFX9: ; %bb.0:
726 ; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c
727 ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
728 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x3c00
729 ; GFX9-NEXT: s_movk_i32 s0, 0x7fff
730 ; GFX9-NEXT: s_mov_b32 s7, 0xf000
731 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
732 ; GFX9-NEXT: v_trunc_f16_e32 v1, s2
733 ; GFX9-NEXT: v_sub_f16_e32 v2, s2, v1
734 ; GFX9-NEXT: v_cmp_ge_f16_e64 vcc, |v2|, 0.5
735 ; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
736 ; GFX9-NEXT: v_mov_b32_e32 v2, s2
737 ; GFX9-NEXT: v_bfi_b32 v0, s0, v0, v2
738 ; GFX9-NEXT: s_mov_b32 s6, -1
739 ; GFX9-NEXT: v_add_f16_e32 v0, v1, v0
740 ; GFX9-NEXT: buffer_store_short v0, off, s[4:7], 0
741 ; GFX9-NEXT: s_endpgm
742 ;
743 ; GFX11-LABEL: round_f16:
744 ; GFX11: ; %bb.0:
745 ; GFX11-NEXT: s_clause 0x1
746 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
747 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
748 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
749 ; GFX11-NEXT: v_trunc_f16_e32 v0, s2
750 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
751 ; GFX11-NEXT: v_sub_f16_e32 v1, s2, v0
752 ; GFX11-NEXT: v_cmp_ge_f16_e64 s3, |v1|, 0.5
753 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
754 ; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x3c00, s3
755 ; GFX11-NEXT: s_mov_b32 s3, 0x31016000
756 ; GFX11-NEXT: v_bfi_b32 v1, 0x7fff, v1, s2
757 ; GFX11-NEXT: s_mov_b32 s2, -1
758 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
759 ; GFX11-NEXT: v_add_f16_e32 v0, v0, v1
760 ; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0
761 ; GFX11-NEXT: s_nop 0
762 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
763 ; GFX11-NEXT: s_endpgm
764 ;
765 ; R600-LABEL: round_f16:
766 ; R600: ; %bb.0:
767 ; R600-NEXT: ALU 17, @4, KC0[CB0:0-32], KC1[]
768 ; R600-NEXT: MEM_RAT MSKOR T0.XW, T1.X
769 ; R600-NEXT: CF_END
770 ; R600-NEXT: PAD
771 ; R600-NEXT: ALU clause starting at 4:
772 ; R600-NEXT: FLT16_TO_FLT32 * T0.W, KC0[2].Z,
773 ; R600-NEXT: TRUNC * T1.W, PV.W,
774 ; R600-NEXT: ADD * T2.W, T0.W, -PV.W,
775 ; R600-NEXT: SETGE * T2.W, |PV.W|, 0.5,
776 ; R600-NEXT: BFI_INT T0.W, literal.x, PV.W, T0.W,
777 ; R600-NEXT: AND_INT * T2.W, KC0[2].Y, literal.y,
778 ; R600-NEXT: 2147483647(nan), 3(4.203895e-45)
779 ; R600-NEXT: ADD * T0.W, T1.W, PV.W,
780 ; R600-NEXT: FLT32_TO_FLT16 T0.W, PV.W,
781 ; R600-NEXT: LSHL * T1.W, T2.W, literal.x,
782 ; R600-NEXT: 3(4.203895e-45), 0(0.000000e+00)
783 ; R600-NEXT: LSHL T0.X, PV.W, PS,
784 ; R600-NEXT: LSHL * T0.W, literal.x, PS,
785 ; R600-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
786 ; R600-NEXT: MOV T0.Y, 0.0,
787 ; R600-NEXT: MOV * T0.Z, 0.0,
788 ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
789 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
790 %x.arg.trunc = trunc i32 %x.arg to i16
791 %x = bitcast i16 %x.arg.trunc to half
792 %result = call half @llvm.round.f16(half %x) #1
793 store half %result, ptr addrspace(1) %out
794 ret void
795 }
797 ; Should be scalarized
798 define amdgpu_kernel void @round_v2f16(ptr addrspace(1) %out, i32 %in.arg) #0 {
799 ; GFX6-LABEL: round_v2f16:
800 ; GFX6: ; %bb.0:
801 ; GFX6-NEXT: s_load_dword s2, s[0:1], 0xb
802 ; GFX6-NEXT: s_brev_b32 s4, -2
803 ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
804 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
805 ; GFX6-NEXT: s_lshr_b32 s3, s2, 16
806 ; GFX6-NEXT: v_cvt_f32_f16_e32 v1, s3
807 ; GFX6-NEXT: v_cvt_f32_f16_e32 v0, s2
808 ; GFX6-NEXT: v_trunc_f32_e32 v3, v1
809 ; GFX6-NEXT: v_sub_f32_e32 v5, v1, v3
810 ; GFX6-NEXT: v_trunc_f32_e32 v2, v0
811 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[2:3], |v5|, 0.5
812 ; GFX6-NEXT: v_sub_f32_e32 v4, v0, v2
813 ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1.0, s[2:3]
814 ; GFX6-NEXT: v_bfi_b32 v1, s4, v5, v1
815 ; GFX6-NEXT: v_cmp_ge_f32_e64 s[2:3], |v4|, 0.5
816 ; GFX6-NEXT: v_add_f32_e32 v1, v3, v1
817 ; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, 1.0, s[2:3]
818 ; GFX6-NEXT: v_bfi_b32 v0, s4, v3, v0
819 ; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
820 ; GFX6-NEXT: v_add_f32_e32 v0, v2, v0
821 ; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
822 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
823 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
824 ; GFX6-NEXT: s_mov_b32 s2, -1
825 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
826 ; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
827 ; GFX6-NEXT: s_endpgm
828 ;
829 ; GFX8-LABEL: round_v2f16:
830 ; GFX8: ; %bb.0:
831 ; GFX8-NEXT: s_load_dword s4, s[0:1], 0x2c
832 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
833 ; GFX8-NEXT: v_mov_b32_e32 v0, 0x3c00
834 ; GFX8-NEXT: s_movk_i32 s6, 0x7fff
835 ; GFX8-NEXT: s_mov_b32 s3, 0xf000
836 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
837 ; GFX8-NEXT: s_lshr_b32 s5, s4, 16
838 ; GFX8-NEXT: v_trunc_f16_e32 v1, s5
839 ; GFX8-NEXT: v_sub_f16_e32 v2, s5, v1
840 ; GFX8-NEXT: v_cmp_ge_f16_e64 vcc, |v2|, 0.5
841 ; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v0, vcc
842 ; GFX8-NEXT: v_mov_b32_e32 v3, s5
843 ; GFX8-NEXT: v_bfi_b32 v2, s6, v2, v3
844 ; GFX8-NEXT: v_add_f16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
845 ; GFX8-NEXT: v_trunc_f16_e32 v2, s4
846 ; GFX8-NEXT: v_sub_f16_e32 v3, s4, v2
847 ; GFX8-NEXT: v_cmp_ge_f16_e64 vcc, |v3|, 0.5
848 ; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
849 ; GFX8-NEXT: v_mov_b32_e32 v3, s4
850 ; GFX8-NEXT: v_bfi_b32 v0, s6, v0, v3
851 ; GFX8-NEXT: v_add_f16_e32 v0, v2, v0
852 ; GFX8-NEXT: s_mov_b32 s2, -1
853 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
854 ; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0
855 ; GFX8-NEXT: s_endpgm
856 ;
857 ; GFX9-LABEL: round_v2f16:
858 ; GFX9: ; %bb.0:
859 ; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c
860 ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
861 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x3c00
862 ; GFX9-NEXT: s_movk_i32 s1, 0x7fff
863 ; GFX9-NEXT: s_mov_b32 s7, 0xf000
864 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
865 ; GFX9-NEXT: s_lshr_b32 s0, s2, 16
866 ; GFX9-NEXT: v_trunc_f16_e32 v1, s0
867 ; GFX9-NEXT: v_sub_f16_e32 v2, s0, v1
868 ; GFX9-NEXT: v_cmp_ge_f16_e64 vcc, |v2|, 0.5
869 ; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v0, vcc
870 ; GFX9-NEXT: v_mov_b32_e32 v3, s0
871 ; GFX9-NEXT: v_bfi_b32 v2, s1, v2, v3
872 ; GFX9-NEXT: v_add_f16_e32 v1, v1, v2
873 ; GFX9-NEXT: v_trunc_f16_e32 v2, s2
874 ; GFX9-NEXT: v_sub_f16_e32 v3, s2, v2
875 ; GFX9-NEXT: v_cmp_ge_f16_e64 vcc, |v3|, 0.5
876 ; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
877 ; GFX9-NEXT: v_mov_b32_e32 v3, s2
878 ; GFX9-NEXT: v_bfi_b32 v0, s1, v0, v3
879 ; GFX9-NEXT: v_add_f16_e32 v0, v2, v0
880 ; GFX9-NEXT: s_mov_b32 s6, -1
881 ; GFX9-NEXT: v_pack_b32_f16 v0, v0, v1
882 ; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0
883 ; GFX9-NEXT: s_endpgm
884 ;
885 ; GFX11-LABEL: round_v2f16:
886 ; GFX11: ; %bb.0:
887 ; GFX11-NEXT: s_clause 0x1
888 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
889 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
890 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
891 ; GFX11-NEXT: s_lshr_b32 s3, s2, 16
892 ; GFX11-NEXT: v_trunc_f16_e32 v1, s2
893 ; GFX11-NEXT: v_trunc_f16_e32 v0, s3
894 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
895 ; GFX11-NEXT: v_sub_f16_e32 v3, s2, v1
896 ; GFX11-NEXT: v_sub_f16_e32 v2, s3, v0
897 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
898 ; GFX11-NEXT: v_cmp_ge_f16_e64 s4, |v2|, 0.5
899 ; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x3c00, s4
900 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
901 ; GFX11-NEXT: v_cmp_ge_f16_e64 s4, |v3|, 0.5
902 ; GFX11-NEXT: v_bfi_b32 v2, 0x7fff, v2, s3
903 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
904 ; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x3c00, s4
905 ; GFX11-NEXT: s_mov_b32 s3, 0x31016000
906 ; GFX11-NEXT: v_add_f16_e32 v0, v0, v2
907 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
908 ; GFX11-NEXT: v_bfi_b32 v3, 0x7fff, v3, s2
909 ; GFX11-NEXT: s_mov_b32 s2, -1
910 ; GFX11-NEXT: v_add_f16_e32 v1, v1, v3
911 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
912 ; GFX11-NEXT: v_pack_b32_f16 v0, v1, v0
913 ; GFX11-NEXT: buffer_store_b32 v0, off, s[0:3], 0
914 ; GFX11-NEXT: s_nop 0
915 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
916 ; GFX11-NEXT: s_endpgm
917 ;
918 ; R600-LABEL: round_v2f16:
919 ; R600: ; %bb.0:
920 ; R600-NEXT: ALU 22, @4, KC0[CB0:0-32], KC1[]
921 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
922 ; R600-NEXT: CF_END
923 ; R600-NEXT: PAD
924 ; R600-NEXT: ALU clause starting at 4:
925 ; R600-NEXT: LSHR * T0.W, KC0[2].Z, literal.x,
926 ; R600-NEXT: 16(2.242078e-44), 0(0.000000e+00)
927 ; R600-NEXT: FLT16_TO_FLT32 * T0.W, PV.W,
928 ; R600-NEXT: FLT16_TO_FLT32 T1.W, KC0[2].Z,
929 ; R600-NEXT: TRUNC * T2.W, PV.W,
930 ; R600-NEXT: ADD T3.W, T0.W, -PS,
931 ; R600-NEXT: TRUNC * T4.W, PV.W,
932 ; R600-NEXT: ADD T5.W, T1.W, -PS,
933 ; R600-NEXT: SETGE * T3.W, |PV.W|, 0.5,
934 ; R600-NEXT: BFI_INT T0.W, literal.x, PS, T0.W,
935 ; R600-NEXT: SETGE * T3.W, |PV.W|, 0.5,
936 ; R600-NEXT: 2147483647(nan), 0(0.000000e+00)
937 ; R600-NEXT: BFI_INT T1.W, literal.x, PS, T1.W, BS:VEC_021/SCL_122
938 ; R600-NEXT: ADD * T0.W, T2.W, PV.W,
939 ; R600-NEXT: 2147483647(nan), 0(0.000000e+00)
940 ; R600-NEXT: FLT32_TO_FLT16 T0.W, PS,
941 ; R600-NEXT: ADD * T1.W, T4.W, PV.W,
942 ; R600-NEXT: FLT32_TO_FLT16 T1.W, PS,
943 ; R600-NEXT: LSHL * T0.W, PV.W, literal.x,
944 ; R600-NEXT: 16(2.242078e-44), 0(0.000000e+00)
945 ; R600-NEXT: OR_INT T0.X, PV.W, PS,
946 ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
947 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
948 %in = bitcast i32 %in.arg to <2 x half>
949 %result = call <2 x half> @llvm.round.v2f16(<2 x half> %in)
950 store <2 x half> %result, ptr addrspace(1) %out
951 ret void
952 }
954 declare float @llvm.round.f32(float) #1
955 declare <2 x float> @llvm.round.v2f32(<2 x float>) #1
956 declare <4 x float> @llvm.round.v4f32(<4 x float>) #1
957 declare <8 x float> @llvm.round.v8f32(<8 x float>) #1
959 declare half @llvm.round.f16(half) #1
960 declare <2 x half> @llvm.round.v2f16(<2 x half>) #1
961 declare <4 x half> @llvm.round.v4f16(<4 x half>) #1
962 declare <8 x half> @llvm.round.v8f16(<8 x half>) #1
964 attributes #0 = { nounwind }
965 attributes #1 = { nounwind readnone }