| blob | 9cb6842ae0a18272ca3e54c70e61f1f010d5615d |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3 ; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
5 define amdgpu_kernel void @s_test_sdiv(ptr addrspace(1) %out, i64 %x, i64 %y) {
6 ; GCN-LABEL: s_test_sdiv:
7 ; GCN: ; %bb.0:
8 ; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd
9 ; GCN-NEXT: s_mov_b32 s7, 0xf000
10 ; GCN-NEXT: s_mov_b32 s6, -1
11 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
12 ; GCN-NEXT: s_ashr_i32 s8, s3, 31
13 ; GCN-NEXT: s_add_u32 s2, s2, s8
14 ; GCN-NEXT: s_mov_b32 s9, s8
15 ; GCN-NEXT: s_addc_u32 s3, s3, s8
16 ; GCN-NEXT: s_xor_b64 s[10:11], s[2:3], s[8:9]
17 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s10
18 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, s11
19 ; GCN-NEXT: s_sub_u32 s4, 0, s10
20 ; GCN-NEXT: s_subb_u32 s5, 0, s11
21 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
22 ; GCN-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0
23 ; GCN-NEXT: v_rcp_f32_e32 v0, v0
24 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
25 ; GCN-NEXT: s_ashr_i32 s12, s3, 31
26 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
27 ; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
28 ; GCN-NEXT: v_trunc_f32_e32 v1, v1
29 ; GCN-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
30 ; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
31 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
32 ; GCN-NEXT: s_add_u32 s2, s2, s12
33 ; GCN-NEXT: s_mov_b32 s13, s12
34 ; GCN-NEXT: v_mul_lo_u32 v2, s4, v1
35 ; GCN-NEXT: v_mul_hi_u32 v3, s4, v0
36 ; GCN-NEXT: v_mul_lo_u32 v5, s5, v0
37 ; GCN-NEXT: v_mul_lo_u32 v4, s4, v0
38 ; GCN-NEXT: s_addc_u32 s3, s3, s12
39 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
40 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5
41 ; GCN-NEXT: v_mul_hi_u32 v3, v0, v4
42 ; GCN-NEXT: v_mul_lo_u32 v5, v0, v2
43 ; GCN-NEXT: v_mul_hi_u32 v7, v0, v2
44 ; GCN-NEXT: v_mul_lo_u32 v6, v1, v4
45 ; GCN-NEXT: v_mul_hi_u32 v4, v1, v4
46 ; GCN-NEXT: v_mul_hi_u32 v8, v1, v2
47 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
48 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc
49 ; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
50 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6
51 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc
52 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v8, vcc
53 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
54 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
55 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
56 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
57 ; GCN-NEXT: v_mul_lo_u32 v2, s4, v1
58 ; GCN-NEXT: v_mul_hi_u32 v3, s4, v0
59 ; GCN-NEXT: v_mul_lo_u32 v4, s5, v0
60 ; GCN-NEXT: s_xor_b64 s[2:3], s[2:3], s[12:13]
61 ; GCN-NEXT: s_mov_b32 s5, s1
62 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
63 ; GCN-NEXT: v_mul_lo_u32 v3, s4, v0
64 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
65 ; GCN-NEXT: v_mul_lo_u32 v6, v0, v2
66 ; GCN-NEXT: v_mul_hi_u32 v7, v0, v3
67 ; GCN-NEXT: v_mul_hi_u32 v8, v0, v2
68 ; GCN-NEXT: v_mul_hi_u32 v5, v1, v3
69 ; GCN-NEXT: v_mul_lo_u32 v3, v1, v3
70 ; GCN-NEXT: v_mul_hi_u32 v4, v1, v2
71 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
72 ; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc
73 ; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
74 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3
75 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v7, v5, vcc
76 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
77 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
78 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
79 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
80 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
81 ; GCN-NEXT: v_mul_lo_u32 v2, s2, v1
82 ; GCN-NEXT: v_mul_hi_u32 v3, s2, v0
83 ; GCN-NEXT: v_mul_hi_u32 v4, s2, v1
84 ; GCN-NEXT: v_mul_hi_u32 v5, s3, v1
85 ; GCN-NEXT: v_mul_lo_u32 v1, s3, v1
86 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
87 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
88 ; GCN-NEXT: v_mul_lo_u32 v4, s3, v0
89 ; GCN-NEXT: v_mul_hi_u32 v0, s3, v0
90 ; GCN-NEXT: s_mov_b32 s4, s0
91 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
92 ; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
93 ; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
94 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
95 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
96 ; GCN-NEXT: v_mul_lo_u32 v2, s10, v1
97 ; GCN-NEXT: v_mul_hi_u32 v3, s10, v0
98 ; GCN-NEXT: v_mul_lo_u32 v4, s11, v0
99 ; GCN-NEXT: v_mov_b32_e32 v5, s11
100 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
101 ; GCN-NEXT: v_mul_lo_u32 v3, s10, v0
102 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v4, v2
103 ; GCN-NEXT: v_sub_i32_e32 v4, vcc, s3, v2
104 ; GCN-NEXT: v_sub_i32_e32 v3, vcc, s2, v3
105 ; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
106 ; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s10, v3
107 ; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
108 ; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v4
109 ; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
110 ; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v5
111 ; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
112 ; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v4
113 ; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1]
114 ; GCN-NEXT: v_add_i32_e64 v5, s[0:1], 1, v0
115 ; GCN-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
116 ; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 2, v0
117 ; GCN-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
118 ; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
119 ; GCN-NEXT: v_cndmask_b32_e64 v4, v5, v7, s[0:1]
120 ; GCN-NEXT: v_cndmask_b32_e64 v5, v6, v8, s[0:1]
121 ; GCN-NEXT: v_mov_b32_e32 v6, s3
122 ; GCN-NEXT: v_subb_u32_e32 v2, vcc, v6, v2, vcc
123 ; GCN-NEXT: v_cmp_le_u32_e32 vcc, s11, v2
124 ; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
125 ; GCN-NEXT: v_cmp_le_u32_e32 vcc, s10, v3
126 ; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
127 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s11, v2
128 ; GCN-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc
129 ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
130 ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
131 ; GCN-NEXT: s_xor_b64 s[0:1], s[12:13], s[8:9]
132 ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
133 ; GCN-NEXT: v_xor_b32_e32 v0, s0, v0
134 ; GCN-NEXT: v_xor_b32_e32 v1, s1, v1
135 ; GCN-NEXT: v_mov_b32_e32 v2, s1
136 ; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
137 ; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
138 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
139 ; GCN-NEXT: s_endpgm
140 ;
141 ; GCN-IR-LABEL: s_test_sdiv:
142 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
143 ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
144 ; GCN-IR-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
145 ; GCN-IR-NEXT: s_mov_b32 s15, 0
146 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
147 ; GCN-IR-NEXT: s_ashr_i32 s0, s7, 31
148 ; GCN-IR-NEXT: s_mov_b32 s1, s0
149 ; GCN-IR-NEXT: s_ashr_i32 s2, s9, 31
150 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[0:1], s[6:7]
151 ; GCN-IR-NEXT: s_mov_b32 s3, s2
152 ; GCN-IR-NEXT: s_sub_u32 s12, s6, s0
153 ; GCN-IR-NEXT: s_subb_u32 s13, s7, s0
154 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[2:3], s[8:9]
155 ; GCN-IR-NEXT: s_sub_u32 s6, s6, s2
156 ; GCN-IR-NEXT: s_subb_u32 s7, s7, s2
157 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[12:13], 0
158 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[6:7], 0
159 ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[8:9]
160 ; GCN-IR-NEXT: s_flbit_i32_b32 s8, s6
161 ; GCN-IR-NEXT: s_add_i32 s8, s8, 32
162 ; GCN-IR-NEXT: s_flbit_i32_b32 s9, s7
163 ; GCN-IR-NEXT: s_min_u32 s14, s8, s9
164 ; GCN-IR-NEXT: s_flbit_i32_b32 s8, s12
165 ; GCN-IR-NEXT: s_add_i32 s8, s8, 32
166 ; GCN-IR-NEXT: s_flbit_i32_b32 s9, s13
167 ; GCN-IR-NEXT: s_min_u32 s18, s8, s9
168 ; GCN-IR-NEXT: s_sub_u32 s16, s14, s18
169 ; GCN-IR-NEXT: s_subb_u32 s17, 0, 0
170 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[20:21], s[16:17], 63
171 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[22:23], s[16:17], 63
172 ; GCN-IR-NEXT: s_or_b64 s[20:21], s[10:11], s[20:21]
173 ; GCN-IR-NEXT: s_and_b64 s[10:11], s[20:21], exec
174 ; GCN-IR-NEXT: s_cselect_b32 s11, 0, s13
175 ; GCN-IR-NEXT: s_cselect_b32 s10, 0, s12
176 ; GCN-IR-NEXT: s_or_b64 s[20:21], s[20:21], s[22:23]
177 ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
178 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[20:21]
179 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_5
180 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
181 ; GCN-IR-NEXT: s_add_u32 s20, s16, 1
182 ; GCN-IR-NEXT: s_addc_u32 s21, s17, 0
183 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[20:21], 0
184 ; GCN-IR-NEXT: s_sub_i32 s16, 63, s16
185 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11]
186 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[12:13], s16
187 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_4
188 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
189 ; GCN-IR-NEXT: s_lshr_b64 s[16:17], s[12:13], s20
190 ; GCN-IR-NEXT: s_add_u32 s19, s6, -1
191 ; GCN-IR-NEXT: s_addc_u32 s20, s7, -1
192 ; GCN-IR-NEXT: s_not_b64 s[8:9], s[14:15]
193 ; GCN-IR-NEXT: s_add_u32 s12, s8, s18
194 ; GCN-IR-NEXT: s_addc_u32 s13, s9, 0
195 ; GCN-IR-NEXT: s_mov_b64 s[14:15], 0
196 ; GCN-IR-NEXT: s_mov_b32 s9, 0
197 ; GCN-IR-NEXT: .LBB0_3: ; %udiv-do-while
198 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
199 ; GCN-IR-NEXT: s_lshl_b64 s[16:17], s[16:17], 1
200 ; GCN-IR-NEXT: s_lshr_b32 s8, s11, 31
201 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
202 ; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[8:9]
203 ; GCN-IR-NEXT: s_or_b64 s[10:11], s[14:15], s[10:11]
204 ; GCN-IR-NEXT: s_sub_u32 s8, s19, s16
205 ; GCN-IR-NEXT: s_subb_u32 s8, s20, s17
206 ; GCN-IR-NEXT: s_ashr_i32 s14, s8, 31
207 ; GCN-IR-NEXT: s_mov_b32 s15, s14
208 ; GCN-IR-NEXT: s_and_b32 s8, s14, 1
209 ; GCN-IR-NEXT: s_and_b64 s[14:15], s[14:15], s[6:7]
210 ; GCN-IR-NEXT: s_sub_u32 s16, s16, s14
211 ; GCN-IR-NEXT: s_subb_u32 s17, s17, s15
212 ; GCN-IR-NEXT: s_add_u32 s12, s12, 1
213 ; GCN-IR-NEXT: s_addc_u32 s13, s13, 0
214 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[22:23], s[12:13], 0
215 ; GCN-IR-NEXT: s_mov_b64 s[14:15], s[8:9]
216 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[22:23]
217 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_3
218 ; GCN-IR-NEXT: .LBB0_4: ; %Flow7
219 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[10:11], 1
220 ; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[6:7]
221 ; GCN-IR-NEXT: .LBB0_5: ; %udiv-end
222 ; GCN-IR-NEXT: s_xor_b64 s[0:1], s[2:3], s[0:1]
223 ; GCN-IR-NEXT: s_xor_b64 s[2:3], s[10:11], s[0:1]
224 ; GCN-IR-NEXT: s_sub_u32 s0, s2, s0
225 ; GCN-IR-NEXT: s_subb_u32 s1, s3, s1
226 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s0
227 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
228 ; GCN-IR-NEXT: s_mov_b32 s6, -1
229 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s1
230 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
231 ; GCN-IR-NEXT: s_endpgm
232 %result = sdiv i64 %x, %y
233 store i64 %result, ptr addrspace(1) %out
234 ret void
235 }
237 define i64 @v_test_sdiv(i64 %x, i64 %y) {
238 ; GCN-LABEL: v_test_sdiv:
239 ; GCN: ; %bb.0:
240 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
241 ; GCN-NEXT: v_ashrrev_i32_e32 v4, 31, v3
242 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v2, v4
243 ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v3, v4, vcc
244 ; GCN-NEXT: v_xor_b32_e32 v2, v2, v4
245 ; GCN-NEXT: v_xor_b32_e32 v3, v5, v4
246 ; GCN-NEXT: v_cvt_f32_u32_e32 v5, v3
247 ; GCN-NEXT: v_cvt_f32_u32_e32 v6, v2
248 ; GCN-NEXT: v_sub_i32_e32 v7, vcc, 0, v3
249 ; GCN-NEXT: v_subb_u32_e32 v8, vcc, 0, v2, vcc
250 ; GCN-NEXT: v_madmk_f32 v5, v6, 0x4f800000, v5
251 ; GCN-NEXT: v_rcp_f32_e32 v5, v5
252 ; GCN-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
253 ; GCN-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5
254 ; GCN-NEXT: v_trunc_f32_e32 v6, v6
255 ; GCN-NEXT: v_madmk_f32 v5, v6, 0xcf800000, v5
256 ; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5
257 ; GCN-NEXT: v_cvt_u32_f32_e32 v6, v6
258 ; GCN-NEXT: v_mul_hi_u32 v9, v7, v5
259 ; GCN-NEXT: v_mul_lo_u32 v10, v7, v6
260 ; GCN-NEXT: v_mul_lo_u32 v11, v8, v5
261 ; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v10
262 ; GCN-NEXT: v_mul_lo_u32 v10, v7, v5
263 ; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v11
264 ; GCN-NEXT: v_mul_lo_u32 v11, v5, v9
265 ; GCN-NEXT: v_mul_hi_u32 v12, v5, v10
266 ; GCN-NEXT: v_mul_hi_u32 v13, v5, v9
267 ; GCN-NEXT: v_mul_hi_u32 v14, v6, v9
268 ; GCN-NEXT: v_mul_lo_u32 v9, v6, v9
269 ; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11
270 ; GCN-NEXT: v_addc_u32_e32 v12, vcc, 0, v13, vcc
271 ; GCN-NEXT: v_mul_lo_u32 v13, v6, v10
272 ; GCN-NEXT: v_mul_hi_u32 v10, v6, v10
273 ; GCN-NEXT: v_add_i32_e32 v11, vcc, v11, v13
274 ; GCN-NEXT: v_addc_u32_e32 v10, vcc, v12, v10, vcc
275 ; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v14, vcc
276 ; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9
277 ; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v11, vcc
278 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v9
279 ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v10, vcc
280 ; GCN-NEXT: v_mul_lo_u32 v9, v7, v6
281 ; GCN-NEXT: v_mul_hi_u32 v10, v7, v5
282 ; GCN-NEXT: v_mul_lo_u32 v8, v8, v5
283 ; GCN-NEXT: v_mul_lo_u32 v7, v7, v5
284 ; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9
285 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
286 ; GCN-NEXT: v_mul_lo_u32 v11, v5, v8
287 ; GCN-NEXT: v_mul_hi_u32 v12, v5, v7
288 ; GCN-NEXT: v_mul_hi_u32 v13, v5, v8
289 ; GCN-NEXT: v_mul_hi_u32 v10, v6, v7
290 ; GCN-NEXT: v_mul_lo_u32 v7, v6, v7
291 ; GCN-NEXT: v_mul_hi_u32 v9, v6, v8
292 ; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11
293 ; GCN-NEXT: v_addc_u32_e32 v12, vcc, 0, v13, vcc
294 ; GCN-NEXT: v_mul_lo_u32 v8, v6, v8
295 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v11, v7
296 ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v10, vcc
297 ; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
298 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8
299 ; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc
300 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
301 ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v8, vcc
302 ; GCN-NEXT: v_ashrrev_i32_e32 v7, 31, v1
303 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v7
304 ; GCN-NEXT: v_xor_b32_e32 v0, v0, v7
305 ; GCN-NEXT: v_mul_lo_u32 v8, v0, v6
306 ; GCN-NEXT: v_mul_hi_u32 v9, v0, v5
307 ; GCN-NEXT: v_mul_hi_u32 v10, v0, v6
308 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v7, vcc
309 ; GCN-NEXT: v_xor_b32_e32 v1, v1, v7
310 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
311 ; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc
312 ; GCN-NEXT: v_mul_lo_u32 v10, v1, v5
313 ; GCN-NEXT: v_mul_hi_u32 v5, v1, v5
314 ; GCN-NEXT: v_mul_hi_u32 v11, v1, v6
315 ; GCN-NEXT: v_mul_lo_u32 v6, v1, v6
316 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10
317 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc
318 ; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v11, vcc
319 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6
320 ; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v8, vcc
321 ; GCN-NEXT: v_mul_lo_u32 v8, v3, v6
322 ; GCN-NEXT: v_mul_hi_u32 v9, v3, v5
323 ; GCN-NEXT: v_mul_lo_u32 v10, v2, v5
324 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
325 ; GCN-NEXT: v_mul_lo_u32 v9, v3, v5
326 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10
327 ; GCN-NEXT: v_sub_i32_e32 v10, vcc, v1, v8
328 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v9
329 ; GCN-NEXT: v_subb_u32_e64 v9, s[4:5], v10, v2, vcc
330 ; GCN-NEXT: v_sub_i32_e64 v10, s[4:5], v0, v3
331 ; GCN-NEXT: v_subbrev_u32_e64 v9, s[4:5], 0, v9, s[4:5]
332 ; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v9, v2
333 ; GCN-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5]
334 ; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v10, v3
335 ; GCN-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5]
336 ; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v9, v2
337 ; GCN-NEXT: v_cndmask_b32_e64 v9, v11, v10, s[4:5]
338 ; GCN-NEXT: v_add_i32_e64 v10, s[4:5], 2, v5
339 ; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v8, vcc
340 ; GCN-NEXT: v_addc_u32_e64 v11, s[4:5], 0, v6, s[4:5]
341 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v2
342 ; GCN-NEXT: v_add_i32_e64 v12, s[4:5], 1, v5
343 ; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
344 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3
345 ; GCN-NEXT: v_addc_u32_e64 v13, s[4:5], 0, v6, s[4:5]
346 ; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
347 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
348 ; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v9
349 ; GCN-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
350 ; GCN-NEXT: v_cndmask_b32_e64 v9, v13, v11, s[4:5]
351 ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
352 ; GCN-NEXT: v_cndmask_b32_e64 v1, v12, v10, s[4:5]
353 ; GCN-NEXT: v_cndmask_b32_e32 v0, v6, v9, vcc
354 ; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
355 ; GCN-NEXT: v_xor_b32_e32 v2, v7, v4
356 ; GCN-NEXT: v_xor_b32_e32 v3, v0, v2
357 ; GCN-NEXT: v_xor_b32_e32 v0, v1, v2
358 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
359 ; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v2, vcc
360 ; GCN-NEXT: s_setpc_b64 s[30:31]
361 ;
362 ; GCN-IR-LABEL: v_test_sdiv:
363 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
364 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
365 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v4, 31, v1
366 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v4, v0
367 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v5, 31, v3
368 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v4, v1
369 ; GCN-IR-NEXT: v_sub_i32_e32 v10, vcc, v0, v4
370 ; GCN-IR-NEXT: v_subb_u32_e32 v11, vcc, v1, v4, vcc
371 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v5, v2
372 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v5, v3
373 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v5
374 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc
375 ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0
376 ; GCN-IR-NEXT: v_add_i32_e64 v2, s[6:7], 32, v2
377 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
378 ; GCN-IR-NEXT: v_min_u32_e32 v12, v2, v3
379 ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v10
380 ; GCN-IR-NEXT: v_add_i32_e64 v2, s[6:7], 32, v2
381 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v11
382 ; GCN-IR-NEXT: v_min_u32_e32 v13, v2, v3
383 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[6:7], v12, v13
384 ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
385 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[10:11]
386 ; GCN-IR-NEXT: v_subb_u32_e64 v3, s[6:7], 0, 0, s[6:7]
387 ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[6:7], 63, v[2:3]
388 ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
389 ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
390 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[2:3]
391 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
392 ; GCN-IR-NEXT: v_mov_b32_e32 v6, v4
393 ; GCN-IR-NEXT: v_mov_b32_e32 v7, v5
394 ; GCN-IR-NEXT: v_cndmask_b32_e64 v9, v11, 0, s[4:5]
395 ; GCN-IR-NEXT: v_cndmask_b32_e64 v8, v10, 0, s[4:5]
396 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
397 ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
398 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_6
399 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
400 ; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, 1, v2
401 ; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, 0, v3, vcc
402 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2
403 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[14:15]
404 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[10:11], v2
405 ; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
406 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
407 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
408 ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
409 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_5
410 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
411 ; GCN-IR-NEXT: v_add_i32_e32 v16, vcc, -1, v0
412 ; GCN-IR-NEXT: v_addc_u32_e32 v17, vcc, -1, v1, vcc
413 ; GCN-IR-NEXT: v_not_b32_e32 v9, v12
414 ; GCN-IR-NEXT: v_lshr_b64 v[14:15], v[10:11], v14
415 ; GCN-IR-NEXT: v_not_b32_e32 v8, 0
416 ; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, v9, v13
417 ; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
418 ; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v8, vcc
419 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
420 ; GCN-IR-NEXT: v_mov_b32_e32 v13, 0
421 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
422 ; GCN-IR-NEXT: .LBB1_3: ; %udiv-do-while
423 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
424 ; GCN-IR-NEXT: v_lshl_b64 v[14:15], v[14:15], 1
425 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v8, 31, v3
426 ; GCN-IR-NEXT: v_or_b32_e32 v14, v14, v8
427 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
428 ; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, v16, v14
429 ; GCN-IR-NEXT: v_subb_u32_e32 v8, vcc, v17, v15, vcc
430 ; GCN-IR-NEXT: v_or_b32_e32 v2, v12, v2
431 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v8
432 ; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v10
433 ; GCN-IR-NEXT: v_or_b32_e32 v3, v13, v3
434 ; GCN-IR-NEXT: v_and_b32_e32 v8, 1, v12
435 ; GCN-IR-NEXT: v_and_b32_e32 v13, v12, v1
436 ; GCN-IR-NEXT: v_and_b32_e32 v12, v12, v0
437 ; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
438 ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11]
439 ; GCN-IR-NEXT: v_sub_i32_e64 v14, s[4:5], v14, v12
440 ; GCN-IR-NEXT: v_subb_u32_e64 v15, s[4:5], v15, v13, s[4:5]
441 ; GCN-IR-NEXT: v_mov_b32_e32 v13, v9
442 ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
443 ; GCN-IR-NEXT: v_mov_b32_e32 v12, v8
444 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
445 ; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3
446 ; GCN-IR-NEXT: ; %bb.4: ; %Flow
447 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
448 ; GCN-IR-NEXT: .LBB1_5: ; %Flow4
449 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
450 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1
451 ; GCN-IR-NEXT: v_or_b32_e32 v9, v9, v1
452 ; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v0
453 ; GCN-IR-NEXT: .LBB1_6: ; %Flow5
454 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
455 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v5, v4
456 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v7, v6
457 ; GCN-IR-NEXT: v_xor_b32_e32 v3, v8, v0
458 ; GCN-IR-NEXT: v_xor_b32_e32 v2, v9, v1
459 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v3, v0
460 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc
461 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
462 %result = sdiv i64 %x, %y
463 ret i64 %result
464 }
466 define amdgpu_kernel void @s_test_sdiv24_64(ptr addrspace(1) %out, i64 %x, i64 %y) {
467 ; GCN-LABEL: s_test_sdiv24_64:
468 ; GCN: ; %bb.0:
469 ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
470 ; GCN-NEXT: s_load_dword s1, s[0:1], 0xe
471 ; GCN-NEXT: s_mov_b32 s3, 0xf000
472 ; GCN-NEXT: s_mov_b32 s2, -1
473 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
474 ; GCN-NEXT: s_mov_b32 s0, s4
475 ; GCN-NEXT: s_ashr_i64 s[8:9], s[0:1], 40
476 ; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8
477 ; GCN-NEXT: s_mov_b32 s1, s5
478 ; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 40
479 ; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4
480 ; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
481 ; GCN-NEXT: s_xor_b32 s4, s4, s8
482 ; GCN-NEXT: s_ashr_i32 s4, s4, 30
483 ; GCN-NEXT: s_or_b32 s6, s4, 1
484 ; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
485 ; GCN-NEXT: v_trunc_f32_e32 v2, v2
486 ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
487 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
488 ; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0|
489 ; GCN-NEXT: s_and_b64 s[4:5], s[4:5], exec
490 ; GCN-NEXT: s_cselect_b32 s4, s6, 0
491 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v2
492 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
493 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
494 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
495 ; GCN-NEXT: s_endpgm
496 ;
497 ; GCN-IR-LABEL: s_test_sdiv24_64:
498 ; GCN-IR: ; %bb.0:
499 ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
500 ; GCN-IR-NEXT: s_load_dword s1, s[0:1], 0xe
501 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
502 ; GCN-IR-NEXT: s_mov_b32 s2, -1
503 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
504 ; GCN-IR-NEXT: s_mov_b32 s0, s4
505 ; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[0:1], 40
506 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8
507 ; GCN-IR-NEXT: s_mov_b32 s1, s5
508 ; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 40
509 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s4
510 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
511 ; GCN-IR-NEXT: s_xor_b32 s4, s4, s8
512 ; GCN-IR-NEXT: s_ashr_i32 s4, s4, 30
513 ; GCN-IR-NEXT: s_or_b32 s6, s4, 1
514 ; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
515 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
516 ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
517 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2
518 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0|
519 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], exec
520 ; GCN-IR-NEXT: s_cselect_b32 s4, s6, 0
521 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v2
522 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24
523 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
524 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
525 ; GCN-IR-NEXT: s_endpgm
526 %1 = ashr i64 %x, 40
527 %2 = ashr i64 %y, 40
528 %result = sdiv i64 %1, %2
529 store i64 %result, ptr addrspace(1) %out
530 ret void
531 }
533 define i64 @v_test_sdiv24_64(i64 %x, i64 %y) {
534 ; GCN-LABEL: v_test_sdiv24_64:
535 ; GCN: ; %bb.0:
536 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
537 ; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v3
538 ; GCN-NEXT: v_cvt_f32_i32_e32 v0, v0
539 ; GCN-NEXT: v_lshrrev_b32_e32 v1, 8, v1
540 ; GCN-NEXT: v_cvt_f32_i32_e32 v1, v1
541 ; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
542 ; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
543 ; GCN-NEXT: v_trunc_f32_e32 v2, v2
544 ; GCN-NEXT: v_cvt_i32_f32_e32 v3, v2
545 ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
546 ; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
547 ; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
548 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 25
549 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
550 ; GCN-NEXT: s_setpc_b64 s[30:31]
551 ;
552 ; GCN-IR-LABEL: v_test_sdiv24_64:
553 ; GCN-IR: ; %bb.0:
554 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
555 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v3
556 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, v0
557 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v1, 8, v1
558 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, v1
559 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
560 ; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
561 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
562 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v3, v2
563 ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
564 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0|
565 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
566 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 25
567 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
568 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
569 %1 = lshr i64 %x, 40
570 %2 = lshr i64 %y, 40
571 %result = sdiv i64 %1, %2
572 ret i64 %result
573 }
575 define amdgpu_kernel void @s_test_sdiv32_64(ptr addrspace(1) %out, i64 %x, i64 %y) {
576 ; GCN-LABEL: s_test_sdiv32_64:
577 ; GCN: ; %bb.0:
578 ; GCN-NEXT: s_load_dword s8, s[0:1], 0xe
579 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
580 ; GCN-NEXT: s_mov_b32 s7, 0xf000
581 ; GCN-NEXT: s_mov_b32 s6, -1
582 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
583 ; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8
584 ; GCN-NEXT: v_cvt_f32_i32_e32 v1, s3
585 ; GCN-NEXT: s_mov_b32 s4, s0
586 ; GCN-NEXT: s_xor_b32 s0, s3, s8
587 ; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
588 ; GCN-NEXT: s_ashr_i32 s0, s0, 30
589 ; GCN-NEXT: s_mov_b32 s5, s1
590 ; GCN-NEXT: s_or_b32 s2, s0, 1
591 ; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
592 ; GCN-NEXT: v_trunc_f32_e32 v2, v2
593 ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
594 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
595 ; GCN-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, |v0|
596 ; GCN-NEXT: s_and_b64 s[0:1], s[0:1], exec
597 ; GCN-NEXT: s_cselect_b32 s0, s2, 0
598 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v2
599 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
600 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
601 ; GCN-NEXT: s_endpgm
602 ;
603 ; GCN-IR-LABEL: s_test_sdiv32_64:
604 ; GCN-IR: ; %bb.0:
605 ; GCN-IR-NEXT: s_load_dword s8, s[0:1], 0xe
606 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
607 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
608 ; GCN-IR-NEXT: s_mov_b32 s6, -1
609 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
610 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8
611 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s3
612 ; GCN-IR-NEXT: s_mov_b32 s4, s0
613 ; GCN-IR-NEXT: s_xor_b32 s0, s3, s8
614 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
615 ; GCN-IR-NEXT: s_ashr_i32 s0, s0, 30
616 ; GCN-IR-NEXT: s_mov_b32 s5, s1
617 ; GCN-IR-NEXT: s_or_b32 s2, s0, 1
618 ; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
619 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
620 ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
621 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2
622 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, |v0|
623 ; GCN-IR-NEXT: s_and_b64 s[0:1], s[0:1], exec
624 ; GCN-IR-NEXT: s_cselect_b32 s0, s2, 0
625 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s0, v2
626 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
627 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
628 ; GCN-IR-NEXT: s_endpgm
629 %1 = ashr i64 %x, 32
630 %2 = ashr i64 %y, 32
631 %result = sdiv i64 %1, %2
632 store i64 %result, ptr addrspace(1) %out
633 ret void
634 }
636 define amdgpu_kernel void @s_test_sdiv31_64(ptr addrspace(1) %out, i64 %x, i64 %y) {
637 ; GCN-LABEL: s_test_sdiv31_64:
638 ; GCN: ; %bb.0:
639 ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
640 ; GCN-NEXT: s_load_dword s1, s[0:1], 0xe
641 ; GCN-NEXT: s_mov_b32 s3, 0xf000
642 ; GCN-NEXT: s_mov_b32 s2, -1
643 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
644 ; GCN-NEXT: s_mov_b32 s0, s4
645 ; GCN-NEXT: s_ashr_i64 s[8:9], s[0:1], 33
646 ; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8
647 ; GCN-NEXT: s_mov_b32 s1, s5
648 ; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 33
649 ; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4
650 ; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
651 ; GCN-NEXT: s_xor_b32 s4, s4, s8
652 ; GCN-NEXT: s_ashr_i32 s4, s4, 30
653 ; GCN-NEXT: s_or_b32 s6, s4, 1
654 ; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
655 ; GCN-NEXT: v_trunc_f32_e32 v2, v2
656 ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
657 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
658 ; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0|
659 ; GCN-NEXT: s_and_b64 s[4:5], s[4:5], exec
660 ; GCN-NEXT: s_cselect_b32 s4, s6, 0
661 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v2
662 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 31
663 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
664 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
665 ; GCN-NEXT: s_endpgm
666 ;
667 ; GCN-IR-LABEL: s_test_sdiv31_64:
668 ; GCN-IR: ; %bb.0:
669 ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
670 ; GCN-IR-NEXT: s_load_dword s1, s[0:1], 0xe
671 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
672 ; GCN-IR-NEXT: s_mov_b32 s2, -1
673 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
674 ; GCN-IR-NEXT: s_mov_b32 s0, s4
675 ; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[0:1], 33
676 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8
677 ; GCN-IR-NEXT: s_mov_b32 s1, s5
678 ; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 33
679 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s4
680 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
681 ; GCN-IR-NEXT: s_xor_b32 s4, s4, s8
682 ; GCN-IR-NEXT: s_ashr_i32 s4, s4, 30
683 ; GCN-IR-NEXT: s_or_b32 s6, s4, 1
684 ; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
685 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
686 ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
687 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2
688 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0|
689 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], exec
690 ; GCN-IR-NEXT: s_cselect_b32 s4, s6, 0
691 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v2
692 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 31
693 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
694 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
695 ; GCN-IR-NEXT: s_endpgm
696 %1 = ashr i64 %x, 33
697 %2 = ashr i64 %y, 33
698 %result = sdiv i64 %1, %2
699 store i64 %result, ptr addrspace(1) %out
700 ret void
701 }
703 define amdgpu_kernel void @s_test_sdiv23_64(ptr addrspace(1) %out, i64 %x, i64 %y) {
704 ; GCN-LABEL: s_test_sdiv23_64:
705 ; GCN: ; %bb.0:
706 ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
707 ; GCN-NEXT: s_load_dword s1, s[0:1], 0xe
708 ; GCN-NEXT: s_mov_b32 s3, 0xf000
709 ; GCN-NEXT: s_mov_b32 s2, -1
710 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
711 ; GCN-NEXT: s_mov_b32 s0, s4
712 ; GCN-NEXT: s_ashr_i64 s[8:9], s[0:1], 41
713 ; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8
714 ; GCN-NEXT: s_mov_b32 s1, s5
715 ; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 41
716 ; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4
717 ; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
718 ; GCN-NEXT: s_xor_b32 s4, s4, s8
719 ; GCN-NEXT: s_ashr_i32 s4, s4, 30
720 ; GCN-NEXT: s_or_b32 s6, s4, 1
721 ; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
722 ; GCN-NEXT: v_trunc_f32_e32 v2, v2
723 ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
724 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
725 ; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0|
726 ; GCN-NEXT: s_and_b64 s[4:5], s[4:5], exec
727 ; GCN-NEXT: s_cselect_b32 s4, s6, 0
728 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v2
729 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 23
730 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
731 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
732 ; GCN-NEXT: s_endpgm
733 ;
734 ; GCN-IR-LABEL: s_test_sdiv23_64:
735 ; GCN-IR: ; %bb.0:
736 ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
737 ; GCN-IR-NEXT: s_load_dword s1, s[0:1], 0xe
738 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
739 ; GCN-IR-NEXT: s_mov_b32 s2, -1
740 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
741 ; GCN-IR-NEXT: s_mov_b32 s0, s4
742 ; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[0:1], 41
743 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8
744 ; GCN-IR-NEXT: s_mov_b32 s1, s5
745 ; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 41
746 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s4
747 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
748 ; GCN-IR-NEXT: s_xor_b32 s4, s4, s8
749 ; GCN-IR-NEXT: s_ashr_i32 s4, s4, 30
750 ; GCN-IR-NEXT: s_or_b32 s6, s4, 1
751 ; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
752 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
753 ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
754 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2
755 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0|
756 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], exec
757 ; GCN-IR-NEXT: s_cselect_b32 s4, s6, 0
758 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v2
759 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 23
760 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
761 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
762 ; GCN-IR-NEXT: s_endpgm
763 %1 = ashr i64 %x, 41
764 %2 = ashr i64 %y, 41
765 %result = sdiv i64 %1, %2
766 store i64 %result, ptr addrspace(1) %out
767 ret void
768 }
770 define amdgpu_kernel void @s_test_sdiv25_64(ptr addrspace(1) %out, i64 %x, i64 %y) {
771 ; GCN-LABEL: s_test_sdiv25_64:
772 ; GCN: ; %bb.0:
773 ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
774 ; GCN-NEXT: s_load_dword s1, s[0:1], 0xe
775 ; GCN-NEXT: s_mov_b32 s3, 0xf000
776 ; GCN-NEXT: s_mov_b32 s2, -1
777 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
778 ; GCN-NEXT: s_mov_b32 s0, s4
779 ; GCN-NEXT: s_ashr_i64 s[8:9], s[0:1], 39
780 ; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8
781 ; GCN-NEXT: s_mov_b32 s1, s5
782 ; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 39
783 ; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4
784 ; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
785 ; GCN-NEXT: s_xor_b32 s4, s4, s8
786 ; GCN-NEXT: s_ashr_i32 s4, s4, 30
787 ; GCN-NEXT: s_or_b32 s6, s4, 1
788 ; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
789 ; GCN-NEXT: v_trunc_f32_e32 v2, v2
790 ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
791 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
792 ; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0|
793 ; GCN-NEXT: s_and_b64 s[4:5], s[4:5], exec
794 ; GCN-NEXT: s_cselect_b32 s4, s6, 0
795 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v2
796 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 25
797 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
798 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
799 ; GCN-NEXT: s_endpgm
800 ;
801 ; GCN-IR-LABEL: s_test_sdiv25_64:
802 ; GCN-IR: ; %bb.0:
803 ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
804 ; GCN-IR-NEXT: s_load_dword s1, s[0:1], 0xe
805 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
806 ; GCN-IR-NEXT: s_mov_b32 s2, -1
807 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
808 ; GCN-IR-NEXT: s_mov_b32 s0, s4
809 ; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[0:1], 39
810 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8
811 ; GCN-IR-NEXT: s_mov_b32 s1, s5
812 ; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 39
813 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s4
814 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
815 ; GCN-IR-NEXT: s_xor_b32 s4, s4, s8
816 ; GCN-IR-NEXT: s_ashr_i32 s4, s4, 30
817 ; GCN-IR-NEXT: s_or_b32 s6, s4, 1
818 ; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
819 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
820 ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
821 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2
822 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0|
823 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], exec
824 ; GCN-IR-NEXT: s_cselect_b32 s4, s6, 0
825 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v2
826 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 25
827 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
828 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
829 ; GCN-IR-NEXT: s_endpgm
830 %1 = ashr i64 %x, 39
831 %2 = ashr i64 %y, 39
832 %result = sdiv i64 %1, %2
833 store i64 %result, ptr addrspace(1) %out
834 ret void
835 }
837 define amdgpu_kernel void @s_test_sdiv24_v2i64(ptr addrspace(1) %out, <2 x i64> %x, <2 x i64> %y) {
838 ; GCN-LABEL: s_test_sdiv24_v2i64:
839 ; GCN: ; %bb.0:
840 ; GCN-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
841 ; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
842 ; GCN-NEXT: s_mov_b32 s3, 0xf000
843 ; GCN-NEXT: s_mov_b32 s2, -1
844 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
845 ; GCN-NEXT: s_ashr_i64 s[8:9], s[8:9], 40
846 ; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8
847 ; GCN-NEXT: s_ashr_i64 s[4:5], s[4:5], 40
848 ; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4
849 ; GCN-NEXT: s_xor_b32 s4, s4, s8
850 ; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
851 ; GCN-NEXT: s_ashr_i64 s[6:7], s[6:7], 40
852 ; GCN-NEXT: s_ashr_i32 s4, s4, 30
853 ; GCN-NEXT: s_ashr_i64 s[10:11], s[10:11], 40
854 ; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
855 ; GCN-NEXT: v_trunc_f32_e32 v2, v2
856 ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
857 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
858 ; GCN-NEXT: s_or_b32 s7, s4, 1
859 ; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0|
860 ; GCN-NEXT: s_and_b64 s[4:5], s[4:5], exec
861 ; GCN-NEXT: s_cselect_b32 s4, s7, 0
862 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v2
863 ; GCN-NEXT: v_cvt_f32_i32_e32 v2, s10
864 ; GCN-NEXT: v_cvt_f32_i32_e32 v3, s6
865 ; GCN-NEXT: s_xor_b32 s4, s6, s10
866 ; GCN-NEXT: s_ashr_i32 s4, s4, 30
867 ; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2
868 ; GCN-NEXT: s_or_b32 s6, s4, 1
869 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
870 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
871 ; GCN-NEXT: v_mul_f32_e32 v4, v3, v4
872 ; GCN-NEXT: v_trunc_f32_e32 v4, v4
873 ; GCN-NEXT: v_mad_f32 v3, -v4, v2, v3
874 ; GCN-NEXT: v_cvt_i32_f32_e32 v4, v4
875 ; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v3|, |v2|
876 ; GCN-NEXT: s_and_b64 s[4:5], s[4:5], exec
877 ; GCN-NEXT: s_cselect_b32 s4, s6, 0
878 ; GCN-NEXT: v_add_i32_e32 v2, vcc, s4, v4
879 ; GCN-NEXT: v_bfe_i32 v2, v2, 0, 24
880 ; GCN-NEXT: v_ashrrev_i32_e32 v3, 31, v2
881 ; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
882 ; GCN-NEXT: s_endpgm
883 ;
884 ; GCN-IR-LABEL: s_test_sdiv24_v2i64:
885 ; GCN-IR: ; %bb.0:
886 ; GCN-IR-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
887 ; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
888 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
889 ; GCN-IR-NEXT: s_mov_b32 s2, -1
890 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
891 ; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[8:9], 40
892 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8
893 ; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[4:5], 40
894 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s4
895 ; GCN-IR-NEXT: s_xor_b32 s4, s4, s8
896 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
897 ; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[6:7], 40
898 ; GCN-IR-NEXT: s_ashr_i32 s4, s4, 30
899 ; GCN-IR-NEXT: s_ashr_i64 s[10:11], s[10:11], 40
900 ; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
901 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
902 ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
903 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2
904 ; GCN-IR-NEXT: s_or_b32 s7, s4, 1
905 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0|
906 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], exec
907 ; GCN-IR-NEXT: s_cselect_b32 s4, s7, 0
908 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v2
909 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v2, s10
910 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v3, s6
911 ; GCN-IR-NEXT: s_xor_b32 s4, s6, s10
912 ; GCN-IR-NEXT: s_ashr_i32 s4, s4, 30
913 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v4, v2
914 ; GCN-IR-NEXT: s_or_b32 s6, s4, 1
915 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24
916 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
917 ; GCN-IR-NEXT: v_mul_f32_e32 v4, v3, v4
918 ; GCN-IR-NEXT: v_trunc_f32_e32 v4, v4
919 ; GCN-IR-NEXT: v_mad_f32 v3, -v4, v2, v3
920 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v4, v4
921 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[4:5], |v3|, |v2|
922 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], exec
923 ; GCN-IR-NEXT: s_cselect_b32 s4, s6, 0
924 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, s4, v4
925 ; GCN-IR-NEXT: v_bfe_i32 v2, v2, 0, 24
926 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v3, 31, v2
927 ; GCN-IR-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
928 ; GCN-IR-NEXT: s_endpgm
929 %1 = ashr <2 x i64> %x, <i64 40, i64 40>
930 %2 = ashr <2 x i64> %y, <i64 40, i64 40>
931 %result = sdiv <2 x i64> %1, %2
932 store <2 x i64> %result, ptr addrspace(1) %out
933 ret void
934 }
936 define amdgpu_kernel void @s_test_sdiv24_48(ptr addrspace(1) %out, i48 %x, i48 %y) {
937 ; GCN-LABEL: s_test_sdiv24_48:
938 ; GCN: ; %bb.0:
939 ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
940 ; GCN-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
941 ; GCN-NEXT: s_mov_b32 s3, 0xf000
942 ; GCN-NEXT: s_mov_b32 s2, -1
943 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
944 ; GCN-NEXT: s_mov_b32 s1, s5
945 ; GCN-NEXT: s_sext_i32_i16 s5, s9
946 ; GCN-NEXT: v_mov_b32_e32 v0, s8
947 ; GCN-NEXT: v_alignbit_b32 v0, s5, v0, 24
948 ; GCN-NEXT: v_cvt_f32_i32_e32 v1, v0
949 ; GCN-NEXT: s_mov_b32 s0, s4
950 ; GCN-NEXT: s_sext_i32_i16 s4, s7
951 ; GCN-NEXT: v_mov_b32_e32 v2, s6
952 ; GCN-NEXT: v_alignbit_b32 v2, s4, v2, 24
953 ; GCN-NEXT: v_cvt_f32_i32_e32 v3, v2
954 ; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v1
955 ; GCN-NEXT: v_xor_b32_e32 v0, v2, v0
956 ; GCN-NEXT: v_ashrrev_i32_e32 v0, 30, v0
957 ; GCN-NEXT: v_or_b32_e32 v0, 1, v0
958 ; GCN-NEXT: v_mul_f32_e32 v2, v3, v4
959 ; GCN-NEXT: v_trunc_f32_e32 v2, v2
960 ; GCN-NEXT: v_mad_f32 v3, -v2, v1, v3
961 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
962 ; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1|
963 ; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
964 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
965 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
966 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
967 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
968 ; GCN-NEXT: buffer_store_short v1, off, s[0:3], 0 offset:4
969 ; GCN-NEXT: s_endpgm
970 ;
971 ; GCN-IR-LABEL: s_test_sdiv24_48:
972 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
973 ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
974 ; GCN-IR-NEXT: s_mov_b32 s15, 0
975 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
976 ; GCN-IR-NEXT: s_sext_i32_i16 s5, s5
977 ; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[4:5], 24
978 ; GCN-IR-NEXT: s_sext_i32_i16 s7, s7
979 ; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[2:3], 16
980 ; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 24
981 ; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[2:3], 16
982 ; GCN-IR-NEXT: s_ashr_i32 s2, s3, 31
983 ; GCN-IR-NEXT: s_lshl_b64 s[4:5], s[4:5], 16
984 ; GCN-IR-NEXT: s_mov_b32 s3, s2
985 ; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[4:5], 16
986 ; GCN-IR-NEXT: s_ashr_i32 s4, s5, 31
987 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[2:3], s[6:7]
988 ; GCN-IR-NEXT: s_mov_b32 s5, s4
989 ; GCN-IR-NEXT: s_sub_u32 s12, s6, s2
990 ; GCN-IR-NEXT: s_subb_u32 s13, s7, s2
991 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], s[8:9]
992 ; GCN-IR-NEXT: s_sub_u32 s6, s6, s4
993 ; GCN-IR-NEXT: s_subb_u32 s7, s7, s4
994 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0
995 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[12:13], 0
996 ; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[10:11]
997 ; GCN-IR-NEXT: s_flbit_i32_b32 s8, s6
998 ; GCN-IR-NEXT: s_add_i32 s8, s8, 32
999 ; GCN-IR-NEXT: s_flbit_i32_b32 s9, s7
1000 ; GCN-IR-NEXT: s_min_u32 s14, s8, s9
1001 ; GCN-IR-NEXT: s_flbit_i32_b32 s8, s12
1002 ; GCN-IR-NEXT: s_add_i32 s8, s8, 32
1003 ; GCN-IR-NEXT: s_flbit_i32_b32 s9, s13
1004 ; GCN-IR-NEXT: s_min_u32 s18, s8, s9
1005 ; GCN-IR-NEXT: s_sub_u32 s16, s14, s18
1006 ; GCN-IR-NEXT: s_subb_u32 s17, 0, 0
1007 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[20:21], s[16:17], 63
1008 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[22:23], s[16:17], 63
1009 ; GCN-IR-NEXT: s_or_b64 s[20:21], s[10:11], s[20:21]
1010 ; GCN-IR-NEXT: s_and_b64 s[10:11], s[20:21], exec
1011 ; GCN-IR-NEXT: s_cselect_b32 s11, 0, s13
1012 ; GCN-IR-NEXT: s_cselect_b32 s10, 0, s12
1013 ; GCN-IR-NEXT: s_or_b64 s[20:21], s[20:21], s[22:23]
1014 ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
1015 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[20:21]
1016 ; GCN-IR-NEXT: s_cbranch_vccz .LBB9_5
1017 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
1018 ; GCN-IR-NEXT: s_add_u32 s20, s16, 1
1019 ; GCN-IR-NEXT: s_addc_u32 s21, s17, 0
1020 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[20:21], 0
1021 ; GCN-IR-NEXT: s_sub_i32 s16, 63, s16
1022 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11]
1023 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[12:13], s16
1024 ; GCN-IR-NEXT: s_cbranch_vccz .LBB9_4
1025 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
1026 ; GCN-IR-NEXT: s_lshr_b64 s[16:17], s[12:13], s20
1027 ; GCN-IR-NEXT: s_add_u32 s19, s6, -1
1028 ; GCN-IR-NEXT: s_addc_u32 s20, s7, -1
1029 ; GCN-IR-NEXT: s_not_b64 s[8:9], s[14:15]
1030 ; GCN-IR-NEXT: s_add_u32 s12, s8, s18
1031 ; GCN-IR-NEXT: s_addc_u32 s13, s9, 0
1032 ; GCN-IR-NEXT: s_mov_b64 s[14:15], 0
1033 ; GCN-IR-NEXT: s_mov_b32 s9, 0
1034 ; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while
1035 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
1036 ; GCN-IR-NEXT: s_lshl_b64 s[16:17], s[16:17], 1
1037 ; GCN-IR-NEXT: s_lshr_b32 s8, s11, 31
1038 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
1039 ; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[8:9]
1040 ; GCN-IR-NEXT: s_or_b64 s[10:11], s[14:15], s[10:11]
1041 ; GCN-IR-NEXT: s_sub_u32 s8, s19, s16
1042 ; GCN-IR-NEXT: s_subb_u32 s8, s20, s17
1043 ; GCN-IR-NEXT: s_ashr_i32 s14, s8, 31
1044 ; GCN-IR-NEXT: s_mov_b32 s15, s14
1045 ; GCN-IR-NEXT: s_and_b32 s8, s14, 1
1046 ; GCN-IR-NEXT: s_and_b64 s[14:15], s[14:15], s[6:7]
1047 ; GCN-IR-NEXT: s_sub_u32 s16, s16, s14
1048 ; GCN-IR-NEXT: s_subb_u32 s17, s17, s15
1049 ; GCN-IR-NEXT: s_add_u32 s12, s12, 1
1050 ; GCN-IR-NEXT: s_addc_u32 s13, s13, 0
1051 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[22:23], s[12:13], 0
1052 ; GCN-IR-NEXT: s_mov_b64 s[14:15], s[8:9]
1053 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[22:23]
1054 ; GCN-IR-NEXT: s_cbranch_vccz .LBB9_3
1055 ; GCN-IR-NEXT: .LBB9_4: ; %Flow4
1056 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[10:11], 1
1057 ; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[6:7]
1058 ; GCN-IR-NEXT: .LBB9_5: ; %udiv-end
1059 ; GCN-IR-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x9
1060 ; GCN-IR-NEXT: s_xor_b64 s[0:1], s[4:5], s[2:3]
1061 ; GCN-IR-NEXT: s_xor_b64 s[2:3], s[10:11], s[0:1]
1062 ; GCN-IR-NEXT: s_sub_u32 s0, s2, s0
1063 ; GCN-IR-NEXT: s_subb_u32 s1, s3, s1
1064 ; GCN-IR-NEXT: s_mov_b32 s15, 0xf000
1065 ; GCN-IR-NEXT: s_mov_b32 s14, -1
1066 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s1
1067 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
1068 ; GCN-IR-NEXT: buffer_store_short v0, off, s[12:15], 0 offset:4
1069 ; GCN-IR-NEXT: s_waitcnt expcnt(0)
1070 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s0
1071 ; GCN-IR-NEXT: buffer_store_dword v0, off, s[12:15], 0
1072 ; GCN-IR-NEXT: s_endpgm
1073 %1 = ashr i48 %x, 24
1074 %2 = ashr i48 %y, 24
1075 %result = sdiv i48 %1, %2
1076 store i48 %result, ptr addrspace(1) %out
1077 ret void
1078 }
1080 define amdgpu_kernel void @s_test_sdiv_k_num_i64(ptr addrspace(1) %out, i64 %x) {
1081 ; GCN-LABEL: s_test_sdiv_k_num_i64:
1082 ; GCN: ; %bb.0:
1083 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
1084 ; GCN-NEXT: s_mov_b32 s7, 0xf000
1085 ; GCN-NEXT: s_mov_b32 s6, -1
1086 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
1087 ; GCN-NEXT: s_ashr_i32 s8, s3, 31
1088 ; GCN-NEXT: s_add_u32 s2, s2, s8
1089 ; GCN-NEXT: s_mov_b32 s9, s8
1090 ; GCN-NEXT: s_addc_u32 s3, s3, s8
1091 ; GCN-NEXT: s_xor_b64 s[2:3], s[2:3], s[8:9]
1092 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2
1093 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, s3
1094 ; GCN-NEXT: s_sub_u32 s4, 0, s2
1095 ; GCN-NEXT: s_subb_u32 s5, 0, s3
1096 ; GCN-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0
1097 ; GCN-NEXT: v_rcp_f32_e32 v0, v0
1098 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
1099 ; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
1100 ; GCN-NEXT: v_trunc_f32_e32 v1, v1
1101 ; GCN-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
1102 ; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
1103 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
1104 ; GCN-NEXT: v_mul_lo_u32 v2, s4, v1
1105 ; GCN-NEXT: v_mul_hi_u32 v3, s4, v0
1106 ; GCN-NEXT: v_mul_lo_u32 v5, s5, v0
1107 ; GCN-NEXT: v_mul_lo_u32 v4, s4, v0
1108 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
1109 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5
1110 ; GCN-NEXT: v_mul_hi_u32 v3, v0, v4
1111 ; GCN-NEXT: v_mul_lo_u32 v5, v0, v2
1112 ; GCN-NEXT: v_mul_hi_u32 v7, v0, v2
1113 ; GCN-NEXT: v_mul_hi_u32 v6, v1, v4
1114 ; GCN-NEXT: v_mul_lo_u32 v4, v1, v4
1115 ; GCN-NEXT: v_mul_hi_u32 v8, v1, v2
1116 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
1117 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc
1118 ; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
1119 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v4
1120 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v6, vcc
1121 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v8, vcc
1122 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
1123 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
1124 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
1125 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
1126 ; GCN-NEXT: v_mul_lo_u32 v2, s4, v1
1127 ; GCN-NEXT: v_mul_hi_u32 v3, s4, v0
1128 ; GCN-NEXT: v_mul_lo_u32 v4, s5, v0
1129 ; GCN-NEXT: s_mov_b32 s5, s1
1130 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
1131 ; GCN-NEXT: v_mul_lo_u32 v3, s4, v0
1132 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
1133 ; GCN-NEXT: v_mul_lo_u32 v6, v0, v2
1134 ; GCN-NEXT: v_mul_hi_u32 v7, v0, v3
1135 ; GCN-NEXT: v_mul_hi_u32 v8, v0, v2
1136 ; GCN-NEXT: v_mul_hi_u32 v5, v1, v3
1137 ; GCN-NEXT: v_mul_lo_u32 v3, v1, v3
1138 ; GCN-NEXT: v_mul_hi_u32 v4, v1, v2
1139 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
1140 ; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc
1141 ; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
1142 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3
1143 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v7, v5, vcc
1144 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
1145 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
1146 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
1147 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
1148 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
1149 ; GCN-NEXT: v_mul_lo_u32 v2, v1, 24
1150 ; GCN-NEXT: v_mul_hi_u32 v0, v0, 24
1151 ; GCN-NEXT: v_mul_hi_u32 v1, v1, 24
1152 ; GCN-NEXT: v_mov_b32_e32 v4, s3
1153 ; GCN-NEXT: s_mov_b32 s4, s0
1154 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
1155 ; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v1, vcc
1156 ; GCN-NEXT: v_mul_lo_u32 v1, s3, v0
1157 ; GCN-NEXT: v_mul_hi_u32 v2, s2, v0
1158 ; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v2
1159 ; GCN-NEXT: v_mul_lo_u32 v2, s2, v0
1160 ; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
1161 ; GCN-NEXT: v_sub_i32_e32 v2, vcc, 24, v2
1162 ; GCN-NEXT: v_subb_u32_e64 v3, s[0:1], v3, v4, vcc
1163 ; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s2, v2
1164 ; GCN-NEXT: v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1]
1165 ; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v3
1166 ; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
1167 ; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v4
1168 ; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1]
1169 ; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v3
1170 ; GCN-NEXT: v_cndmask_b32_e64 v3, v5, v4, s[0:1]
1171 ; GCN-NEXT: v_add_i32_e64 v4, s[0:1], 1, v0
1172 ; GCN-NEXT: v_addc_u32_e64 v5, s[0:1], 0, 0, s[0:1]
1173 ; GCN-NEXT: v_add_i32_e64 v6, s[0:1], 2, v0
1174 ; GCN-NEXT: v_addc_u32_e64 v7, s[0:1], 0, 0, s[0:1]
1175 ; GCN-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
1176 ; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v3
1177 ; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
1178 ; GCN-NEXT: v_cndmask_b32_e64 v3, v4, v6, s[0:1]
1179 ; GCN-NEXT: v_cndmask_b32_e64 v4, v5, v7, s[0:1]
1180 ; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
1181 ; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v2
1182 ; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc
1183 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1
1184 ; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc
1185 ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
1186 ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
1187 ; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc
1188 ; GCN-NEXT: v_xor_b32_e32 v0, s8, v0
1189 ; GCN-NEXT: v_xor_b32_e32 v1, s8, v1
1190 ; GCN-NEXT: v_mov_b32_e32 v2, s8
1191 ; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0
1192 ; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
1193 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1194 ; GCN-NEXT: s_endpgm
1195 ;
1196 ; GCN-IR-LABEL: s_test_sdiv_k_num_i64:
1197 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
1198 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
1199 ; GCN-IR-NEXT: s_mov_b64 s[6:7], 0
1200 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
1201 ; GCN-IR-NEXT: s_ashr_i32 s4, s3, 31
1202 ; GCN-IR-NEXT: s_mov_b32 s5, s4
1203 ; GCN-IR-NEXT: s_xor_b64 s[2:3], s[4:5], s[2:3]
1204 ; GCN-IR-NEXT: s_sub_u32 s2, s2, s4
1205 ; GCN-IR-NEXT: s_subb_u32 s3, s3, s4
1206 ; GCN-IR-NEXT: s_flbit_i32_b32 s10, s2
1207 ; GCN-IR-NEXT: s_add_i32 s10, s10, 32
1208 ; GCN-IR-NEXT: s_flbit_i32_b32 s11, s3
1209 ; GCN-IR-NEXT: s_min_u32 s10, s10, s11
1210 ; GCN-IR-NEXT: s_add_u32 s12, s10, 0xffffffc5
1211 ; GCN-IR-NEXT: s_addc_u32 s13, 0, -1
1212 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[2:3], 0
1213 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[14:15], s[12:13], 63
1214 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[16:17], s[12:13], 63
1215 ; GCN-IR-NEXT: s_or_b64 s[14:15], s[8:9], s[14:15]
1216 ; GCN-IR-NEXT: s_and_b64 s[8:9], s[14:15], exec
1217 ; GCN-IR-NEXT: s_cselect_b32 s8, 0, 24
1218 ; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17]
1219 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[14:15]
1220 ; GCN-IR-NEXT: s_mov_b32 s9, 0
1221 ; GCN-IR-NEXT: s_cbranch_vccz .LBB10_5
1222 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
1223 ; GCN-IR-NEXT: s_add_u32 s14, s12, 1
1224 ; GCN-IR-NEXT: s_addc_u32 s15, s13, 0
1225 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[14:15], 0
1226 ; GCN-IR-NEXT: s_sub_i32 s11, 63, s12
1227 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[8:9]
1228 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], 24, s11
1229 ; GCN-IR-NEXT: s_cbranch_vccz .LBB10_4
1230 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
1231 ; GCN-IR-NEXT: s_lshr_b64 s[12:13], 24, s14
1232 ; GCN-IR-NEXT: s_add_u32 s16, s2, -1
1233 ; GCN-IR-NEXT: s_addc_u32 s17, s3, -1
1234 ; GCN-IR-NEXT: s_sub_u32 s10, 58, s10
1235 ; GCN-IR-NEXT: s_subb_u32 s11, 0, 0
1236 ; GCN-IR-NEXT: s_mov_b64 s[14:15], 0
1237 ; GCN-IR-NEXT: s_mov_b32 s7, 0
1238 ; GCN-IR-NEXT: .LBB10_3: ; %udiv-do-while
1239 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
1240 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1
1241 ; GCN-IR-NEXT: s_lshr_b32 s6, s9, 31
1242 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
1243 ; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[6:7]
1244 ; GCN-IR-NEXT: s_or_b64 s[8:9], s[14:15], s[8:9]
1245 ; GCN-IR-NEXT: s_sub_u32 s6, s16, s12
1246 ; GCN-IR-NEXT: s_subb_u32 s6, s17, s13
1247 ; GCN-IR-NEXT: s_ashr_i32 s14, s6, 31
1248 ; GCN-IR-NEXT: s_mov_b32 s15, s14
1249 ; GCN-IR-NEXT: s_and_b32 s6, s14, 1
1250 ; GCN-IR-NEXT: s_and_b64 s[14:15], s[14:15], s[2:3]
1251 ; GCN-IR-NEXT: s_sub_u32 s12, s12, s14
1252 ; GCN-IR-NEXT: s_subb_u32 s13, s13, s15
1253 ; GCN-IR-NEXT: s_add_u32 s10, s10, 1
1254 ; GCN-IR-NEXT: s_addc_u32 s11, s11, 0
1255 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[10:11], 0
1256 ; GCN-IR-NEXT: s_mov_b64 s[14:15], s[6:7]
1257 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[18:19]
1258 ; GCN-IR-NEXT: s_cbranch_vccz .LBB10_3
1259 ; GCN-IR-NEXT: .LBB10_4: ; %Flow6
1260 ; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[8:9], 1
1261 ; GCN-IR-NEXT: s_or_b64 s[8:9], s[6:7], s[2:3]
1262 ; GCN-IR-NEXT: .LBB10_5: ; %udiv-end
1263 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[8:9], s[4:5]
1264 ; GCN-IR-NEXT: s_sub_u32 s4, s6, s4
1265 ; GCN-IR-NEXT: s_subb_u32 s5, s7, s5
1266 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s4
1267 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
1268 ; GCN-IR-NEXT: s_mov_b32 s2, -1
1269 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s5
1270 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1271 ; GCN-IR-NEXT: s_endpgm
1272 %result = sdiv i64 24, %x
1273 store i64 %result, ptr addrspace(1) %out
1274 ret void
1275 }
1277 define i64 @v_test_sdiv_k_num_i64(i64 %x) {
1278 ; GCN-LABEL: v_test_sdiv_k_num_i64:
1279 ; GCN: ; %bb.0:
1280 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1281 ; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v1
1282 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
1283 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
1284 ; GCN-NEXT: v_xor_b32_e32 v1, v1, v2
1285 ; GCN-NEXT: v_xor_b32_e32 v0, v0, v2
1286 ; GCN-NEXT: v_cvt_f32_u32_e32 v3, v0
1287 ; GCN-NEXT: v_cvt_f32_u32_e32 v4, v1
1288 ; GCN-NEXT: v_sub_i32_e32 v5, vcc, 0, v0
1289 ; GCN-NEXT: v_subb_u32_e32 v6, vcc, 0, v1, vcc
1290 ; GCN-NEXT: v_madmk_f32 v3, v4, 0x4f800000, v3
1291 ; GCN-NEXT: v_rcp_f32_e32 v3, v3
1292 ; GCN-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v3
1293 ; GCN-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3
1294 ; GCN-NEXT: v_trunc_f32_e32 v4, v4
1295 ; GCN-NEXT: v_madmk_f32 v3, v4, 0xcf800000, v3
1296 ; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
1297 ; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4
1298 ; GCN-NEXT: v_mul_hi_u32 v7, v5, v3
1299 ; GCN-NEXT: v_mul_lo_u32 v8, v5, v4
1300 ; GCN-NEXT: v_mul_lo_u32 v9, v6, v3
1301 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8
1302 ; GCN-NEXT: v_mul_lo_u32 v8, v5, v3
1303 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v9
1304 ; GCN-NEXT: v_mul_lo_u32 v9, v3, v7
1305 ; GCN-NEXT: v_mul_hi_u32 v10, v3, v8
1306 ; GCN-NEXT: v_mul_hi_u32 v11, v3, v7
1307 ; GCN-NEXT: v_mul_hi_u32 v12, v4, v7
1308 ; GCN-NEXT: v_mul_lo_u32 v7, v4, v7
1309 ; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9
1310 ; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v11, vcc
1311 ; GCN-NEXT: v_mul_lo_u32 v11, v4, v8
1312 ; GCN-NEXT: v_mul_hi_u32 v8, v4, v8
1313 ; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v11
1314 ; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v8, vcc
1315 ; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v12, vcc
1316 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
1317 ; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc
1318 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7
1319 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v8, vcc
1320 ; GCN-NEXT: v_mul_lo_u32 v7, v5, v4
1321 ; GCN-NEXT: v_mul_hi_u32 v8, v5, v3
1322 ; GCN-NEXT: v_mul_lo_u32 v6, v6, v3
1323 ; GCN-NEXT: v_mul_lo_u32 v5, v5, v3
1324 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
1325 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
1326 ; GCN-NEXT: v_mul_lo_u32 v9, v3, v6
1327 ; GCN-NEXT: v_mul_hi_u32 v10, v3, v5
1328 ; GCN-NEXT: v_mul_hi_u32 v11, v3, v6
1329 ; GCN-NEXT: v_mul_hi_u32 v8, v4, v5
1330 ; GCN-NEXT: v_mul_lo_u32 v5, v4, v5
1331 ; GCN-NEXT: v_mul_hi_u32 v7, v4, v6
1332 ; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9
1333 ; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v11, vcc
1334 ; GCN-NEXT: v_mul_lo_u32 v6, v4, v6
1335 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v9, v5
1336 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v8, vcc
1337 ; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
1338 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6
1339 ; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v7, vcc
1340 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
1341 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v6, vcc
1342 ; GCN-NEXT: v_mul_lo_u32 v5, v4, 24
1343 ; GCN-NEXT: v_mul_hi_u32 v3, v3, 24
1344 ; GCN-NEXT: v_mul_hi_u32 v4, v4, 24
1345 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
1346 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
1347 ; GCN-NEXT: v_mul_lo_u32 v4, v1, v3
1348 ; GCN-NEXT: v_mul_hi_u32 v5, v0, v3
1349 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
1350 ; GCN-NEXT: v_mul_lo_u32 v5, v0, v3
1351 ; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v4
1352 ; GCN-NEXT: v_sub_i32_e32 v5, vcc, 24, v5
1353 ; GCN-NEXT: v_subb_u32_e64 v6, s[4:5], v6, v1, vcc
1354 ; GCN-NEXT: v_sub_i32_e64 v7, s[4:5], v5, v0
1355 ; GCN-NEXT: v_subbrev_u32_e64 v6, s[4:5], 0, v6, s[4:5]
1356 ; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v1
1357 ; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5]
1358 ; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v0
1359 ; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
1360 ; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v6, v1
1361 ; GCN-NEXT: v_cndmask_b32_e64 v6, v8, v7, s[4:5]
1362 ; GCN-NEXT: v_add_i32_e64 v7, s[4:5], 2, v3
1363 ; GCN-NEXT: v_addc_u32_e64 v8, s[4:5], 0, 0, s[4:5]
1364 ; GCN-NEXT: v_add_i32_e64 v9, s[4:5], 1, v3
1365 ; GCN-NEXT: v_addc_u32_e64 v10, s[4:5], 0, 0, s[4:5]
1366 ; GCN-NEXT: v_subb_u32_e32 v4, vcc, 0, v4, vcc
1367 ; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v6
1368 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v4, v1
1369 ; GCN-NEXT: v_cndmask_b32_e64 v6, v10, v8, s[4:5]
1370 ; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
1371 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v5, v0
1372 ; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
1373 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v4, v1
1374 ; GCN-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
1375 ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
1376 ; GCN-NEXT: v_cndmask_b32_e64 v1, v9, v7, s[4:5]
1377 ; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
1378 ; GCN-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
1379 ; GCN-NEXT: v_xor_b32_e32 v3, v0, v2
1380 ; GCN-NEXT: v_xor_b32_e32 v0, v1, v2
1381 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
1382 ; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v2, vcc
1383 ; GCN-NEXT: s_setpc_b64 s[30:31]
1384 ;
1385 ; GCN-IR-LABEL: v_test_sdiv_k_num_i64:
1386 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
1387 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1388 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v2, 31, v1
1389 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v2, v0
1390 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v2, v1
1391 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
1392 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
1393 ; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v0
1394 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 32, v4
1395 ; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1
1396 ; GCN-IR-NEXT: v_min_u32_e32 v8, v4, v5
1397 ; GCN-IR-NEXT: s_movk_i32 s6, 0xffc5
1398 ; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, s6, v8
1399 ; GCN-IR-NEXT: v_addc_u32_e64 v6, s[6:7], 0, -1, vcc
1400 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1401 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[5:6]
1402 ; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[6:7], 63, v[5:6]
1403 ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
1404 ; GCN-IR-NEXT: v_cndmask_b32_e64 v7, 24, 0, s[4:5]
1405 ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
1406 ; GCN-IR-NEXT: v_mov_b32_e32 v3, v2
1407 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
1408 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7]
1409 ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
1410 ; GCN-IR-NEXT: s_cbranch_execz .LBB11_6
1411 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
1412 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v5
1413 ; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v6, vcc
1414 ; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v5
1415 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[9:10]
1416 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], 24, v4
1417 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
1418 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
1419 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
1420 ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
1421 ; GCN-IR-NEXT: s_cbranch_execz .LBB11_5
1422 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
1423 ; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, -1, v0
1424 ; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, -1, v1, vcc
1425 ; GCN-IR-NEXT: v_lshr_b64 v[10:11], 24, v9
1426 ; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, 58, v8
1427 ; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
1428 ; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], 0, 0, vcc
1429 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
1430 ; GCN-IR-NEXT: v_mov_b32_e32 v13, 0
1431 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
1432 ; GCN-IR-NEXT: .LBB11_3: ; %udiv-do-while
1433 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
1434 ; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
1435 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5
1436 ; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6
1437 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
1438 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v14, v10
1439 ; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v15, v11, vcc
1440 ; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4
1441 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6
1442 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v8
1443 ; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5
1444 ; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12
1445 ; GCN-IR-NEXT: v_and_b32_e32 v13, v12, v1
1446 ; GCN-IR-NEXT: v_and_b32_e32 v12, v12, v0
1447 ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
1448 ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9]
1449 ; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v12
1450 ; GCN-IR-NEXT: v_subb_u32_e64 v11, s[4:5], v11, v13, s[4:5]
1451 ; GCN-IR-NEXT: v_mov_b32_e32 v13, v7
1452 ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
1453 ; GCN-IR-NEXT: v_mov_b32_e32 v12, v6
1454 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
1455 ; GCN-IR-NEXT: s_cbranch_execnz .LBB11_3
1456 ; GCN-IR-NEXT: ; %bb.4: ; %Flow
1457 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
1458 ; GCN-IR-NEXT: .LBB11_5: ; %Flow4
1459 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
1460 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[4:5], 1
1461 ; GCN-IR-NEXT: v_or_b32_e32 v4, v7, v1
1462 ; GCN-IR-NEXT: v_or_b32_e32 v7, v6, v0
1463 ; GCN-IR-NEXT: .LBB11_6: ; %Flow5
1464 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
1465 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v7, v2
1466 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v4, v3
1467 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
1468 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
1469 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
1470 %result = sdiv i64 24, %x
1471 ret i64 %result
1472 }
1474 define i64 @v_test_sdiv_pow2_k_num_i64(i64 %x) {
1475 ; GCN-LABEL: v_test_sdiv_pow2_k_num_i64:
1476 ; GCN: ; %bb.0:
1477 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1478 ; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v1
1479 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
1480 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
1481 ; GCN-NEXT: v_xor_b32_e32 v1, v1, v2
1482 ; GCN-NEXT: v_xor_b32_e32 v0, v0, v2
1483 ; GCN-NEXT: v_cvt_f32_u32_e32 v3, v0
1484 ; GCN-NEXT: v_cvt_f32_u32_e32 v4, v1
1485 ; GCN-NEXT: v_sub_i32_e32 v5, vcc, 0, v0
1486 ; GCN-NEXT: v_subb_u32_e32 v6, vcc, 0, v1, vcc
1487 ; GCN-NEXT: v_madmk_f32 v3, v4, 0x4f800000, v3
1488 ; GCN-NEXT: v_rcp_f32_e32 v3, v3
1489 ; GCN-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v3
1490 ; GCN-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3
1491 ; GCN-NEXT: v_trunc_f32_e32 v4, v4
1492 ; GCN-NEXT: v_madmk_f32 v3, v4, 0xcf800000, v3
1493 ; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
1494 ; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4
1495 ; GCN-NEXT: v_mul_hi_u32 v7, v5, v3
1496 ; GCN-NEXT: v_mul_lo_u32 v8, v5, v4
1497 ; GCN-NEXT: v_mul_lo_u32 v9, v6, v3
1498 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8
1499 ; GCN-NEXT: v_mul_lo_u32 v8, v5, v3
1500 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v9
1501 ; GCN-NEXT: v_mul_lo_u32 v9, v3, v7
1502 ; GCN-NEXT: v_mul_hi_u32 v10, v3, v8
1503 ; GCN-NEXT: v_mul_hi_u32 v11, v3, v7
1504 ; GCN-NEXT: v_mul_hi_u32 v12, v4, v7
1505 ; GCN-NEXT: v_mul_lo_u32 v7, v4, v7
1506 ; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9
1507 ; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v11, vcc
1508 ; GCN-NEXT: v_mul_lo_u32 v11, v4, v8
1509 ; GCN-NEXT: v_mul_hi_u32 v8, v4, v8
1510 ; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v11
1511 ; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v8, vcc
1512 ; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v12, vcc
1513 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
1514 ; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc
1515 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7
1516 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v8, vcc
1517 ; GCN-NEXT: v_mul_lo_u32 v7, v5, v4
1518 ; GCN-NEXT: v_mul_hi_u32 v8, v5, v3
1519 ; GCN-NEXT: v_mul_lo_u32 v6, v6, v3
1520 ; GCN-NEXT: v_mul_lo_u32 v5, v5, v3
1521 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
1522 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
1523 ; GCN-NEXT: v_mul_lo_u32 v9, v3, v6
1524 ; GCN-NEXT: v_mul_hi_u32 v10, v3, v5
1525 ; GCN-NEXT: v_mul_hi_u32 v11, v3, v6
1526 ; GCN-NEXT: v_mul_hi_u32 v8, v4, v5
1527 ; GCN-NEXT: v_mul_lo_u32 v5, v4, v5
1528 ; GCN-NEXT: v_mul_hi_u32 v7, v4, v6
1529 ; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9
1530 ; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v11, vcc
1531 ; GCN-NEXT: v_mul_lo_u32 v6, v4, v6
1532 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v9, v5
1533 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v8, vcc
1534 ; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
1535 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6
1536 ; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v7, vcc
1537 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
1538 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v4, v6, vcc
1539 ; GCN-NEXT: v_lshrrev_b32_e32 v3, 17, v3
1540 ; GCN-NEXT: v_mul_lo_u32 v4, v1, v3
1541 ; GCN-NEXT: v_mul_hi_u32 v5, v0, v3
1542 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
1543 ; GCN-NEXT: v_mul_lo_u32 v5, v0, v3
1544 ; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v4
1545 ; GCN-NEXT: v_sub_i32_e32 v5, vcc, 0x8000, v5
1546 ; GCN-NEXT: v_subb_u32_e64 v6, s[4:5], v6, v1, vcc
1547 ; GCN-NEXT: v_sub_i32_e64 v7, s[4:5], v5, v0
1548 ; GCN-NEXT: v_subbrev_u32_e64 v6, s[4:5], 0, v6, s[4:5]
1549 ; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v1
1550 ; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5]
1551 ; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v0
1552 ; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
1553 ; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v6, v1
1554 ; GCN-NEXT: v_cndmask_b32_e64 v6, v8, v7, s[4:5]
1555 ; GCN-NEXT: v_add_i32_e64 v7, s[4:5], 2, v3
1556 ; GCN-NEXT: v_addc_u32_e64 v8, s[4:5], 0, 0, s[4:5]
1557 ; GCN-NEXT: v_add_i32_e64 v9, s[4:5], 1, v3
1558 ; GCN-NEXT: v_addc_u32_e64 v10, s[4:5], 0, 0, s[4:5]
1559 ; GCN-NEXT: v_subb_u32_e32 v4, vcc, 0, v4, vcc
1560 ; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v6
1561 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v4, v1
1562 ; GCN-NEXT: v_cndmask_b32_e64 v6, v10, v8, s[4:5]
1563 ; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
1564 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v5, v0
1565 ; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
1566 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v4, v1
1567 ; GCN-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc
1568 ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
1569 ; GCN-NEXT: v_cndmask_b32_e64 v1, v9, v7, s[4:5]
1570 ; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
1571 ; GCN-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
1572 ; GCN-NEXT: v_xor_b32_e32 v3, v0, v2
1573 ; GCN-NEXT: v_xor_b32_e32 v0, v1, v2
1574 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
1575 ; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v2, vcc
1576 ; GCN-NEXT: s_setpc_b64 s[30:31]
1577 ;
1578 ; GCN-IR-LABEL: v_test_sdiv_pow2_k_num_i64:
1579 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
1580 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1581 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v2, 31, v1
1582 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v2, v0
1583 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v2, v1
1584 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
1585 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc
1586 ; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v0
1587 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 32, v4
1588 ; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1
1589 ; GCN-IR-NEXT: v_min_u32_e32 v8, v4, v5
1590 ; GCN-IR-NEXT: s_movk_i32 s6, 0xffd0
1591 ; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, s6, v8
1592 ; GCN-IR-NEXT: v_addc_u32_e64 v6, s[6:7], 0, -1, vcc
1593 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1594 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[5:6]
1595 ; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[6:7], 63, v[5:6]
1596 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0x8000
1597 ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
1598 ; GCN-IR-NEXT: v_cndmask_b32_e64 v7, v7, 0, s[4:5]
1599 ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
1600 ; GCN-IR-NEXT: v_mov_b32_e32 v3, v2
1601 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
1602 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7]
1603 ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
1604 ; GCN-IR-NEXT: s_cbranch_execz .LBB12_6
1605 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
1606 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v5
1607 ; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v5
1608 ; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v6, vcc
1609 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000
1610 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[9:10]
1611 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], s[4:5], v4
1612 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
1613 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
1614 ; GCN-IR-NEXT: s_and_saveexec_b64 s[8:9], vcc
1615 ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[8:9]
1616 ; GCN-IR-NEXT: s_cbranch_execz .LBB12_5
1617 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
1618 ; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, -1, v0
1619 ; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, -1, v1, vcc
1620 ; GCN-IR-NEXT: v_lshr_b64 v[10:11], s[4:5], v9
1621 ; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, 47, v8
1622 ; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
1623 ; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], 0, 0, vcc
1624 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
1625 ; GCN-IR-NEXT: v_mov_b32_e32 v13, 0
1626 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
1627 ; GCN-IR-NEXT: .LBB12_3: ; %udiv-do-while
1628 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
1629 ; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
1630 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5
1631 ; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6
1632 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
1633 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v14, v10
1634 ; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v15, v11, vcc
1635 ; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4
1636 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6
1637 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v8
1638 ; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5
1639 ; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12
1640 ; GCN-IR-NEXT: v_and_b32_e32 v13, v12, v1
1641 ; GCN-IR-NEXT: v_and_b32_e32 v12, v12, v0
1642 ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
1643 ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9]
1644 ; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v12
1645 ; GCN-IR-NEXT: v_subb_u32_e64 v11, s[4:5], v11, v13, s[4:5]
1646 ; GCN-IR-NEXT: v_mov_b32_e32 v13, v7
1647 ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
1648 ; GCN-IR-NEXT: v_mov_b32_e32 v12, v6
1649 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
1650 ; GCN-IR-NEXT: s_cbranch_execnz .LBB12_3
1651 ; GCN-IR-NEXT: ; %bb.4: ; %Flow
1652 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
1653 ; GCN-IR-NEXT: .LBB12_5: ; %Flow4
1654 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
1655 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[4:5], 1
1656 ; GCN-IR-NEXT: v_or_b32_e32 v4, v7, v1
1657 ; GCN-IR-NEXT: v_or_b32_e32 v7, v6, v0
1658 ; GCN-IR-NEXT: .LBB12_6: ; %Flow5
1659 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
1660 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v7, v2
1661 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v4, v3
1662 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
1663 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
1664 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
1665 %result = sdiv i64 32768, %x
1666 ret i64 %result
1667 }
1669 define i64 @v_test_sdiv_pow2_k_den_i64(i64 %x) {
1670 ; GCN-LABEL: v_test_sdiv_pow2_k_den_i64:
1671 ; GCN: ; %bb.0:
1672 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1673 ; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v1
1674 ; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v2
1675 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
1676 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
1677 ; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 15
1678 ; GCN-NEXT: s_setpc_b64 s[30:31]
1679 ;
1680 ; GCN-IR-LABEL: v_test_sdiv_pow2_k_den_i64:
1681 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
1682 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1683 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v2, 31, v1
1684 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v2, v0
1685 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v2, v1
1686 ; GCN-IR-NEXT: v_sub_i32_e32 v7, vcc, v0, v2
1687 ; GCN-IR-NEXT: v_subb_u32_e32 v8, vcc, v1, v2, vcc
1688 ; GCN-IR-NEXT: v_ffbh_u32_e32 v0, v7
1689 ; GCN-IR-NEXT: v_add_i32_e64 v0, s[4:5], 32, v0
1690 ; GCN-IR-NEXT: v_ffbh_u32_e32 v1, v8
1691 ; GCN-IR-NEXT: v_min_u32_e32 v0, v0, v1
1692 ; GCN-IR-NEXT: v_sub_i32_e64 v3, s[4:5], 48, v0
1693 ; GCN-IR-NEXT: v_subb_u32_e64 v4, s[4:5], 0, 0, s[4:5]
1694 ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[7:8]
1695 ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[3:4]
1696 ; GCN-IR-NEXT: v_mov_b32_e32 v1, v2
1697 ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
1698 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[3:4]
1699 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
1700 ; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v8, 0, s[4:5]
1701 ; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v7, 0, s[4:5]
1702 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
1703 ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
1704 ; GCN-IR-NEXT: s_cbranch_execz .LBB13_6
1705 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
1706 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v3
1707 ; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v4, vcc
1708 ; GCN-IR-NEXT: v_sub_i32_e64 v3, s[4:5], 63, v3
1709 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[9:10]
1710 ; GCN-IR-NEXT: v_lshl_b64 v[3:4], v[7:8], v3
1711 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
1712 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
1713 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
1714 ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
1715 ; GCN-IR-NEXT: s_cbranch_execz .LBB13_5
1716 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
1717 ; GCN-IR-NEXT: v_lshr_b64 v[9:10], v[7:8], v9
1718 ; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 0xffffffcf, v0
1719 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
1720 ; GCN-IR-NEXT: v_addc_u32_e64 v8, s[4:5], 0, -1, vcc
1721 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
1722 ; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
1723 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
1724 ; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff
1725 ; GCN-IR-NEXT: .LBB13_3: ; %udiv-do-while
1726 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
1727 ; GCN-IR-NEXT: v_lshl_b64 v[9:10], v[9:10], 1
1728 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 31, v4
1729 ; GCN-IR-NEXT: v_or_b32_e32 v0, v9, v0
1730 ; GCN-IR-NEXT: v_sub_i32_e32 v5, vcc, s12, v0
1731 ; GCN-IR-NEXT: v_subb_u32_e32 v5, vcc, 0, v10, vcc
1732 ; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v7
1733 ; GCN-IR-NEXT: v_lshl_b64 v[3:4], v[3:4], 1
1734 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v9, 31, v5
1735 ; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc
1736 ; GCN-IR-NEXT: v_and_b32_e32 v5, 1, v9
1737 ; GCN-IR-NEXT: v_and_b32_e32 v9, 0x8000, v9
1738 ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[7:8]
1739 ; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4
1740 ; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3
1741 ; GCN-IR-NEXT: v_sub_i32_e64 v9, s[4:5], v0, v9
1742 ; GCN-IR-NEXT: v_mov_b32_e32 v12, v6
1743 ; GCN-IR-NEXT: v_subbrev_u32_e64 v10, s[4:5], 0, v10, s[4:5]
1744 ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
1745 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v5
1746 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
1747 ; GCN-IR-NEXT: s_cbranch_execnz .LBB13_3
1748 ; GCN-IR-NEXT: ; %bb.4: ; %Flow
1749 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
1750 ; GCN-IR-NEXT: .LBB13_5: ; %Flow4
1751 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
1752 ; GCN-IR-NEXT: v_lshl_b64 v[3:4], v[3:4], 1
1753 ; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v4
1754 ; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3
1755 ; GCN-IR-NEXT: .LBB13_6: ; %Flow5
1756 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
1757 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v5, v2
1758 ; GCN-IR-NEXT: v_xor_b32_e32 v3, v6, v1
1759 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
1760 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc
1761 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
1762 %result = sdiv i64 %x, 32768
1763 ret i64 %result
1764 }
1766 define amdgpu_kernel void @s_test_sdiv24_k_num_i64(ptr addrspace(1) %out, i64 %x) {
1767 ; GCN-LABEL: s_test_sdiv24_k_num_i64:
1768 ; GCN: ; %bb.0:
1769 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
1770 ; GCN-NEXT: s_mov_b32 s7, 0xf000
1771 ; GCN-NEXT: s_mov_b32 s6, -1
1772 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
1773 ; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 40
1774 ; GCN-NEXT: v_cvt_f32_i32_e32 v0, s2
1775 ; GCN-NEXT: s_mov_b32 s3, 0x41c00000
1776 ; GCN-NEXT: s_mov_b32 s4, s0
1777 ; GCN-NEXT: s_ashr_i32 s0, s2, 30
1778 ; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0
1779 ; GCN-NEXT: s_mov_b32 s5, s1
1780 ; GCN-NEXT: s_or_b32 s2, s0, 1
1781 ; GCN-NEXT: v_mul_f32_e32 v1, 0x41c00000, v1
1782 ; GCN-NEXT: v_trunc_f32_e32 v1, v1
1783 ; GCN-NEXT: v_mad_f32 v2, -v1, v0, s3
1784 ; GCN-NEXT: v_cvt_i32_f32_e32 v1, v1
1785 ; GCN-NEXT: v_cmp_ge_f32_e64 s[0:1], |v2|, |v0|
1786 ; GCN-NEXT: s_and_b64 s[0:1], s[0:1], exec
1787 ; GCN-NEXT: s_cselect_b32 s0, s2, 0
1788 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v1
1789 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
1790 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
1791 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1792 ; GCN-NEXT: s_endpgm
1793 ;
1794 ; GCN-IR-LABEL: s_test_sdiv24_k_num_i64:
1795 ; GCN-IR: ; %bb.0:
1796 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
1797 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
1798 ; GCN-IR-NEXT: s_mov_b32 s6, -1
1799 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
1800 ; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 40
1801 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s2
1802 ; GCN-IR-NEXT: s_mov_b32 s3, 0x41c00000
1803 ; GCN-IR-NEXT: s_mov_b32 s4, s0
1804 ; GCN-IR-NEXT: s_ashr_i32 s0, s2, 30
1805 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0
1806 ; GCN-IR-NEXT: s_mov_b32 s5, s1
1807 ; GCN-IR-NEXT: s_or_b32 s2, s0, 1
1808 ; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x41c00000, v1
1809 ; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
1810 ; GCN-IR-NEXT: v_mad_f32 v2, -v1, v0, s3
1811 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v1, v1
1812 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[0:1], |v2|, |v0|
1813 ; GCN-IR-NEXT: s_and_b64 s[0:1], s[0:1], exec
1814 ; GCN-IR-NEXT: s_cselect_b32 s0, s2, 0
1815 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s0, v1
1816 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24
1817 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
1818 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1819 ; GCN-IR-NEXT: s_endpgm
1820 %x.shr = ashr i64 %x, 40
1821 %result = sdiv i64 24, %x.shr
1822 store i64 %result, ptr addrspace(1) %out
1823 ret void
1824 }
1826 define amdgpu_kernel void @s_test_sdiv24_k_den_i64(ptr addrspace(1) %out, i64 %x) {
1827 ; GCN-LABEL: s_test_sdiv24_k_den_i64:
1828 ; GCN: ; %bb.0:
1829 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
1830 ; GCN-NEXT: s_mov_b32 s8, 0x46b6fe00
1831 ; GCN-NEXT: s_mov_b32 s7, 0xf000
1832 ; GCN-NEXT: s_mov_b32 s6, -1
1833 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
1834 ; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 40
1835 ; GCN-NEXT: v_cvt_f32_i32_e32 v0, s2
1836 ; GCN-NEXT: s_mov_b32 s4, s0
1837 ; GCN-NEXT: s_ashr_i32 s0, s2, 30
1838 ; GCN-NEXT: s_mov_b32 s5, s1
1839 ; GCN-NEXT: v_mul_f32_e32 v1, 0x38331158, v0
1840 ; GCN-NEXT: v_trunc_f32_e32 v1, v1
1841 ; GCN-NEXT: v_mad_f32 v0, -v1, s8, v0
1842 ; GCN-NEXT: v_cvt_i32_f32_e32 v1, v1
1843 ; GCN-NEXT: s_or_b32 s2, s0, 1
1844 ; GCN-NEXT: v_cmp_ge_f32_e64 s[0:1], |v0|, s8
1845 ; GCN-NEXT: s_and_b64 s[0:1], s[0:1], exec
1846 ; GCN-NEXT: s_cselect_b32 s0, s2, 0
1847 ; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v1
1848 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
1849 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
1850 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1851 ; GCN-NEXT: s_endpgm
1852 ;
1853 ; GCN-IR-LABEL: s_test_sdiv24_k_den_i64:
1854 ; GCN-IR: ; %bb.0:
1855 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
1856 ; GCN-IR-NEXT: s_mov_b32 s8, 0x46b6fe00
1857 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
1858 ; GCN-IR-NEXT: s_mov_b32 s6, -1
1859 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
1860 ; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 40
1861 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s2
1862 ; GCN-IR-NEXT: s_mov_b32 s4, s0
1863 ; GCN-IR-NEXT: s_ashr_i32 s0, s2, 30
1864 ; GCN-IR-NEXT: s_mov_b32 s5, s1
1865 ; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x38331158, v0
1866 ; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
1867 ; GCN-IR-NEXT: v_mad_f32 v0, -v1, s8, v0
1868 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v1, v1
1869 ; GCN-IR-NEXT: s_or_b32 s2, s0, 1
1870 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[0:1], |v0|, s8
1871 ; GCN-IR-NEXT: s_and_b64 s[0:1], s[0:1], exec
1872 ; GCN-IR-NEXT: s_cselect_b32 s0, s2, 0
1873 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s0, v1
1874 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24
1875 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
1876 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1877 ; GCN-IR-NEXT: s_endpgm
1878 %x.shr = ashr i64 %x, 40
1879 %result = sdiv i64 %x.shr, 23423
1880 store i64 %result, ptr addrspace(1) %out
1881 ret void
1882 }
1884 define i64 @v_test_sdiv24_k_num_i64(i64 %x) {
1885 ; GCN-LABEL: v_test_sdiv24_k_num_i64:
1886 ; GCN: ; %bb.0:
1887 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1888 ; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 40
1889 ; GCN-NEXT: s_mov_b32 s4, 0x41c00000
1890 ; GCN-NEXT: v_cvt_f32_i32_e32 v1, v0
1891 ; GCN-NEXT: v_ashrrev_i32_e32 v0, 30, v0
1892 ; GCN-NEXT: v_or_b32_e32 v0, 1, v0
1893 ; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1
1894 ; GCN-NEXT: v_mul_f32_e32 v2, 0x41c00000, v2
1895 ; GCN-NEXT: v_trunc_f32_e32 v2, v2
1896 ; GCN-NEXT: v_mad_f32 v3, -v2, v1, s4
1897 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
1898 ; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1899 ; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
1900 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v2, v0
1901 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
1902 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
1903 ; GCN-NEXT: s_setpc_b64 s[30:31]
1904 ;
1905 ; GCN-IR-LABEL: v_test_sdiv24_k_num_i64:
1906 ; GCN-IR: ; %bb.0:
1907 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1908 ; GCN-IR-NEXT: v_ashr_i64 v[0:1], v[0:1], 40
1909 ; GCN-IR-NEXT: s_mov_b32 s4, 0x41c00000
1910 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, v0
1911 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v0, 30, v0
1912 ; GCN-IR-NEXT: v_or_b32_e32 v0, 1, v0
1913 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1
1914 ; GCN-IR-NEXT: v_mul_f32_e32 v2, 0x41c00000, v2
1915 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
1916 ; GCN-IR-NEXT: v_mad_f32 v3, -v2, v1, s4
1917 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2
1918 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1919 ; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
1920 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v2, v0
1921 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24
1922 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
1923 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
1924 %x.shr = ashr i64 %x, 40
1925 %result = sdiv i64 24, %x.shr
1926 ret i64 %result
1927 }
1929 define i64 @v_test_sdiv24_pow2_k_num_i64(i64 %x) {
1930 ; GCN-LABEL: v_test_sdiv24_pow2_k_num_i64:
1931 ; GCN: ; %bb.0:
1932 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1933 ; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 40
1934 ; GCN-NEXT: s_mov_b32 s4, 0x47000000
1935 ; GCN-NEXT: v_cvt_f32_i32_e32 v1, v0
1936 ; GCN-NEXT: v_ashrrev_i32_e32 v0, 30, v0
1937 ; GCN-NEXT: v_or_b32_e32 v0, 1, v0
1938 ; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1
1939 ; GCN-NEXT: v_mul_f32_e32 v2, 0x47000000, v2
1940 ; GCN-NEXT: v_trunc_f32_e32 v2, v2
1941 ; GCN-NEXT: v_mad_f32 v3, -v2, v1, s4
1942 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2
1943 ; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1944 ; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
1945 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v2, v0
1946 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24
1947 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0
1948 ; GCN-NEXT: s_setpc_b64 s[30:31]
1949 ;
1950 ; GCN-IR-LABEL: v_test_sdiv24_pow2_k_num_i64:
1951 ; GCN-IR: ; %bb.0:
1952 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1953 ; GCN-IR-NEXT: v_ashr_i64 v[0:1], v[0:1], 40
1954 ; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000
1955 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, v0
1956 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v0, 30, v0
1957 ; GCN-IR-NEXT: v_or_b32_e32 v0, 1, v0
1958 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1
1959 ; GCN-IR-NEXT: v_mul_f32_e32 v2, 0x47000000, v2
1960 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
1961 ; GCN-IR-NEXT: v_mad_f32 v3, -v2, v1, s4
1962 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2
1963 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1|
1964 ; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
1965 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v2, v0
1966 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24
1967 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
1968 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
1969 %x.shr = ashr i64 %x, 40
1970 %result = sdiv i64 32768, %x.shr
1971 ret i64 %result
1972 }
1974 define i64 @v_test_sdiv24_pow2_k_den_i64(i64 %x) {
1975 ; GCN-LABEL: v_test_sdiv24_pow2_k_den_i64:
1976 ; GCN: ; %bb.0:
1977 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1978 ; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 40
1979 ; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v1
1980 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
1981 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
1982 ; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 15
1983 ; GCN-NEXT: s_setpc_b64 s[30:31]
1984 ;
1985 ; GCN-IR-LABEL: v_test_sdiv24_pow2_k_den_i64:
1986 ; GCN-IR: ; %bb.0:
1987 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1988 ; GCN-IR-NEXT: v_ashr_i64 v[0:1], v[0:1], 40
1989 ; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000
1990 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, v0
1991 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v0, 30, v0
1992 ; GCN-IR-NEXT: v_or_b32_e32 v0, 1, v0
1993 ; GCN-IR-NEXT: v_mul_f32_e32 v2, 0x38000000, v1
1994 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
1995 ; GCN-IR-NEXT: v_mad_f32 v1, -v2, s4, v1
1996 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2
1997 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, s4
1998 ; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
1999 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v2, v0
2000 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24
2001 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0
2002 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
2003 %x.shr = ashr i64 %x, 40
2004 %result = sdiv i64 %x.shr, 32768
2005 ret i64 %result
2006 }