1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
4 define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) {
8 ; CHECK-NEXT: ALU 7, @4, KC0[], KC1[]
9 ; CHECK-NEXT: EXPORT T0.X___
11 ; CHECK-NEXT: ALU clause starting at 4:
12 ; CHECK-NEXT: MULADD_IEEE T0.X, T0.W, T0.W, literal.x,
13 ; CHECK-NEXT: MULADD_IEEE T0.Y, T1.W, T1.W, literal.x, BS:VEC_120/SCL_212
14 ; CHECK-NEXT: MULADD_IEEE * T0.Z, T2.W, T2.W, literal.x, BS:VEC_201
15 ; CHECK-NEXT: 1073741824(2.000000e+00), 0(0.000000e+00)
16 ; CHECK-NEXT: DOT4 T0.X, T0.X, T0.X,
17 ; CHECK-NEXT: DOT4 T0.Y (MASKED), T0.Y, T0.Y,
18 ; CHECK-NEXT: DOT4 T0.Z (MASKED), T0.Z, T0.Z,
19 ; CHECK-NEXT: DOT4 * T0.W (MASKED), T0.W, T0.W,
20 %w0 = extractelement <4 x float> %reg0, i32 3
21 %w1 = extractelement <4 x float> %reg1, i32 3
22 %w2 = extractelement <4 x float> %reg2, i32 3
23 %sq0 = fmul float %w0, %w0
24 %r0 = fadd float %sq0, 2.0
25 %sq1 = fmul float %w1, %w1
26 %r1 = fadd float %sq1, 2.0
27 %sq2 = fmul float %w2, %w2
28 %r2 = fadd float %sq2, 2.0
29 %v0 = insertelement <4 x float> undef, float %r0, i32 0
30 %v1 = insertelement <4 x float> %v0, float %r1, i32 1
31 %v2 = insertelement <4 x float> %v1, float %r2, i32 2
32 %res = call float @llvm.r600.dot4(<4 x float> %v2, <4 x float> %v2)
33 %vecres = insertelement <4 x float> undef, float %res, i32 0
34 call void @llvm.r600.store.swizzle(<4 x float> %vecres, i32 0, i32 2)
38 ; Function Attrs: readnone
39 declare float @llvm.r600.dot4(<4 x float>, <4 x float>) #1
41 declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)
43 attributes #1 = { readnone }