| blob | 9cd13b3d45150999a7ec3820b4765dbfd032d64a |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-- -mcpu=verde -verify-machineinstrs | FileCheck %s --check-prefixes=SI
3 ; RUN: llc < %s -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s -check-prefixes=VI
4 ; RUN: llc < %s -amdgpu-scalarize-global-loads=false -march=r600 -mtriple=r600-- -mcpu=redwood -verify-machineinstrs | FileCheck %s --check-prefixes=EG
6 declare i32 @llvm.amdgcn.workitem.id.x() #0
8 declare i32 @llvm.amdgcn.workgroup.id.x() #0
10 define amdgpu_kernel void @shl_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
11 ; SI-LABEL: shl_v2i32:
12 ; SI: ; %bb.0:
13 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
14 ; SI-NEXT: s_mov_b32 s7, 0xf000
15 ; SI-NEXT: s_mov_b32 s6, -1
16 ; SI-NEXT: s_mov_b32 s10, s6
17 ; SI-NEXT: s_mov_b32 s11, s7
18 ; SI-NEXT: s_waitcnt lgkmcnt(0)
19 ; SI-NEXT: s_mov_b32 s8, s2
20 ; SI-NEXT: s_mov_b32 s9, s3
21 ; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
22 ; SI-NEXT: s_mov_b32 s4, s0
23 ; SI-NEXT: s_mov_b32 s5, s1
24 ; SI-NEXT: s_waitcnt vmcnt(0)
25 ; SI-NEXT: v_lshl_b32_e32 v1, v1, v3
26 ; SI-NEXT: v_lshl_b32_e32 v0, v0, v2
27 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
28 ; SI-NEXT: s_endpgm
29 ;
30 ; VI-LABEL: shl_v2i32:
31 ; VI: ; %bb.0:
32 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
33 ; VI-NEXT: s_waitcnt lgkmcnt(0)
34 ; VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
35 ; VI-NEXT: s_mov_b32 s3, 0xf000
36 ; VI-NEXT: s_mov_b32 s2, -1
37 ; VI-NEXT: s_waitcnt lgkmcnt(0)
38 ; VI-NEXT: s_lshl_b32 s5, s5, s7
39 ; VI-NEXT: s_lshl_b32 s4, s4, s6
40 ; VI-NEXT: v_mov_b32_e32 v0, s4
41 ; VI-NEXT: v_mov_b32_e32 v1, s5
42 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
43 ; VI-NEXT: s_endpgm
44 ;
45 ; EG-LABEL: shl_v2i32:
46 ; EG: ; %bb.0:
47 ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
48 ; EG-NEXT: TEX 0 @6
49 ; EG-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]
50 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
51 ; EG-NEXT: CF_END
52 ; EG-NEXT: PAD
53 ; EG-NEXT: Fetch clause starting at 6:
54 ; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
55 ; EG-NEXT: ALU clause starting at 8:
56 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
57 ; EG-NEXT: ALU clause starting at 9:
58 ; EG-NEXT: LSHL * T0.Y, T0.Y, T0.W,
59 ; EG-NEXT: LSHL T0.X, T0.X, T0.Z,
60 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
61 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
62 %b_ptr = getelementptr <2 x i32>, ptr addrspace(1) %in, i32 1
63 %a = load <2 x i32>, ptr addrspace(1) %in
64 %b = load <2 x i32>, ptr addrspace(1) %b_ptr
65 %result = shl <2 x i32> %a, %b
66 store <2 x i32> %result, ptr addrspace(1) %out
67 ret void
68 }
70 define amdgpu_kernel void @shl_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
71 ; SI-LABEL: shl_v4i32:
72 ; SI: ; %bb.0:
73 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
74 ; SI-NEXT: s_mov_b32 s7, 0xf000
75 ; SI-NEXT: s_mov_b32 s6, -1
76 ; SI-NEXT: s_mov_b32 s10, s6
77 ; SI-NEXT: s_mov_b32 s11, s7
78 ; SI-NEXT: s_waitcnt lgkmcnt(0)
79 ; SI-NEXT: s_mov_b32 s8, s2
80 ; SI-NEXT: s_mov_b32 s9, s3
81 ; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
82 ; SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
83 ; SI-NEXT: s_mov_b32 s4, s0
84 ; SI-NEXT: s_mov_b32 s5, s1
85 ; SI-NEXT: s_waitcnt vmcnt(0)
86 ; SI-NEXT: v_lshl_b32_e32 v3, v3, v7
87 ; SI-NEXT: v_lshl_b32_e32 v2, v2, v6
88 ; SI-NEXT: v_lshl_b32_e32 v1, v1, v5
89 ; SI-NEXT: v_lshl_b32_e32 v0, v0, v4
90 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
91 ; SI-NEXT: s_endpgm
92 ;
93 ; VI-LABEL: shl_v4i32:
94 ; VI: ; %bb.0:
95 ; VI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24
96 ; VI-NEXT: s_waitcnt lgkmcnt(0)
97 ; VI-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
98 ; VI-NEXT: s_mov_b32 s11, 0xf000
99 ; VI-NEXT: s_mov_b32 s10, -1
100 ; VI-NEXT: s_waitcnt lgkmcnt(0)
101 ; VI-NEXT: s_lshl_b32 s3, s3, s7
102 ; VI-NEXT: s_lshl_b32 s2, s2, s6
103 ; VI-NEXT: s_lshl_b32 s1, s1, s5
104 ; VI-NEXT: s_lshl_b32 s0, s0, s4
105 ; VI-NEXT: v_mov_b32_e32 v0, s0
106 ; VI-NEXT: v_mov_b32_e32 v1, s1
107 ; VI-NEXT: v_mov_b32_e32 v2, s2
108 ; VI-NEXT: v_mov_b32_e32 v3, s3
109 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
110 ; VI-NEXT: s_endpgm
111 ;
112 ; EG-LABEL: shl_v4i32:
113 ; EG: ; %bb.0:
114 ; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
115 ; EG-NEXT: TEX 1 @6
116 ; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[]
117 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
118 ; EG-NEXT: CF_END
119 ; EG-NEXT: PAD
120 ; EG-NEXT: Fetch clause starting at 6:
121 ; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1
122 ; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
123 ; EG-NEXT: ALU clause starting at 10:
124 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
125 ; EG-NEXT: ALU clause starting at 11:
126 ; EG-NEXT: LSHL * T0.W, T0.W, T1.W,
127 ; EG-NEXT: LSHL * T0.Z, T0.Z, T1.Z,
128 ; EG-NEXT: LSHL * T0.Y, T0.Y, T1.Y,
129 ; EG-NEXT: LSHL T0.X, T0.X, T1.X,
130 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
131 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
132 %b_ptr = getelementptr <4 x i32>, ptr addrspace(1) %in, i32 1
133 %a = load <4 x i32>, ptr addrspace(1) %in
134 %b = load <4 x i32>, ptr addrspace(1) %b_ptr
135 %result = shl <4 x i32> %a, %b
136 store <4 x i32> %result, ptr addrspace(1) %out
137 ret void
138 }
140 define amdgpu_kernel void @shl_i16(ptr addrspace(1) %out, ptr addrspace(1) %in) {
141 ; SI-LABEL: shl_i16:
142 ; SI: ; %bb.0:
143 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
144 ; SI-NEXT: s_mov_b32 s7, 0xf000
145 ; SI-NEXT: s_mov_b32 s6, -1
146 ; SI-NEXT: s_mov_b32 s10, s6
147 ; SI-NEXT: s_mov_b32 s11, s7
148 ; SI-NEXT: s_waitcnt lgkmcnt(0)
149 ; SI-NEXT: s_mov_b32 s8, s2
150 ; SI-NEXT: s_mov_b32 s9, s3
151 ; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 0
152 ; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 offset:2
153 ; SI-NEXT: s_mov_b32 s4, s0
154 ; SI-NEXT: s_mov_b32 s5, s1
155 ; SI-NEXT: s_waitcnt vmcnt(0)
156 ; SI-NEXT: v_lshl_b32_e32 v0, v0, v1
157 ; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
158 ; SI-NEXT: s_endpgm
159 ;
160 ; VI-LABEL: shl_i16:
161 ; VI: ; %bb.0:
162 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
163 ; VI-NEXT: s_mov_b32 s7, 0xf000
164 ; VI-NEXT: s_mov_b32 s6, -1
165 ; VI-NEXT: s_mov_b32 s10, s6
166 ; VI-NEXT: s_mov_b32 s11, s7
167 ; VI-NEXT: s_waitcnt lgkmcnt(0)
168 ; VI-NEXT: s_mov_b32 s8, s2
169 ; VI-NEXT: s_mov_b32 s9, s3
170 ; VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0
171 ; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 offset:2
172 ; VI-NEXT: s_mov_b32 s4, s0
173 ; VI-NEXT: s_mov_b32 s5, s1
174 ; VI-NEXT: s_waitcnt vmcnt(0)
175 ; VI-NEXT: v_lshlrev_b32_e32 v0, v1, v0
176 ; VI-NEXT: buffer_store_short v0, off, s[4:7], 0
177 ; VI-NEXT: s_endpgm
178 ;
179 ; EG-LABEL: shl_i16:
180 ; EG: ; %bb.0:
181 ; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
182 ; EG-NEXT: TEX 1 @6
183 ; EG-NEXT: ALU 12, @11, KC0[CB0:0-32], KC1[]
184 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
185 ; EG-NEXT: CF_END
186 ; EG-NEXT: PAD
187 ; EG-NEXT: Fetch clause starting at 6:
188 ; EG-NEXT: VTX_READ_16 T1.X, T0.X, 2, #1
189 ; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #1
190 ; EG-NEXT: ALU clause starting at 10:
191 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
192 ; EG-NEXT: ALU clause starting at 11:
193 ; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,
194 ; EG-NEXT: LSHL * T1.W, T0.X, T1.X,
195 ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
196 ; EG-NEXT: AND_INT T1.W, PS, literal.x,
197 ; EG-NEXT: LSHL * T0.W, PV.W, literal.y,
198 ; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)
199 ; EG-NEXT: LSHL T0.X, PV.W, PS,
200 ; EG-NEXT: LSHL * T0.W, literal.x, PS,
201 ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
202 ; EG-NEXT: MOV T0.Y, 0.0,
203 ; EG-NEXT: MOV * T0.Z, 0.0,
204 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
205 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
206 %b_ptr = getelementptr i16, ptr addrspace(1) %in, i16 1
207 %a = load i16, ptr addrspace(1) %in
208 %b = load i16, ptr addrspace(1) %b_ptr
209 %result = shl i16 %a, %b
210 store i16 %result, ptr addrspace(1) %out
211 ret void
212 }
214 define amdgpu_kernel void @shl_i16_v_s(ptr addrspace(1) %out, ptr addrspace(1) %in, i16 %b) {
215 ; SI-LABEL: shl_i16_v_s:
216 ; SI: ; %bb.0:
217 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
218 ; SI-NEXT: s_load_dword s12, s[0:1], 0xd
219 ; SI-NEXT: s_mov_b32 s3, 0xf000
220 ; SI-NEXT: s_mov_b32 s2, -1
221 ; SI-NEXT: s_mov_b32 s10, s2
222 ; SI-NEXT: s_waitcnt lgkmcnt(0)
223 ; SI-NEXT: s_mov_b32 s8, s6
224 ; SI-NEXT: s_mov_b32 s9, s7
225 ; SI-NEXT: s_mov_b32 s11, s3
226 ; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 0
227 ; SI-NEXT: s_mov_b32 s0, s4
228 ; SI-NEXT: s_mov_b32 s1, s5
229 ; SI-NEXT: s_waitcnt vmcnt(0)
230 ; SI-NEXT: v_lshlrev_b32_e32 v0, s12, v0
231 ; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
232 ; SI-NEXT: s_endpgm
233 ;
234 ; VI-LABEL: shl_i16_v_s:
235 ; VI: ; %bb.0:
236 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
237 ; VI-NEXT: s_load_dword s12, s[0:1], 0x34
238 ; VI-NEXT: s_mov_b32 s3, 0xf000
239 ; VI-NEXT: s_mov_b32 s2, -1
240 ; VI-NEXT: s_mov_b32 s10, s2
241 ; VI-NEXT: s_waitcnt lgkmcnt(0)
242 ; VI-NEXT: s_mov_b32 s8, s6
243 ; VI-NEXT: s_mov_b32 s9, s7
244 ; VI-NEXT: s_mov_b32 s11, s3
245 ; VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0
246 ; VI-NEXT: s_mov_b32 s0, s4
247 ; VI-NEXT: s_mov_b32 s1, s5
248 ; VI-NEXT: s_waitcnt vmcnt(0)
249 ; VI-NEXT: v_lshlrev_b32_e32 v0, s12, v0
250 ; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
251 ; VI-NEXT: s_endpgm
252 ;
253 ; EG-LABEL: shl_i16_v_s:
254 ; EG: ; %bb.0:
255 ; EG-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[]
256 ; EG-NEXT: TEX 1 @6
257 ; EG-NEXT: ALU 12, @12, KC0[CB0:0-32], KC1[]
258 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
259 ; EG-NEXT: CF_END
260 ; EG-NEXT: PAD
261 ; EG-NEXT: Fetch clause starting at 6:
262 ; EG-NEXT: VTX_READ_16 T1.X, T1.X, 0, #1
263 ; EG-NEXT: VTX_READ_16 T0.X, T0.X, 44, #3
264 ; EG-NEXT: ALU clause starting at 10:
265 ; EG-NEXT: MOV T0.X, 0.0,
266 ; EG-NEXT: MOV * T1.X, KC0[2].Z,
267 ; EG-NEXT: ALU clause starting at 12:
268 ; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,
269 ; EG-NEXT: LSHL * T1.W, T1.X, T0.X,
270 ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
271 ; EG-NEXT: AND_INT T1.W, PS, literal.x,
272 ; EG-NEXT: LSHL * T0.W, PV.W, literal.y,
273 ; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)
274 ; EG-NEXT: LSHL T0.X, PV.W, PS,
275 ; EG-NEXT: LSHL * T0.W, literal.x, PS,
276 ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
277 ; EG-NEXT: MOV T0.Y, 0.0,
278 ; EG-NEXT: MOV * T0.Z, 0.0,
279 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
280 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
281 %a = load i16, ptr addrspace(1) %in
282 %result = shl i16 %a, %b
283 store i16 %result, ptr addrspace(1) %out
284 ret void
285 }
287 define amdgpu_kernel void @shl_i16_v_compute_s(ptr addrspace(1) %out, ptr addrspace(1) %in, i16 %b) {
288 ; SI-LABEL: shl_i16_v_compute_s:
289 ; SI: ; %bb.0:
290 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
291 ; SI-NEXT: s_load_dword s12, s[0:1], 0xd
292 ; SI-NEXT: s_mov_b32 s3, 0xf000
293 ; SI-NEXT: s_mov_b32 s2, -1
294 ; SI-NEXT: s_mov_b32 s10, s2
295 ; SI-NEXT: s_waitcnt lgkmcnt(0)
296 ; SI-NEXT: s_mov_b32 s8, s6
297 ; SI-NEXT: s_mov_b32 s9, s7
298 ; SI-NEXT: s_mov_b32 s11, s3
299 ; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 0
300 ; SI-NEXT: s_add_i32 s12, s12, 3
301 ; SI-NEXT: s_mov_b32 s0, s4
302 ; SI-NEXT: s_mov_b32 s1, s5
303 ; SI-NEXT: s_waitcnt vmcnt(0)
304 ; SI-NEXT: v_lshlrev_b32_e32 v0, s12, v0
305 ; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
306 ; SI-NEXT: s_endpgm
307 ;
308 ; VI-LABEL: shl_i16_v_compute_s:
309 ; VI: ; %bb.0:
310 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
311 ; VI-NEXT: s_load_dword s12, s[0:1], 0x34
312 ; VI-NEXT: s_mov_b32 s3, 0xf000
313 ; VI-NEXT: s_mov_b32 s2, -1
314 ; VI-NEXT: s_mov_b32 s10, s2
315 ; VI-NEXT: s_waitcnt lgkmcnt(0)
316 ; VI-NEXT: s_mov_b32 s8, s6
317 ; VI-NEXT: s_mov_b32 s9, s7
318 ; VI-NEXT: s_mov_b32 s11, s3
319 ; VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0
320 ; VI-NEXT: s_add_i32 s12, s12, 3
321 ; VI-NEXT: s_mov_b32 s0, s4
322 ; VI-NEXT: s_mov_b32 s1, s5
323 ; VI-NEXT: s_waitcnt vmcnt(0)
324 ; VI-NEXT: v_lshlrev_b32_e32 v0, s12, v0
325 ; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
326 ; VI-NEXT: s_endpgm
327 ;
328 ; EG-LABEL: shl_i16_v_compute_s:
329 ; EG: ; %bb.0:
330 ; EG-NEXT: ALU 0, @12, KC0[], KC1[]
331 ; EG-NEXT: TEX 0 @8
332 ; EG-NEXT: ALU 0, @13, KC0[CB0:0-32], KC1[]
333 ; EG-NEXT: TEX 0 @10
334 ; EG-NEXT: ALU 15, @14, KC0[CB0:0-32], KC1[]
335 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
336 ; EG-NEXT: CF_END
337 ; EG-NEXT: PAD
338 ; EG-NEXT: Fetch clause starting at 8:
339 ; EG-NEXT: VTX_READ_16 T0.X, T0.X, 44, #3
340 ; EG-NEXT: Fetch clause starting at 10:
341 ; EG-NEXT: VTX_READ_16 T1.X, T1.X, 0, #1
342 ; EG-NEXT: ALU clause starting at 12:
343 ; EG-NEXT: MOV * T0.X, 0.0,
344 ; EG-NEXT: ALU clause starting at 13:
345 ; EG-NEXT: MOV * T1.X, KC0[2].Z,
346 ; EG-NEXT: ALU clause starting at 14:
347 ; EG-NEXT: ADD_INT * T0.W, T0.X, literal.x,
348 ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
349 ; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
350 ; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y,
351 ; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)
352 ; EG-NEXT: LSHL * T0.W, T1.X, PV.W,
353 ; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
354 ; EG-NEXT: LSHL * T1.W, T1.W, literal.y,
355 ; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)
356 ; EG-NEXT: LSHL T0.X, PV.W, PS,
357 ; EG-NEXT: LSHL * T0.W, literal.x, PS,
358 ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
359 ; EG-NEXT: MOV T0.Y, 0.0,
360 ; EG-NEXT: MOV * T0.Z, 0.0,
361 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
362 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
363 %a = load i16, ptr addrspace(1) %in
364 %b.add = add i16 %b, 3
365 %result = shl i16 %a, %b.add
366 store i16 %result, ptr addrspace(1) %out
367 ret void
368 }
370 define amdgpu_kernel void @shl_i16_computed_amount(ptr addrspace(1) %out, ptr addrspace(1) %in) {
371 ; SI-LABEL: shl_i16_computed_amount:
372 ; SI: ; %bb.0:
373 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
374 ; SI-NEXT: s_mov_b32 s7, 0xf000
375 ; SI-NEXT: s_mov_b32 s6, -1
376 ; SI-NEXT: s_mov_b32 s10, s6
377 ; SI-NEXT: s_mov_b32 s11, s7
378 ; SI-NEXT: s_waitcnt lgkmcnt(0)
379 ; SI-NEXT: s_mov_b32 s8, s2
380 ; SI-NEXT: s_mov_b32 s9, s3
381 ; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v0
382 ; SI-NEXT: v_mov_b32_e32 v1, 0
383 ; SI-NEXT: s_mov_b32 s14, 0
384 ; SI-NEXT: s_mov_b32 s15, s7
385 ; SI-NEXT: s_mov_b64 s[12:13], s[2:3]
386 ; SI-NEXT: buffer_load_ushort v2, off, s[8:11], 0 glc
387 ; SI-NEXT: s_waitcnt vmcnt(0)
388 ; SI-NEXT: buffer_load_ushort v0, v[0:1], s[12:15], 0 addr64 offset:2 glc
389 ; SI-NEXT: s_waitcnt vmcnt(0)
390 ; SI-NEXT: s_mov_b32 s4, s0
391 ; SI-NEXT: s_mov_b32 s5, s1
392 ; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
393 ; SI-NEXT: v_lshlrev_b32_e32 v0, v0, v2
394 ; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
395 ; SI-NEXT: s_endpgm
396 ;
397 ; VI-LABEL: shl_i16_computed_amount:
398 ; VI: ; %bb.0:
399 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
400 ; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v0
401 ; VI-NEXT: s_mov_b32 s7, 0xf000
402 ; VI-NEXT: s_mov_b32 s6, -1
403 ; VI-NEXT: s_mov_b32 s10, s6
404 ; VI-NEXT: s_waitcnt lgkmcnt(0)
405 ; VI-NEXT: v_mov_b32_e32 v1, s3
406 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
407 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
408 ; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0
409 ; VI-NEXT: s_mov_b32 s8, s2
410 ; VI-NEXT: s_mov_b32 s9, s3
411 ; VI-NEXT: s_mov_b32 s11, s7
412 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
413 ; VI-NEXT: buffer_load_ushort v2, off, s[8:11], 0 glc
414 ; VI-NEXT: s_waitcnt vmcnt(0)
415 ; VI-NEXT: flat_load_ushort v0, v[0:1] glc
416 ; VI-NEXT: s_waitcnt vmcnt(0)
417 ; VI-NEXT: s_mov_b32 s4, s0
418 ; VI-NEXT: s_mov_b32 s5, s1
419 ; VI-NEXT: v_add_u16_e32 v0, 3, v0
420 ; VI-NEXT: v_lshlrev_b16_e32 v0, v0, v2
421 ; VI-NEXT: buffer_store_short v0, off, s[4:7], 0
422 ; VI-NEXT: s_endpgm
423 ;
424 ; EG-LABEL: shl_i16_computed_amount:
425 ; EG: ; %bb.0:
426 ; EG-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[]
427 ; EG-NEXT: TEX 0 @8
428 ; EG-NEXT: ALU 1, @13, KC0[CB0:0-32], KC1[]
429 ; EG-NEXT: TEX 0 @10
430 ; EG-NEXT: ALU 15, @15, KC0[CB0:0-32], KC1[]
431 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
432 ; EG-NEXT: CF_END
433 ; EG-NEXT: PAD
434 ; EG-NEXT: Fetch clause starting at 8:
435 ; EG-NEXT: VTX_READ_16 T1.X, T1.X, 0, #1
436 ; EG-NEXT: Fetch clause starting at 10:
437 ; EG-NEXT: VTX_READ_16 T0.X, T0.X, 2, #1
438 ; EG-NEXT: ALU clause starting at 12:
439 ; EG-NEXT: MOV * T1.X, KC0[2].Z,
440 ; EG-NEXT: ALU clause starting at 13:
441 ; EG-NEXT: LSHL * T0.W, T0.X, 1,
442 ; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,
443 ; EG-NEXT: ALU clause starting at 15:
444 ; EG-NEXT: ADD_INT * T0.W, T0.X, literal.x,
445 ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
446 ; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
447 ; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y,
448 ; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)
449 ; EG-NEXT: LSHL * T0.W, T1.X, PV.W,
450 ; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
451 ; EG-NEXT: LSHL * T1.W, T1.W, literal.y,
452 ; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)
453 ; EG-NEXT: LSHL T0.X, PV.W, PS,
454 ; EG-NEXT: LSHL * T0.W, literal.x, PS,
455 ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
456 ; EG-NEXT: MOV T0.Y, 0.0,
457 ; EG-NEXT: MOV * T0.Z, 0.0,
458 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
459 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
460 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0
461 %gep = getelementptr inbounds i16, ptr addrspace(1) %in, i32 %tid
462 %gep.out = getelementptr inbounds i16, ptr addrspace(1) %out, i32 %tid
463 %b_ptr = getelementptr i16, ptr addrspace(1) %gep, i16 1
464 %a = load volatile i16, ptr addrspace(1) %in
465 %b = load volatile i16, ptr addrspace(1) %b_ptr
466 %b.add = add i16 %b, 3
467 %result = shl i16 %a, %b.add
468 store i16 %result, ptr addrspace(1) %out
469 ret void
470 }
472 define amdgpu_kernel void @shl_i16_i_s(ptr addrspace(1) %out, i16 zeroext %a) {
473 ; SI-LABEL: shl_i16_i_s:
474 ; SI: ; %bb.0:
475 ; SI-NEXT: s_load_dword s4, s[0:1], 0xb
476 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
477 ; SI-NEXT: s_mov_b32 s3, 0xf000
478 ; SI-NEXT: s_mov_b32 s2, -1
479 ; SI-NEXT: s_waitcnt lgkmcnt(0)
480 ; SI-NEXT: s_lshl_b32 s4, s4, 12
481 ; SI-NEXT: v_mov_b32_e32 v0, s4
482 ; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
483 ; SI-NEXT: s_endpgm
484 ;
485 ; VI-LABEL: shl_i16_i_s:
486 ; VI: ; %bb.0:
487 ; VI-NEXT: s_load_dword s4, s[0:1], 0x2c
488 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
489 ; VI-NEXT: s_mov_b32 s3, 0xf000
490 ; VI-NEXT: s_mov_b32 s2, -1
491 ; VI-NEXT: s_waitcnt lgkmcnt(0)
492 ; VI-NEXT: s_lshl_b32 s4, s4, 12
493 ; VI-NEXT: v_mov_b32_e32 v0, s4
494 ; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
495 ; VI-NEXT: s_endpgm
496 ;
497 ; EG-LABEL: shl_i16_i_s:
498 ; EG: ; %bb.0:
499 ; EG-NEXT: ALU 0, @8, KC0[], KC1[]
500 ; EG-NEXT: TEX 0 @6
501 ; EG-NEXT: ALU 14, @9, KC0[CB0:0-32], KC1[]
502 ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
503 ; EG-NEXT: CF_END
504 ; EG-NEXT: PAD
505 ; EG-NEXT: Fetch clause starting at 6:
506 ; EG-NEXT: VTX_READ_16 T0.X, T0.X, 40, #3
507 ; EG-NEXT: ALU clause starting at 8:
508 ; EG-NEXT: MOV * T0.X, 0.0,
509 ; EG-NEXT: ALU clause starting at 9:
510 ; EG-NEXT: BFE_INT T0.W, T0.X, 0.0, literal.x,
511 ; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y,
512 ; EG-NEXT: 16(2.242078e-44), 3(4.203895e-45)
513 ; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
514 ; EG-NEXT: 12(1.681558e-44), 0(0.000000e+00)
515 ; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
516 ; EG-NEXT: LSHL * T1.W, T1.W, literal.y,
517 ; EG-NEXT: 61440(8.609578e-41), 3(4.203895e-45)
518 ; EG-NEXT: LSHL T0.X, PV.W, PS,
519 ; EG-NEXT: LSHL * T0.W, literal.x, PS,
520 ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
521 ; EG-NEXT: MOV T0.Y, 0.0,
522 ; EG-NEXT: MOV * T0.Z, 0.0,
523 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
524 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
525 %result = shl i16 %a, 12
526 store i16 %result, ptr addrspace(1) %out
527 ret void
528 }
530 define amdgpu_kernel void @shl_v2i16(ptr addrspace(1) %out, ptr addrspace(1) %in) {
531 ; SI-LABEL: shl_v2i16:
532 ; SI: ; %bb.0:
533 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
534 ; SI-NEXT: s_mov_b32 s7, 0xf000
535 ; SI-NEXT: s_mov_b32 s6, -1
536 ; SI-NEXT: s_mov_b32 s10, s6
537 ; SI-NEXT: s_mov_b32 s11, s7
538 ; SI-NEXT: s_waitcnt lgkmcnt(0)
539 ; SI-NEXT: s_mov_b32 s8, s2
540 ; SI-NEXT: s_mov_b32 s9, s3
541 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
542 ; SI-NEXT: v_mov_b32_e32 v1, 0
543 ; SI-NEXT: s_mov_b32 s14, 0
544 ; SI-NEXT: s_mov_b32 s15, s7
545 ; SI-NEXT: s_mov_b64 s[12:13], s[2:3]
546 ; SI-NEXT: buffer_load_dword v2, off, s[8:11], 0
547 ; SI-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64 offset:4
548 ; SI-NEXT: s_mov_b32 s4, s0
549 ; SI-NEXT: s_mov_b32 s5, s1
550 ; SI-NEXT: s_waitcnt vmcnt(1)
551 ; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
552 ; SI-NEXT: s_waitcnt vmcnt(0)
553 ; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
554 ; SI-NEXT: v_lshlrev_b32_e32 v0, v0, v2
555 ; SI-NEXT: v_lshlrev_b32_e32 v1, v3, v1
556 ; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
557 ; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
558 ; SI-NEXT: v_or_b32_e32 v0, v0, v1
559 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
560 ; SI-NEXT: s_endpgm
561 ;
562 ; VI-LABEL: shl_v2i16:
563 ; VI: ; %bb.0:
564 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
565 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
566 ; VI-NEXT: s_waitcnt lgkmcnt(0)
567 ; VI-NEXT: v_mov_b32_e32 v1, s3
568 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
569 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
570 ; VI-NEXT: v_add_u32_e32 v0, vcc, 4, v0
571 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
572 ; VI-NEXT: flat_load_dword v0, v[0:1]
573 ; VI-NEXT: s_load_dword s4, s[2:3], 0x0
574 ; VI-NEXT: s_mov_b32 s3, 0xf000
575 ; VI-NEXT: s_mov_b32 s2, -1
576 ; VI-NEXT: s_waitcnt lgkmcnt(0)
577 ; VI-NEXT: s_lshr_b32 s5, s4, 16
578 ; VI-NEXT: v_mov_b32_e32 v1, s5
579 ; VI-NEXT: s_waitcnt vmcnt(0)
580 ; VI-NEXT: v_lshlrev_b16_e64 v2, v0, s4
581 ; VI-NEXT: v_lshlrev_b16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
582 ; VI-NEXT: v_or_b32_e32 v0, v2, v0
583 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
584 ; VI-NEXT: s_endpgm
585 ;
586 ; EG-LABEL: shl_v2i16:
587 ; EG: ; %bb.0:
588 ; EG-NEXT: ALU 2, @12, KC0[CB0:0-32], KC1[]
589 ; EG-NEXT: TEX 0 @8
590 ; EG-NEXT: ALU 0, @15, KC0[CB0:0-32], KC1[]
591 ; EG-NEXT: TEX 0 @10
592 ; EG-NEXT: ALU 11, @16, KC0[CB0:0-32], KC1[]
593 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T7.X, 1
594 ; EG-NEXT: CF_END
595 ; EG-NEXT: PAD
596 ; EG-NEXT: Fetch clause starting at 8:
597 ; EG-NEXT: VTX_READ_32 T0.X, T0.X, 4, #1
598 ; EG-NEXT: Fetch clause starting at 10:
599 ; EG-NEXT: VTX_READ_32 T7.X, T7.X, 0, #1
600 ; EG-NEXT: ALU clause starting at 12:
601 ; EG-NEXT: LSHL * T0.W, T0.X, literal.x,
602 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
603 ; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,
604 ; EG-NEXT: ALU clause starting at 15:
605 ; EG-NEXT: MOV * T7.X, KC0[2].Z,
606 ; EG-NEXT: ALU clause starting at 16:
607 ; EG-NEXT: AND_INT T0.Z, T0.X, literal.x,
608 ; EG-NEXT: LSHR T0.W, T0.X, literal.y,
609 ; EG-NEXT: LSHR * T1.W, T7.X, literal.y,
610 ; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)
611 ; EG-NEXT: LSHL T0.W, PS, PV.W,
612 ; EG-NEXT: LSHL * T1.W, T7.X, PV.Z,
613 ; EG-NEXT: AND_INT T1.W, PS, literal.x,
614 ; EG-NEXT: LSHL * T0.W, PV.W, literal.y,
615 ; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)
616 ; EG-NEXT: OR_INT T0.X, PV.W, PS,
617 ; EG-NEXT: LSHR * T7.X, KC0[2].Y, literal.x,
618 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
619 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0
620 %gep = getelementptr inbounds <2 x i16>, ptr addrspace(1) %in, i32 %tid
621 %gep.out = getelementptr inbounds <2 x i16>, ptr addrspace(1) %out, i32 %tid
622 %b_ptr = getelementptr <2 x i16>, ptr addrspace(1) %gep, i16 1
623 %a = load <2 x i16>, ptr addrspace(1) %in
624 %b = load <2 x i16>, ptr addrspace(1) %b_ptr
625 %result = shl <2 x i16> %a, %b
626 store <2 x i16> %result, ptr addrspace(1) %out
627 ret void
628 }
630 define amdgpu_kernel void @shl_v4i16(ptr addrspace(1) %out, ptr addrspace(1) %in) {
631 ; SI-LABEL: shl_v4i16:
632 ; SI: ; %bb.0:
633 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
634 ; SI-NEXT: s_mov_b32 s7, 0xf000
635 ; SI-NEXT: s_mov_b32 s6, 0
636 ; SI-NEXT: v_lshlrev_b32_e32 v4, 3, v0
637 ; SI-NEXT: v_mov_b32_e32 v5, 0
638 ; SI-NEXT: s_waitcnt lgkmcnt(0)
639 ; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
640 ; SI-NEXT: buffer_load_dwordx4 v[0:3], v[4:5], s[4:7], 0 addr64
641 ; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
642 ; SI-NEXT: s_waitcnt vmcnt(0)
643 ; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v0
644 ; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v1
645 ; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v2
646 ; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v3
647 ; SI-NEXT: v_lshlrev_b32_e32 v1, v3, v1
648 ; SI-NEXT: v_lshlrev_b32_e32 v0, v2, v0
649 ; SI-NEXT: v_lshlrev_b32_e32 v2, v9, v7
650 ; SI-NEXT: v_lshlrev_b32_e32 v3, v8, v6
651 ; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
652 ; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
653 ; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
654 ; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
655 ; SI-NEXT: v_or_b32_e32 v1, v1, v2
656 ; SI-NEXT: v_or_b32_e32 v0, v0, v3
657 ; SI-NEXT: buffer_store_dwordx2 v[0:1], v[4:5], s[0:3], 0 addr64
658 ; SI-NEXT: s_endpgm
659 ;
660 ; VI-LABEL: shl_v4i16:
661 ; VI: ; %bb.0:
662 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
663 ; VI-NEXT: v_lshlrev_b32_e32 v4, 3, v0
664 ; VI-NEXT: s_waitcnt lgkmcnt(0)
665 ; VI-NEXT: v_mov_b32_e32 v1, s3
666 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
667 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
668 ; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
669 ; VI-NEXT: v_mov_b32_e32 v5, s1
670 ; VI-NEXT: v_add_u32_e32 v4, vcc, s0, v4
671 ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
672 ; VI-NEXT: s_waitcnt vmcnt(0)
673 ; VI-NEXT: v_lshlrev_b16_e32 v6, v3, v1
674 ; VI-NEXT: v_lshlrev_b16_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
675 ; VI-NEXT: v_lshlrev_b16_e32 v3, v2, v0
676 ; VI-NEXT: v_lshlrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
677 ; VI-NEXT: v_or_b32_e32 v1, v6, v1
678 ; VI-NEXT: v_or_b32_e32 v0, v3, v0
679 ; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
680 ; VI-NEXT: s_endpgm
681 ;
682 ; EG-LABEL: shl_v4i16:
683 ; EG: ; %bb.0:
684 ; EG-NEXT: ALU 3, @8, KC0[CB0:0-32], KC1[]
685 ; EG-NEXT: TEX 0 @6
686 ; EG-NEXT: ALU 42, @12, KC0[CB0:0-32], KC1[]
687 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T10.XY, T0.X, 1
688 ; EG-NEXT: CF_END
689 ; EG-NEXT: PAD
690 ; EG-NEXT: Fetch clause starting at 6:
691 ; EG-NEXT: VTX_READ_128 T10.XYZW, T0.X, 0, #1
692 ; EG-NEXT: ALU clause starting at 8:
693 ; EG-NEXT: MOV T0.Y, T6.X,
694 ; EG-NEXT: LSHL * T0.W, T0.X, literal.x, BS:VEC_120/SCL_212
695 ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
696 ; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,
697 ; EG-NEXT: ALU clause starting at 12:
698 ; EG-NEXT: AND_INT * T1.W, T10.Z, literal.x,
699 ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
700 ; EG-NEXT: LSHL * T1.W, T10.X, PV.W,
701 ; EG-NEXT: AND_INT T1.W, PV.W, literal.x,
702 ; EG-NEXT: AND_INT * T2.W, T0.Y, literal.y,
703 ; EG-NEXT: 65535(9.183409e-41), -65536(nan)
704 ; EG-NEXT: OR_INT * T1.W, PS, PV.W,
705 ; EG-NEXT: MOV * T6.X, PV.W,
706 ; EG-NEXT: MOV T0.X, PV.X,
707 ; EG-NEXT: LSHR T1.W, T10.Z, literal.x,
708 ; EG-NEXT: LSHR * T2.W, T10.X, literal.x,
709 ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
710 ; EG-NEXT: LSHL T1.W, PS, PV.W,
711 ; EG-NEXT: AND_INT * T2.W, PV.X, literal.x,
712 ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
713 ; EG-NEXT: LSHL * T1.W, PV.W, literal.x,
714 ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
715 ; EG-NEXT: OR_INT * T1.W, T2.W, PV.W,
716 ; EG-NEXT: MOV T6.X, PV.W,
717 ; EG-NEXT: MOV * T0.X, T7.X,
718 ; EG-NEXT: AND_INT * T1.W, T10.W, literal.x,
719 ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
720 ; EG-NEXT: LSHL T1.W, T10.Y, PV.W,
721 ; EG-NEXT: AND_INT * T2.W, T0.X, literal.x,
722 ; EG-NEXT: -65536(nan), 0(0.000000e+00)
723 ; EG-NEXT: AND_INT * T1.W, PV.W, literal.x,
724 ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
725 ; EG-NEXT: OR_INT * T1.W, T2.W, PV.W,
726 ; EG-NEXT: MOV * T7.X, PV.W,
727 ; EG-NEXT: MOV T0.X, PV.X,
728 ; EG-NEXT: LSHR T1.W, T10.W, literal.x,
729 ; EG-NEXT: LSHR * T2.W, T10.Y, literal.x,
730 ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
731 ; EG-NEXT: LSHL * T1.W, PS, PV.W,
732 ; EG-NEXT: AND_INT T0.Z, T0.X, literal.x,
733 ; EG-NEXT: LSHL T1.W, PV.W, literal.y,
734 ; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W,
735 ; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)
736 ; EG-NEXT: LSHR T0.X, PS, literal.x,
737 ; EG-NEXT: OR_INT * T10.Y, PV.Z, PV.W,
738 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
739 ; EG-NEXT: MOV T7.X, PV.Y,
740 ; EG-NEXT: MOV * T10.X, T6.X,
741 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0
742 %gep = getelementptr inbounds <4 x i16>, ptr addrspace(1) %in, i32 %tid
743 %gep.out = getelementptr inbounds <4 x i16>, ptr addrspace(1) %out, i32 %tid
744 %b_ptr = getelementptr <4 x i16>, ptr addrspace(1) %gep, i16 1
745 %a = load <4 x i16>, ptr addrspace(1) %gep
746 %b = load <4 x i16>, ptr addrspace(1) %b_ptr
747 %result = shl <4 x i16> %a, %b
748 store <4 x i16> %result, ptr addrspace(1) %gep.out
749 ret void
750 }
752 define amdgpu_kernel void @shl_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {
753 ; SI-LABEL: shl_i64:
754 ; SI: ; %bb.0:
755 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
756 ; SI-NEXT: s_mov_b32 s7, 0xf000
757 ; SI-NEXT: s_mov_b32 s6, -1
758 ; SI-NEXT: s_mov_b32 s10, s6
759 ; SI-NEXT: s_mov_b32 s11, s7
760 ; SI-NEXT: s_waitcnt lgkmcnt(0)
761 ; SI-NEXT: s_mov_b32 s8, s2
762 ; SI-NEXT: s_mov_b32 s9, s3
763 ; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
764 ; SI-NEXT: s_mov_b32 s4, s0
765 ; SI-NEXT: s_mov_b32 s5, s1
766 ; SI-NEXT: s_waitcnt vmcnt(0)
767 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], v2
768 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
769 ; SI-NEXT: s_endpgm
770 ;
771 ; VI-LABEL: shl_i64:
772 ; VI: ; %bb.0:
773 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
774 ; VI-NEXT: s_waitcnt lgkmcnt(0)
775 ; VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
776 ; VI-NEXT: s_mov_b32 s3, 0xf000
777 ; VI-NEXT: s_mov_b32 s2, -1
778 ; VI-NEXT: s_waitcnt lgkmcnt(0)
779 ; VI-NEXT: s_lshl_b64 s[4:5], s[4:5], s6
780 ; VI-NEXT: v_mov_b32_e32 v0, s4
781 ; VI-NEXT: v_mov_b32_e32 v1, s5
782 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
783 ; VI-NEXT: s_endpgm
784 ;
785 ; EG-LABEL: shl_i64:
786 ; EG: ; %bb.0:
787 ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
788 ; EG-NEXT: TEX 0 @6
789 ; EG-NEXT: ALU 12, @9, KC0[CB0:0-32], KC1[]
790 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
791 ; EG-NEXT: CF_END
792 ; EG-NEXT: PAD
793 ; EG-NEXT: Fetch clause starting at 6:
794 ; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
795 ; EG-NEXT: ALU clause starting at 8:
796 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
797 ; EG-NEXT: ALU clause starting at 9:
798 ; EG-NEXT: AND_INT T1.Y, T0.Z, literal.x,
799 ; EG-NEXT: LSHR T1.Z, T0.Y, 1,
800 ; EG-NEXT: BIT_ALIGN_INT T0.W, T0.Y, T0.X, 1,
801 ; EG-NEXT: NOT_INT * T1.W, T0.Z,
802 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
803 ; EG-NEXT: BIT_ALIGN_INT T1.Z, PV.Z, PV.W, PS,
804 ; EG-NEXT: LSHL T0.W, T0.X, PV.Y,
805 ; EG-NEXT: AND_INT * T1.W, T0.Z, literal.x,
806 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
807 ; EG-NEXT: CNDE_INT * T0.Y, PS, PV.Z, PV.W,
808 ; EG-NEXT: CNDE_INT T0.X, T1.W, T0.W, 0.0,
809 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
810 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
811 %b_ptr = getelementptr i64, ptr addrspace(1) %in, i64 1
812 %a = load i64, ptr addrspace(1) %in
813 %b = load i64, ptr addrspace(1) %b_ptr
814 %result = shl i64 %a, %b
815 store i64 %result, ptr addrspace(1) %out
816 ret void
817 }
819 define amdgpu_kernel void @shl_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {
820 ; SI-LABEL: shl_v2i64:
821 ; SI: ; %bb.0:
822 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
823 ; SI-NEXT: s_mov_b32 s7, 0xf000
824 ; SI-NEXT: s_mov_b32 s6, -1
825 ; SI-NEXT: s_mov_b32 s10, s6
826 ; SI-NEXT: s_mov_b32 s11, s7
827 ; SI-NEXT: s_waitcnt lgkmcnt(0)
828 ; SI-NEXT: s_mov_b32 s8, s2
829 ; SI-NEXT: s_mov_b32 s9, s3
830 ; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
831 ; SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
832 ; SI-NEXT: s_mov_b32 s4, s0
833 ; SI-NEXT: s_mov_b32 s5, s1
834 ; SI-NEXT: s_waitcnt vmcnt(0)
835 ; SI-NEXT: v_lshl_b64 v[2:3], v[2:3], v6
836 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], v4
837 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
838 ; SI-NEXT: s_endpgm
839 ;
840 ; VI-LABEL: shl_v2i64:
841 ; VI: ; %bb.0:
842 ; VI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24
843 ; VI-NEXT: s_waitcnt lgkmcnt(0)
844 ; VI-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
845 ; VI-NEXT: s_mov_b32 s11, 0xf000
846 ; VI-NEXT: s_mov_b32 s10, -1
847 ; VI-NEXT: s_waitcnt lgkmcnt(0)
848 ; VI-NEXT: s_lshl_b64 s[2:3], s[2:3], s6
849 ; VI-NEXT: s_lshl_b64 s[0:1], s[0:1], s4
850 ; VI-NEXT: v_mov_b32_e32 v0, s0
851 ; VI-NEXT: v_mov_b32_e32 v1, s1
852 ; VI-NEXT: v_mov_b32_e32 v2, s2
853 ; VI-NEXT: v_mov_b32_e32 v3, s3
854 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
855 ; VI-NEXT: s_endpgm
856 ;
857 ; EG-LABEL: shl_v2i64:
858 ; EG: ; %bb.0:
859 ; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
860 ; EG-NEXT: TEX 1 @6
861 ; EG-NEXT: ALU 22, @11, KC0[CB0:0-32], KC1[]
862 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XYZW, T0.X, 1
863 ; EG-NEXT: CF_END
864 ; EG-NEXT: PAD
865 ; EG-NEXT: Fetch clause starting at 6:
866 ; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1
867 ; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
868 ; EG-NEXT: ALU clause starting at 10:
869 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
870 ; EG-NEXT: ALU clause starting at 11:
871 ; EG-NEXT: AND_INT T1.Y, T1.Z, literal.x,
872 ; EG-NEXT: LSHR T2.Z, T0.W, 1,
873 ; EG-NEXT: BIT_ALIGN_INT T0.W, T0.W, T0.Z, 1,
874 ; EG-NEXT: NOT_INT * T1.W, T1.Z,
875 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
876 ; EG-NEXT: BIT_ALIGN_INT T0.W, PV.Z, PV.W, PS,
877 ; EG-NEXT: LSHL * T1.W, T0.Z, PV.Y,
878 ; EG-NEXT: AND_INT T2.X, T1.Z, literal.x,
879 ; EG-NEXT: AND_INT T1.Y, T1.X, literal.y,
880 ; EG-NEXT: LSHR T0.Z, T0.Y, 1,
881 ; EG-NEXT: BIT_ALIGN_INT T2.W, T0.Y, T0.X, 1,
882 ; EG-NEXT: NOT_INT * T3.W, T1.X,
883 ; EG-NEXT: 32(4.484155e-44), 31(4.344025e-44)
884 ; EG-NEXT: BIT_ALIGN_INT T0.Y, PV.Z, PV.W, PS,
885 ; EG-NEXT: LSHL T0.Z, T0.X, PV.Y,
886 ; EG-NEXT: AND_INT T2.W, T1.X, literal.x, BS:VEC_120/SCL_212
887 ; EG-NEXT: CNDE_INT * T3.W, PV.X, T0.W, T1.W,
888 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
889 ; EG-NEXT: CNDE_INT T3.Y, PV.W, PV.Y, PV.Z,
890 ; EG-NEXT: CNDE_INT * T3.Z, T2.X, T1.W, 0.0,
891 ; EG-NEXT: CNDE_INT T3.X, T2.W, T0.Z, 0.0,
892 ; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
893 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
894 %b_ptr = getelementptr <2 x i64>, ptr addrspace(1) %in, i64 1
895 %a = load <2 x i64>, ptr addrspace(1) %in
896 %b = load <2 x i64>, ptr addrspace(1) %b_ptr
897 %result = shl <2 x i64> %a, %b
898 store <2 x i64> %result, ptr addrspace(1) %out
899 ret void
900 }
902 define amdgpu_kernel void @shl_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {
903 ; SI-LABEL: shl_v4i64:
904 ; SI: ; %bb.0:
905 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
906 ; SI-NEXT: s_mov_b32 s3, 0xf000
907 ; SI-NEXT: s_mov_b32 s2, -1
908 ; SI-NEXT: s_mov_b32 s10, s2
909 ; SI-NEXT: s_mov_b32 s11, s3
910 ; SI-NEXT: s_waitcnt lgkmcnt(0)
911 ; SI-NEXT: s_mov_b32 s8, s6
912 ; SI-NEXT: s_mov_b32 s9, s7
913 ; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
914 ; SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
915 ; SI-NEXT: buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:32
916 ; SI-NEXT: buffer_load_dwordx4 v[11:14], off, s[8:11], 0 offset:48
917 ; SI-NEXT: s_mov_b32 s0, s4
918 ; SI-NEXT: s_mov_b32 s1, s5
919 ; SI-NEXT: s_waitcnt vmcnt(1)
920 ; SI-NEXT: v_lshl_b64 v[2:3], v[2:3], v10
921 ; SI-NEXT: s_waitcnt vmcnt(0)
922 ; SI-NEXT: v_lshl_b64 v[6:7], v[6:7], v13
923 ; SI-NEXT: v_lshl_b64 v[4:5], v[4:5], v11
924 ; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], v8
925 ; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
926 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
927 ; SI-NEXT: s_endpgm
928 ;
929 ; VI-LABEL: shl_v4i64:
930 ; VI: ; %bb.0:
931 ; VI-NEXT: s_load_dwordx4 s[16:19], s[0:1], 0x24
932 ; VI-NEXT: s_waitcnt lgkmcnt(0)
933 ; VI-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
934 ; VI-NEXT: s_mov_b32 s19, 0xf000
935 ; VI-NEXT: s_mov_b32 s18, -1
936 ; VI-NEXT: s_waitcnt lgkmcnt(0)
937 ; VI-NEXT: s_lshl_b64 s[6:7], s[6:7], s14
938 ; VI-NEXT: s_lshl_b64 s[4:5], s[4:5], s12
939 ; VI-NEXT: s_lshl_b64 s[2:3], s[2:3], s10
940 ; VI-NEXT: s_lshl_b64 s[0:1], s[0:1], s8
941 ; VI-NEXT: v_mov_b32_e32 v0, s4
942 ; VI-NEXT: v_mov_b32_e32 v1, s5
943 ; VI-NEXT: v_mov_b32_e32 v2, s6
944 ; VI-NEXT: v_mov_b32_e32 v3, s7
945 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:16
946 ; VI-NEXT: s_nop 0
947 ; VI-NEXT: v_mov_b32_e32 v0, s0
948 ; VI-NEXT: v_mov_b32_e32 v1, s1
949 ; VI-NEXT: v_mov_b32_e32 v2, s2
950 ; VI-NEXT: v_mov_b32_e32 v3, s3
951 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0
952 ; VI-NEXT: s_endpgm
953 ;
954 ; EG-LABEL: shl_v4i64:
955 ; EG: ; %bb.0:
956 ; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[]
957 ; EG-NEXT: TEX 3 @6
958 ; EG-NEXT: ALU 47, @15, KC0[CB0:0-32], KC1[]
959 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T2.X, 0
960 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T0.X, 1
961 ; EG-NEXT: CF_END
962 ; EG-NEXT: Fetch clause starting at 6:
963 ; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 48, #1
964 ; EG-NEXT: VTX_READ_128 T2.XYZW, T0.X, 0, #1
965 ; EG-NEXT: VTX_READ_128 T3.XYZW, T0.X, 32, #1
966 ; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 16, #1
967 ; EG-NEXT: ALU clause starting at 14:
968 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
969 ; EG-NEXT: ALU clause starting at 15:
970 ; EG-NEXT: AND_INT T4.Z, T1.Z, literal.x,
971 ; EG-NEXT: LSHR T1.W, T0.W, 1,
972 ; EG-NEXT: NOT_INT * T3.W, T1.Z,
973 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
974 ; EG-NEXT: BIT_ALIGN_INT T4.X, T0.W, T0.Z, 1,
975 ; EG-NEXT: AND_INT T1.Y, T3.Z, literal.x, BS:VEC_201
976 ; EG-NEXT: LSHR T5.Z, T2.W, 1, BS:VEC_120/SCL_212
977 ; EG-NEXT: BIT_ALIGN_INT T0.W, T2.W, T2.Z, 1, BS:VEC_102/SCL_221
978 ; EG-NEXT: NOT_INT * T2.W, T3.Z,
979 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
980 ; EG-NEXT: BIT_ALIGN_INT T3.Y, PV.Z, PV.W, PS,
981 ; EG-NEXT: LSHL T2.Z, T2.Z, PV.Y,
982 ; EG-NEXT: BIT_ALIGN_INT T0.W, T1.W, PV.X, T3.W,
983 ; EG-NEXT: LSHL * T1.W, T0.Z, T4.Z,
984 ; EG-NEXT: AND_INT T4.X, T1.Z, literal.x,
985 ; EG-NEXT: AND_INT T1.Y, T1.X, literal.y,
986 ; EG-NEXT: LSHR T0.Z, T0.Y, 1,
987 ; EG-NEXT: BIT_ALIGN_INT T2.W, T0.Y, T0.X, 1,
988 ; EG-NEXT: NOT_INT * T3.W, T1.X,
989 ; EG-NEXT: 32(4.484155e-44), 31(4.344025e-44)
990 ; EG-NEXT: AND_INT T5.X, T3.Z, literal.x,
991 ; EG-NEXT: BIT_ALIGN_INT T0.Y, PV.Z, PV.W, PS,
992 ; EG-NEXT: LSHL T0.Z, T0.X, PV.Y,
993 ; EG-NEXT: AND_INT T2.W, T1.X, literal.x, BS:VEC_120/SCL_212
994 ; EG-NEXT: CNDE_INT * T4.W, PV.X, T0.W, T1.W,
995 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
996 ; EG-NEXT: AND_INT T0.X, T3.X, literal.x,
997 ; EG-NEXT: CNDE_INT T4.Y, PV.W, PV.Y, PV.Z,
998 ; EG-NEXT: LSHR T1.Z, T2.Y, 1,
999 ; EG-NEXT: BIT_ALIGN_INT T0.W, T2.Y, T2.X, 1,
1000 ; EG-NEXT: NOT_INT * T3.W, T3.X,
1001 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
1002 ; EG-NEXT: BIT_ALIGN_INT T1.X, PV.Z, PV.W, PS,
1003 ; EG-NEXT: LSHL T0.Y, T2.X, PV.X,
1004 ; EG-NEXT: CNDE_INT T4.Z, T4.X, T1.W, 0.0, BS:VEC_120/SCL_212
1005 ; EG-NEXT: AND_INT * T0.W, T3.X, literal.x, BS:VEC_201
1006 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
1007 ; EG-NEXT: CNDE_INT * T1.W, T5.X, T3.Y, T2.Z,
1008 ; EG-NEXT: CNDE_INT T4.X, T2.W, T0.Z, 0.0,
1009 ; EG-NEXT: CNDE_INT T1.Y, T0.W, T1.X, T0.Y, BS:VEC_120/SCL_212
1010 ; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x,
1011 ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
1012 ; EG-NEXT: LSHR T0.X, PV.W, literal.x,
1013 ; EG-NEXT: CNDE_INT T1.Z, T5.X, T2.Z, 0.0,
1014 ; EG-NEXT: CNDE_INT * T1.X, T0.W, T0.Y, 0.0,
1015 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
1016 ; EG-NEXT: LSHR * T2.X, KC0[2].Y, literal.x,
1017 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
1018 %b_ptr = getelementptr <4 x i64>, ptr addrspace(1) %in, i64 1
1019 %a = load <4 x i64>, ptr addrspace(1) %in
1020 %b = load <4 x i64>, ptr addrspace(1) %b_ptr
1021 %result = shl <4 x i64> %a, %b
1022 store <4 x i64> %result, ptr addrspace(1) %out
1023 ret void
1024 }
1026 ; Make sure load width gets reduced to i32 load.
1027 define amdgpu_kernel void @s_shl_32_i64(ptr addrspace(1) %out, [8 x i32], i64 %a) {
1028 ; SI-LABEL: s_shl_32_i64:
1029 ; SI: ; %bb.0:
1030 ; SI-NEXT: s_load_dword s4, s[0:1], 0x13
1031 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
1032 ; SI-NEXT: s_mov_b32 s3, 0xf000
1033 ; SI-NEXT: s_mov_b32 s2, -1
1034 ; SI-NEXT: v_mov_b32_e32 v0, 0
1035 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1036 ; SI-NEXT: v_mov_b32_e32 v1, s4
1037 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1038 ; SI-NEXT: s_endpgm
1039 ;
1040 ; VI-LABEL: s_shl_32_i64:
1041 ; VI: ; %bb.0:
1042 ; VI-NEXT: s_load_dword s4, s[0:1], 0x4c
1043 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1044 ; VI-NEXT: s_mov_b32 s3, 0xf000
1045 ; VI-NEXT: s_mov_b32 s2, -1
1046 ; VI-NEXT: v_mov_b32_e32 v0, 0
1047 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1048 ; VI-NEXT: v_mov_b32_e32 v1, s4
1049 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1050 ; VI-NEXT: s_endpgm
1051 ;
1052 ; EG-LABEL: s_shl_32_i64:
1053 ; EG: ; %bb.0:
1054 ; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
1055 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
1056 ; EG-NEXT: CF_END
1057 ; EG-NEXT: PAD
1058 ; EG-NEXT: ALU clause starting at 4:
1059 ; EG-NEXT: MOV * T0.Y, KC0[4].W,
1060 ; EG-NEXT: MOV T0.X, 0.0,
1061 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
1062 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
1063 %result = shl i64 %a, 32
1064 store i64 %result, ptr addrspace(1) %out
1065 ret void
1066 }
1068 define amdgpu_kernel void @v_shl_32_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {
1069 ; SI-LABEL: v_shl_32_i64:
1070 ; SI: ; %bb.0:
1071 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
1072 ; SI-NEXT: s_ashr_i32 s3, s2, 31
1073 ; SI-NEXT: s_lshl_b64 s[0:1], s[2:3], 3
1074 ; SI-NEXT: v_mov_b32_e32 v0, s0
1075 ; SI-NEXT: s_mov_b32 s11, 0xf000
1076 ; SI-NEXT: s_mov_b32 s10, 0
1077 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1078 ; SI-NEXT: s_mov_b64 s[8:9], s[6:7]
1079 ; SI-NEXT: v_mov_b32_e32 v1, s1
1080 ; SI-NEXT: buffer_load_dword v3, v[0:1], s[8:11], 0 addr64
1081 ; SI-NEXT: s_mov_b64 s[6:7], s[10:11]
1082 ; SI-NEXT: v_mov_b32_e32 v2, 0
1083 ; SI-NEXT: s_waitcnt vmcnt(0)
1084 ; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
1085 ; SI-NEXT: s_endpgm
1086 ;
1087 ; VI-LABEL: v_shl_32_i64:
1088 ; VI: ; %bb.0:
1089 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
1090 ; VI-NEXT: s_ashr_i32 s3, s2, 31
1091 ; VI-NEXT: s_lshl_b64 s[0:1], s[2:3], 3
1092 ; VI-NEXT: v_mov_b32_e32 v0, 0
1093 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1094 ; VI-NEXT: s_add_u32 s2, s6, s0
1095 ; VI-NEXT: s_addc_u32 s3, s7, s1
1096 ; VI-NEXT: s_load_dword s2, s[2:3], 0x0
1097 ; VI-NEXT: s_add_u32 s0, s4, s0
1098 ; VI-NEXT: s_addc_u32 s1, s5, s1
1099 ; VI-NEXT: v_mov_b32_e32 v3, s1
1100 ; VI-NEXT: v_mov_b32_e32 v2, s0
1101 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1102 ; VI-NEXT: v_mov_b32_e32 v1, s2
1103 ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
1104 ; VI-NEXT: s_endpgm
1105 ;
1106 ; EG-LABEL: v_shl_32_i64:
1107 ; EG: ; %bb.0:
1108 ; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]
1109 ; EG-NEXT: TEX 0 @6
1110 ; EG-NEXT: ALU 4, @11, KC0[CB0:0-32], KC1[]
1111 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XY, T2.X, 1
1112 ; EG-NEXT: CF_END
1113 ; EG-NEXT: PAD
1114 ; EG-NEXT: Fetch clause starting at 6:
1115 ; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
1116 ; EG-NEXT: ALU clause starting at 8:
1117 ; EG-NEXT: LSHL * T0.W, T1.X, literal.x,
1118 ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
1119 ; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,
1120 ; EG-NEXT: ALU clause starting at 11:
1121 ; EG-NEXT: MOV T1.X, 0.0,
1122 ; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W,
1123 ; EG-NEXT: LSHR T2.X, PV.W, literal.x,
1124 ; EG-NEXT: MOV * T1.Y, T0.X,
1125 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
1126 %tid = call i32 @llvm.amdgcn.workgroup.id.x() #0
1127 %gep.in = getelementptr i64, ptr addrspace(1) %in, i32 %tid
1128 %gep.out = getelementptr i64, ptr addrspace(1) %out, i32 %tid
1129 %a = load i64, ptr addrspace(1) %gep.in
1130 %result = shl i64 %a, 32
1131 store i64 %result, ptr addrspace(1) %gep.out
1132 ret void
1133 }
1135 define amdgpu_kernel void @s_shl_constant_i64(ptr addrspace(1) %out, i64 %a) {
1136 ; SI-LABEL: s_shl_constant_i64:
1137 ; SI: ; %bb.0:
1138 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
1139 ; SI-NEXT: s_mov_b32 s6, -1
1140 ; SI-NEXT: s_mov_b32 s9, 0xffff
1141 ; SI-NEXT: s_mov_b32 s8, s6
1142 ; SI-NEXT: s_mov_b32 s7, 0xf000
1143 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1144 ; SI-NEXT: s_mov_b32 s4, s0
1145 ; SI-NEXT: s_mov_b32 s5, s1
1146 ; SI-NEXT: s_lshl_b64 s[0:1], s[8:9], s2
1147 ; SI-NEXT: v_mov_b32_e32 v0, s0
1148 ; SI-NEXT: v_mov_b32_e32 v1, s1
1149 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1150 ; SI-NEXT: s_endpgm
1151 ;
1152 ; VI-LABEL: s_shl_constant_i64:
1153 ; VI: ; %bb.0:
1154 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1155 ; VI-NEXT: s_mov_b32 s6, -1
1156 ; VI-NEXT: s_mov_b32 s9, 0xffff
1157 ; VI-NEXT: s_mov_b32 s8, s6
1158 ; VI-NEXT: s_mov_b32 s7, 0xf000
1159 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1160 ; VI-NEXT: s_mov_b32 s4, s0
1161 ; VI-NEXT: s_mov_b32 s5, s1
1162 ; VI-NEXT: s_lshl_b64 s[0:1], s[8:9], s2
1163 ; VI-NEXT: v_mov_b32_e32 v0, s0
1164 ; VI-NEXT: v_mov_b32_e32 v1, s1
1165 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1166 ; VI-NEXT: s_endpgm
1167 ;
1168 ; EG-LABEL: s_shl_constant_i64:
1169 ; EG: ; %bb.0:
1170 ; EG-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[]
1171 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
1172 ; EG-NEXT: CF_END
1173 ; EG-NEXT: PAD
1174 ; EG-NEXT: ALU clause starting at 4:
1175 ; EG-NEXT: AND_INT T0.Z, KC0[2].W, literal.x,
1176 ; EG-NEXT: MOV T0.W, literal.y,
1177 ; EG-NEXT: NOT_INT * T1.W, KC0[2].W,
1178 ; EG-NEXT: 31(4.344025e-44), -1(nan)
1179 ; EG-NEXT: BIT_ALIGN_INT T1.Z, literal.x, PV.W, PS,
1180 ; EG-NEXT: LSHL T0.W, literal.y, PV.Z,
1181 ; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.z,
1182 ; EG-NEXT: 32767(4.591635e-41), -1(nan)
1183 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
1184 ; EG-NEXT: CNDE_INT * T0.Y, PS, PV.Z, PV.W,
1185 ; EG-NEXT: CNDE_INT T0.X, T1.W, T0.W, 0.0,
1186 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
1187 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
1188 %shl = shl i64 281474976710655, %a
1189 store i64 %shl, ptr addrspace(1) %out, align 8
1190 ret void
1191 }
1193 define amdgpu_kernel void @v_shl_constant_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr) {
1194 ; SI-LABEL: v_shl_constant_i64:
1195 ; SI: ; %bb.0:
1196 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
1197 ; SI-NEXT: s_mov_b32 s7, 0xf000
1198 ; SI-NEXT: s_mov_b32 s6, -1
1199 ; SI-NEXT: s_mov_b32 s10, s6
1200 ; SI-NEXT: s_mov_b32 s11, s7
1201 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1202 ; SI-NEXT: s_mov_b32 s8, s2
1203 ; SI-NEXT: s_mov_b32 s9, s3
1204 ; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0
1205 ; SI-NEXT: s_mov_b32 s2, 0xab19b207
1206 ; SI-NEXT: s_movk_i32 s3, 0x11e
1207 ; SI-NEXT: s_mov_b32 s4, s0
1208 ; SI-NEXT: s_mov_b32 s5, s1
1209 ; SI-NEXT: s_waitcnt vmcnt(0)
1210 ; SI-NEXT: v_lshl_b64 v[0:1], s[2:3], v0
1211 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1212 ; SI-NEXT: s_endpgm
1213 ;
1214 ; VI-LABEL: v_shl_constant_i64:
1215 ; VI: ; %bb.0:
1216 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1217 ; VI-NEXT: s_mov_b32 s7, 0xf000
1218 ; VI-NEXT: s_mov_b32 s6, -1
1219 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1220 ; VI-NEXT: s_load_dword s2, s[2:3], 0x0
1221 ; VI-NEXT: s_mov_b32 s4, s0
1222 ; VI-NEXT: s_mov_b32 s5, s1
1223 ; VI-NEXT: s_mov_b32 s0, 0xab19b207
1224 ; VI-NEXT: s_movk_i32 s1, 0x11e
1225 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1226 ; VI-NEXT: s_lshl_b64 s[0:1], s[0:1], s2
1227 ; VI-NEXT: v_mov_b32_e32 v0, s0
1228 ; VI-NEXT: v_mov_b32_e32 v1, s1
1229 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1230 ; VI-NEXT: s_endpgm
1231 ;
1232 ; EG-LABEL: v_shl_constant_i64:
1233 ; EG: ; %bb.0:
1234 ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
1235 ; EG-NEXT: TEX 0 @6
1236 ; EG-NEXT: ALU 12, @9, KC0[CB0:0-32], KC1[]
1237 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
1238 ; EG-NEXT: CF_END
1239 ; EG-NEXT: PAD
1240 ; EG-NEXT: Fetch clause starting at 6:
1241 ; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
1242 ; EG-NEXT: ALU clause starting at 8:
1243 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
1244 ; EG-NEXT: ALU clause starting at 9:
1245 ; EG-NEXT: NOT_INT T0.Z, T0.X,
1246 ; EG-NEXT: MOV T0.W, literal.x,
1247 ; EG-NEXT: AND_INT * T1.W, T0.X, literal.y,
1248 ; EG-NEXT: 1435293955(1.935796e+13), 31(4.344025e-44)
1249 ; EG-NEXT: LSHL T1.Z, literal.x, PS,
1250 ; EG-NEXT: BIT_ALIGN_INT T0.W, literal.y, PV.W, PV.Z,
1251 ; EG-NEXT: AND_INT * T1.W, T0.X, literal.z,
1252 ; EG-NEXT: -1424379385(-5.460358e-13), 143(2.003857e-43)
1253 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
1254 ; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, PV.Z,
1255 ; EG-NEXT: CNDE_INT T0.X, T1.W, T1.Z, 0.0,
1256 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
1257 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
1258 %a = load i64, ptr addrspace(1) %aptr, align 8
1259 %shl = shl i64 1231231234567, %a
1260 store i64 %shl, ptr addrspace(1) %out, align 8
1261 ret void
1262 }
1264 define amdgpu_kernel void @v_shl_i64_32_bit_constant(ptr addrspace(1) %out, ptr addrspace(1) %aptr) {
1265 ; SI-LABEL: v_shl_i64_32_bit_constant:
1266 ; SI: ; %bb.0:
1267 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
1268 ; SI-NEXT: s_mov_b32 s7, 0xf000
1269 ; SI-NEXT: s_mov_b32 s6, -1
1270 ; SI-NEXT: s_mov_b32 s10, s6
1271 ; SI-NEXT: s_mov_b32 s11, s7
1272 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1273 ; SI-NEXT: s_mov_b32 s8, s2
1274 ; SI-NEXT: s_mov_b32 s9, s3
1275 ; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0
1276 ; SI-NEXT: s_mov_b64 s[2:3], 0x12d687
1277 ; SI-NEXT: s_mov_b32 s4, s0
1278 ; SI-NEXT: s_mov_b32 s5, s1
1279 ; SI-NEXT: s_waitcnt vmcnt(0)
1280 ; SI-NEXT: v_lshl_b64 v[0:1], s[2:3], v0
1281 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1282 ; SI-NEXT: s_endpgm
1283 ;
1284 ; VI-LABEL: v_shl_i64_32_bit_constant:
1285 ; VI: ; %bb.0:
1286 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1287 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1288 ; VI-NEXT: s_load_dword s4, s[2:3], 0x0
1289 ; VI-NEXT: s_mov_b32 s3, 0xf000
1290 ; VI-NEXT: s_mov_b32 s2, -1
1291 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1292 ; VI-NEXT: s_lshl_b64 s[4:5], 0x12d687, s4
1293 ; VI-NEXT: v_mov_b32_e32 v0, s4
1294 ; VI-NEXT: v_mov_b32_e32 v1, s5
1295 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1296 ; VI-NEXT: s_endpgm
1297 ;
1298 ; EG-LABEL: v_shl_i64_32_bit_constant:
1299 ; EG: ; %bb.0:
1300 ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
1301 ; EG-NEXT: TEX 0 @6
1302 ; EG-NEXT: ALU 11, @9, KC0[CB0:0-32], KC1[]
1303 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
1304 ; EG-NEXT: CF_END
1305 ; EG-NEXT: PAD
1306 ; EG-NEXT: Fetch clause starting at 6:
1307 ; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
1308 ; EG-NEXT: ALU clause starting at 8:
1309 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
1310 ; EG-NEXT: ALU clause starting at 9:
1311 ; EG-NEXT: AND_INT T0.W, T0.X, literal.x,
1312 ; EG-NEXT: NOT_INT * T1.W, T0.X,
1313 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
1314 ; EG-NEXT: BIT_ALIGN_INT T0.Z, 0.0, literal.x, PS,
1315 ; EG-NEXT: LSHL T0.W, literal.y, PV.W,
1316 ; EG-NEXT: AND_INT * T1.W, T0.X, literal.z,
1317 ; EG-NEXT: 617283(8.649977e-40), 1234567(1.729997e-39)
1318 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
1319 ; EG-NEXT: CNDE_INT * T0.Y, PS, PV.Z, PV.W,
1320 ; EG-NEXT: CNDE_INT T0.X, T1.W, T0.W, 0.0,
1321 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
1322 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
1323 %a = load i64, ptr addrspace(1) %aptr, align 8
1324 %shl = shl i64 1234567, %a
1325 store i64 %shl, ptr addrspace(1) %out, align 8
1326 ret void
1327 }
1329 define amdgpu_kernel void @v_shl_inline_imm_64_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr) {
1330 ; SI-LABEL: v_shl_inline_imm_64_i64:
1331 ; SI: ; %bb.0:
1332 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
1333 ; SI-NEXT: s_mov_b32 s7, 0xf000
1334 ; SI-NEXT: s_mov_b32 s6, -1
1335 ; SI-NEXT: s_mov_b32 s10, s6
1336 ; SI-NEXT: s_mov_b32 s11, s7
1337 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1338 ; SI-NEXT: s_mov_b32 s8, s2
1339 ; SI-NEXT: s_mov_b32 s9, s3
1340 ; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0
1341 ; SI-NEXT: s_mov_b32 s4, s0
1342 ; SI-NEXT: s_mov_b32 s5, s1
1343 ; SI-NEXT: s_waitcnt vmcnt(0)
1344 ; SI-NEXT: v_lshl_b64 v[0:1], 64, v0
1345 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1346 ; SI-NEXT: s_endpgm
1347 ;
1348 ; VI-LABEL: v_shl_inline_imm_64_i64:
1349 ; VI: ; %bb.0:
1350 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
1351 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1352 ; VI-NEXT: s_load_dword s4, s[2:3], 0x0
1353 ; VI-NEXT: s_mov_b32 s3, 0xf000
1354 ; VI-NEXT: s_mov_b32 s2, -1
1355 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1356 ; VI-NEXT: s_lshl_b64 s[4:5], 64, s4
1357 ; VI-NEXT: v_mov_b32_e32 v0, s4
1358 ; VI-NEXT: v_mov_b32_e32 v1, s5
1359 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1360 ; VI-NEXT: s_endpgm
1361 ;
1362 ; EG-LABEL: v_shl_inline_imm_64_i64:
1363 ; EG: ; %bb.0:
1364 ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
1365 ; EG-NEXT: TEX 0 @6
1366 ; EG-NEXT: ALU 10, @9, KC0[CB0:0-32], KC1[]
1367 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
1368 ; EG-NEXT: CF_END
1369 ; EG-NEXT: PAD
1370 ; EG-NEXT: Fetch clause starting at 6:
1371 ; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
1372 ; EG-NEXT: ALU clause starting at 8:
1373 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
1374 ; EG-NEXT: ALU clause starting at 9:
1375 ; EG-NEXT: AND_INT T0.W, T0.X, literal.x,
1376 ; EG-NEXT: NOT_INT * T1.W, T0.X,
1377 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
1378 ; EG-NEXT: BIT_ALIGN_INT T0.Z, 0.0, literal.x, PS,
1379 ; EG-NEXT: LSHL T0.W, literal.y, PV.W,
1380 ; EG-NEXT: AND_INT * T1.W, T0.X, literal.x,
1381 ; EG-NEXT: 32(4.484155e-44), 64(8.968310e-44)
1382 ; EG-NEXT: CNDE_INT * T0.Y, PS, PV.Z, PV.W,
1383 ; EG-NEXT: CNDE_INT T0.X, T1.W, T0.W, 0.0,
1384 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
1385 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
1386 %a = load i64, ptr addrspace(1) %aptr, align 8
1387 %shl = shl i64 64, %a
1388 store i64 %shl, ptr addrspace(1) %out, align 8
1389 ret void
1390 }
1392 define amdgpu_kernel void @s_shl_inline_imm_64_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {
1393 ; SI-LABEL: s_shl_inline_imm_64_i64:
1394 ; SI: ; %bb.0:
1395 ; SI-NEXT: s_load_dword s4, s[0:1], 0xd
1396 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
1397 ; SI-NEXT: s_mov_b32 s3, 0xf000
1398 ; SI-NEXT: s_mov_b32 s2, -1
1399 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1400 ; SI-NEXT: s_lshl_b64 s[4:5], 64, s4
1401 ; SI-NEXT: v_mov_b32_e32 v0, s4
1402 ; SI-NEXT: v_mov_b32_e32 v1, s5
1403 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1404 ; SI-NEXT: s_endpgm
1405 ;
1406 ; VI-LABEL: s_shl_inline_imm_64_i64:
1407 ; VI: ; %bb.0:
1408 ; VI-NEXT: s_load_dword s4, s[0:1], 0x34
1409 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1410 ; VI-NEXT: s_mov_b32 s3, 0xf000
1411 ; VI-NEXT: s_mov_b32 s2, -1
1412 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1413 ; VI-NEXT: s_lshl_b64 s[4:5], 64, s4
1414 ; VI-NEXT: v_mov_b32_e32 v0, s4
1415 ; VI-NEXT: v_mov_b32_e32 v1, s5
1416 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1417 ; VI-NEXT: s_endpgm
1418 ;
1419 ; EG-LABEL: s_shl_inline_imm_64_i64:
1420 ; EG: ; %bb.0:
1421 ; EG-NEXT: ALU 10, @4, KC0[CB0:0-32], KC1[]
1422 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
1423 ; EG-NEXT: CF_END
1424 ; EG-NEXT: PAD
1425 ; EG-NEXT: ALU clause starting at 4:
1426 ; EG-NEXT: NOT_INT T0.W, KC0[2].W,
1427 ; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.x,
1428 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
1429 ; EG-NEXT: LSHL T0.Z, literal.x, PS,
1430 ; EG-NEXT: BIT_ALIGN_INT T0.W, 0.0, literal.y, PV.W,
1431 ; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y,
1432 ; EG-NEXT: 64(8.968310e-44), 32(4.484155e-44)
1433 ; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, PV.Z,
1434 ; EG-NEXT: CNDE_INT T0.X, T1.W, T0.Z, 0.0,
1435 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
1436 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
1437 %shl = shl i64 64, %a
1438 store i64 %shl, ptr addrspace(1) %out, align 8
1439 ret void
1440 }
1442 define amdgpu_kernel void @s_shl_inline_imm_1_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {
1443 ; SI-LABEL: s_shl_inline_imm_1_i64:
1444 ; SI: ; %bb.0:
1445 ; SI-NEXT: s_load_dword s4, s[0:1], 0xd
1446 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
1447 ; SI-NEXT: s_mov_b32 s3, 0xf000
1448 ; SI-NEXT: s_mov_b32 s2, -1
1449 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1450 ; SI-NEXT: s_lshl_b64 s[4:5], 1, s4
1451 ; SI-NEXT: v_mov_b32_e32 v0, s4
1452 ; SI-NEXT: v_mov_b32_e32 v1, s5
1453 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1454 ; SI-NEXT: s_endpgm
1455 ;
1456 ; VI-LABEL: s_shl_inline_imm_1_i64:
1457 ; VI: ; %bb.0:
1458 ; VI-NEXT: s_load_dword s4, s[0:1], 0x34
1459 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1460 ; VI-NEXT: s_mov_b32 s3, 0xf000
1461 ; VI-NEXT: s_mov_b32 s2, -1
1462 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1463 ; VI-NEXT: s_lshl_b64 s[4:5], 1, s4
1464 ; VI-NEXT: v_mov_b32_e32 v0, s4
1465 ; VI-NEXT: v_mov_b32_e32 v1, s5
1466 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1467 ; VI-NEXT: s_endpgm
1468 ;
1469 ; EG-LABEL: s_shl_inline_imm_1_i64:
1470 ; EG: ; %bb.0:
1471 ; EG-NEXT: ALU 11, @4, KC0[CB0:0-32], KC1[]
1472 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
1473 ; EG-NEXT: CF_END
1474 ; EG-NEXT: PAD
1475 ; EG-NEXT: ALU clause starting at 4:
1476 ; EG-NEXT: AND_INT T0.W, KC0[2].W, literal.x,
1477 ; EG-NEXT: LSHL * T1.W, KC0[2].W, literal.y,
1478 ; EG-NEXT: 31(4.344025e-44), 26(3.643376e-44)
1479 ; EG-NEXT: ASHR T1.W, PS, literal.x,
1480 ; EG-NEXT: LSHL * T0.W, 1, PV.W,
1481 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
1482 ; EG-NEXT: AND_INT T0.Y, PV.W, PS,
1483 ; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.x,
1484 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
1485 ; EG-NEXT: CNDE_INT T0.X, PV.W, T0.W, 0.0,
1486 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
1487 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
1488 %shl = shl i64 1, %a
1489 store i64 %shl, ptr addrspace(1) %out, align 8
1490 ret void
1491 }
1493 define amdgpu_kernel void @s_shl_inline_imm_1_0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {
1494 ; SI-LABEL: s_shl_inline_imm_1_0_i64:
1495 ; SI: ; %bb.0:
1496 ; SI-NEXT: s_load_dword s4, s[0:1], 0xd
1497 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
1498 ; SI-NEXT: s_mov_b32 s3, 0xf000
1499 ; SI-NEXT: s_mov_b32 s2, -1
1500 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1501 ; SI-NEXT: s_lshl_b64 s[4:5], 1.0, s4
1502 ; SI-NEXT: v_mov_b32_e32 v0, s4
1503 ; SI-NEXT: v_mov_b32_e32 v1, s5
1504 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1505 ; SI-NEXT: s_endpgm
1506 ;
1507 ; VI-LABEL: s_shl_inline_imm_1_0_i64:
1508 ; VI: ; %bb.0:
1509 ; VI-NEXT: s_load_dword s4, s[0:1], 0x34
1510 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1511 ; VI-NEXT: s_mov_b32 s3, 0xf000
1512 ; VI-NEXT: s_mov_b32 s2, -1
1513 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1514 ; VI-NEXT: s_lshl_b64 s[4:5], 1.0, s4
1515 ; VI-NEXT: v_mov_b32_e32 v0, s4
1516 ; VI-NEXT: v_mov_b32_e32 v1, s5
1517 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1518 ; VI-NEXT: s_endpgm
1519 ;
1520 ; EG-LABEL: s_shl_inline_imm_1_0_i64:
1521 ; EG: ; %bb.0:
1522 ; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]
1523 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
1524 ; EG-NEXT: CF_END
1525 ; EG-NEXT: PAD
1526 ; EG-NEXT: ALU clause starting at 4:
1527 ; EG-NEXT: NOT_INT * T0.W, KC0[2].W,
1528 ; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,
1529 ; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y,
1530 ; EG-NEXT: 536346624(1.050321e-19), 32(4.484155e-44)
1531 ; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0,
1532 ; EG-NEXT: MOV T0.X, 0.0,
1533 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
1534 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
1535 %shl = shl i64 4607182418800017408, %a
1536 store i64 %shl, ptr addrspace(1) %out, align 8
1537 ret void
1538 }
1540 define amdgpu_kernel void @s_shl_inline_imm_neg_1_0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {
1541 ; SI-LABEL: s_shl_inline_imm_neg_1_0_i64:
1542 ; SI: ; %bb.0:
1543 ; SI-NEXT: s_load_dword s4, s[0:1], 0xd
1544 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
1545 ; SI-NEXT: s_mov_b32 s3, 0xf000
1546 ; SI-NEXT: s_mov_b32 s2, -1
1547 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1548 ; SI-NEXT: s_lshl_b64 s[4:5], -1.0, s4
1549 ; SI-NEXT: v_mov_b32_e32 v0, s4
1550 ; SI-NEXT: v_mov_b32_e32 v1, s5
1551 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1552 ; SI-NEXT: s_endpgm
1553 ;
1554 ; VI-LABEL: s_shl_inline_imm_neg_1_0_i64:
1555 ; VI: ; %bb.0:
1556 ; VI-NEXT: s_load_dword s4, s[0:1], 0x34
1557 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1558 ; VI-NEXT: s_mov_b32 s3, 0xf000
1559 ; VI-NEXT: s_mov_b32 s2, -1
1560 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1561 ; VI-NEXT: s_lshl_b64 s[4:5], -1.0, s4
1562 ; VI-NEXT: v_mov_b32_e32 v0, s4
1563 ; VI-NEXT: v_mov_b32_e32 v1, s5
1564 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1565 ; VI-NEXT: s_endpgm
1566 ;
1567 ; EG-LABEL: s_shl_inline_imm_neg_1_0_i64:
1568 ; EG: ; %bb.0:
1569 ; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]
1570 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
1571 ; EG-NEXT: CF_END
1572 ; EG-NEXT: PAD
1573 ; EG-NEXT: ALU clause starting at 4:
1574 ; EG-NEXT: NOT_INT * T0.W, KC0[2].W,
1575 ; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,
1576 ; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y,
1577 ; EG-NEXT: 1610088448(3.574057e+19), 32(4.484155e-44)
1578 ; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0,
1579 ; EG-NEXT: MOV T0.X, 0.0,
1580 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
1581 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
1582 %shl = shl i64 13830554455654793216, %a
1583 store i64 %shl, ptr addrspace(1) %out, align 8
1584 ret void
1585 }
1587 define amdgpu_kernel void @s_shl_inline_imm_0_5_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {
1588 ; SI-LABEL: s_shl_inline_imm_0_5_i64:
1589 ; SI: ; %bb.0:
1590 ; SI-NEXT: s_load_dword s4, s[0:1], 0xd
1591 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
1592 ; SI-NEXT: s_mov_b32 s3, 0xf000
1593 ; SI-NEXT: s_mov_b32 s2, -1
1594 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1595 ; SI-NEXT: s_lshl_b64 s[4:5], 0.5, s4
1596 ; SI-NEXT: v_mov_b32_e32 v0, s4
1597 ; SI-NEXT: v_mov_b32_e32 v1, s5
1598 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1599 ; SI-NEXT: s_endpgm
1600 ;
1601 ; VI-LABEL: s_shl_inline_imm_0_5_i64:
1602 ; VI: ; %bb.0:
1603 ; VI-NEXT: s_load_dword s4, s[0:1], 0x34
1604 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1605 ; VI-NEXT: s_mov_b32 s3, 0xf000
1606 ; VI-NEXT: s_mov_b32 s2, -1
1607 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1608 ; VI-NEXT: s_lshl_b64 s[4:5], 0.5, s4
1609 ; VI-NEXT: v_mov_b32_e32 v0, s4
1610 ; VI-NEXT: v_mov_b32_e32 v1, s5
1611 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1612 ; VI-NEXT: s_endpgm
1613 ;
1614 ; EG-LABEL: s_shl_inline_imm_0_5_i64:
1615 ; EG: ; %bb.0:
1616 ; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]
1617 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
1618 ; EG-NEXT: CF_END
1619 ; EG-NEXT: PAD
1620 ; EG-NEXT: ALU clause starting at 4:
1621 ; EG-NEXT: NOT_INT * T0.W, KC0[2].W,
1622 ; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,
1623 ; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y,
1624 ; EG-NEXT: 535822336(1.016440e-19), 32(4.484155e-44)
1625 ; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0,
1626 ; EG-NEXT: MOV T0.X, 0.0,
1627 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
1628 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
1629 %shl = shl i64 4602678819172646912, %a
1630 store i64 %shl, ptr addrspace(1) %out, align 8
1631 ret void
1632 }
1634 define amdgpu_kernel void @s_shl_inline_imm_neg_0_5_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {
1635 ; SI-LABEL: s_shl_inline_imm_neg_0_5_i64:
1636 ; SI: ; %bb.0:
1637 ; SI-NEXT: s_load_dword s4, s[0:1], 0xd
1638 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
1639 ; SI-NEXT: s_mov_b32 s3, 0xf000
1640 ; SI-NEXT: s_mov_b32 s2, -1
1641 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1642 ; SI-NEXT: s_lshl_b64 s[4:5], -0.5, s4
1643 ; SI-NEXT: v_mov_b32_e32 v0, s4
1644 ; SI-NEXT: v_mov_b32_e32 v1, s5
1645 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1646 ; SI-NEXT: s_endpgm
1647 ;
1648 ; VI-LABEL: s_shl_inline_imm_neg_0_5_i64:
1649 ; VI: ; %bb.0:
1650 ; VI-NEXT: s_load_dword s4, s[0:1], 0x34
1651 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1652 ; VI-NEXT: s_mov_b32 s3, 0xf000
1653 ; VI-NEXT: s_mov_b32 s2, -1
1654 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1655 ; VI-NEXT: s_lshl_b64 s[4:5], -0.5, s4
1656 ; VI-NEXT: v_mov_b32_e32 v0, s4
1657 ; VI-NEXT: v_mov_b32_e32 v1, s5
1658 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1659 ; VI-NEXT: s_endpgm
1660 ;
1661 ; EG-LABEL: s_shl_inline_imm_neg_0_5_i64:
1662 ; EG: ; %bb.0:
1663 ; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]
1664 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
1665 ; EG-NEXT: CF_END
1666 ; EG-NEXT: PAD
1667 ; EG-NEXT: ALU clause starting at 4:
1668 ; EG-NEXT: NOT_INT * T0.W, KC0[2].W,
1669 ; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,
1670 ; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y,
1671 ; EG-NEXT: 1609564160(3.458765e+19), 32(4.484155e-44)
1672 ; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0,
1673 ; EG-NEXT: MOV T0.X, 0.0,
1674 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
1675 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
1676 %shl = shl i64 13826050856027422720, %a
1677 store i64 %shl, ptr addrspace(1) %out, align 8
1678 ret void
1679 }
1681 define amdgpu_kernel void @s_shl_inline_imm_2_0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {
1682 ; SI-LABEL: s_shl_inline_imm_2_0_i64:
1683 ; SI: ; %bb.0:
1684 ; SI-NEXT: s_load_dword s4, s[0:1], 0xd
1685 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
1686 ; SI-NEXT: s_mov_b32 s3, 0xf000
1687 ; SI-NEXT: s_mov_b32 s2, -1
1688 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1689 ; SI-NEXT: s_lshl_b64 s[4:5], 2.0, s4
1690 ; SI-NEXT: v_mov_b32_e32 v0, s4
1691 ; SI-NEXT: v_mov_b32_e32 v1, s5
1692 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1693 ; SI-NEXT: s_endpgm
1694 ;
1695 ; VI-LABEL: s_shl_inline_imm_2_0_i64:
1696 ; VI: ; %bb.0:
1697 ; VI-NEXT: s_load_dword s4, s[0:1], 0x34
1698 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1699 ; VI-NEXT: s_mov_b32 s3, 0xf000
1700 ; VI-NEXT: s_mov_b32 s2, -1
1701 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1702 ; VI-NEXT: s_lshl_b64 s[4:5], 2.0, s4
1703 ; VI-NEXT: v_mov_b32_e32 v0, s4
1704 ; VI-NEXT: v_mov_b32_e32 v1, s5
1705 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1706 ; VI-NEXT: s_endpgm
1707 ;
1708 ; EG-LABEL: s_shl_inline_imm_2_0_i64:
1709 ; EG: ; %bb.0:
1710 ; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]
1711 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
1712 ; EG-NEXT: CF_END
1713 ; EG-NEXT: PAD
1714 ; EG-NEXT: ALU clause starting at 4:
1715 ; EG-NEXT: NOT_INT * T0.W, KC0[2].W,
1716 ; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,
1717 ; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y,
1718 ; EG-NEXT: 536870912(1.084202e-19), 32(4.484155e-44)
1719 ; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0,
1720 ; EG-NEXT: MOV T0.X, 0.0,
1721 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
1722 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
1723 %shl = shl i64 4611686018427387904, %a
1724 store i64 %shl, ptr addrspace(1) %out, align 8
1725 ret void
1726 }
1728 define amdgpu_kernel void @s_shl_inline_imm_neg_2_0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {
1729 ; SI-LABEL: s_shl_inline_imm_neg_2_0_i64:
1730 ; SI: ; %bb.0:
1731 ; SI-NEXT: s_load_dword s4, s[0:1], 0xd
1732 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
1733 ; SI-NEXT: s_mov_b32 s3, 0xf000
1734 ; SI-NEXT: s_mov_b32 s2, -1
1735 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1736 ; SI-NEXT: s_lshl_b64 s[4:5], -2.0, s4
1737 ; SI-NEXT: v_mov_b32_e32 v0, s4
1738 ; SI-NEXT: v_mov_b32_e32 v1, s5
1739 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1740 ; SI-NEXT: s_endpgm
1741 ;
1742 ; VI-LABEL: s_shl_inline_imm_neg_2_0_i64:
1743 ; VI: ; %bb.0:
1744 ; VI-NEXT: s_load_dword s4, s[0:1], 0x34
1745 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1746 ; VI-NEXT: s_mov_b32 s3, 0xf000
1747 ; VI-NEXT: s_mov_b32 s2, -1
1748 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1749 ; VI-NEXT: s_lshl_b64 s[4:5], -2.0, s4
1750 ; VI-NEXT: v_mov_b32_e32 v0, s4
1751 ; VI-NEXT: v_mov_b32_e32 v1, s5
1752 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1753 ; VI-NEXT: s_endpgm
1754 ;
1755 ; EG-LABEL: s_shl_inline_imm_neg_2_0_i64:
1756 ; EG: ; %bb.0:
1757 ; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]
1758 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
1759 ; EG-NEXT: CF_END
1760 ; EG-NEXT: PAD
1761 ; EG-NEXT: ALU clause starting at 4:
1762 ; EG-NEXT: NOT_INT * T0.W, KC0[2].W,
1763 ; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,
1764 ; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y,
1765 ; EG-NEXT: 1610612736(3.689349e+19), 32(4.484155e-44)
1766 ; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0,
1767 ; EG-NEXT: MOV T0.X, 0.0,
1768 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
1769 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
1770 %shl = shl i64 13835058055282163712, %a
1771 store i64 %shl, ptr addrspace(1) %out, align 8
1772 ret void
1773 }
1775 define amdgpu_kernel void @s_shl_inline_imm_4_0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {
1776 ; SI-LABEL: s_shl_inline_imm_4_0_i64:
1777 ; SI: ; %bb.0:
1778 ; SI-NEXT: s_load_dword s4, s[0:1], 0xd
1779 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
1780 ; SI-NEXT: s_mov_b32 s3, 0xf000
1781 ; SI-NEXT: s_mov_b32 s2, -1
1782 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1783 ; SI-NEXT: s_lshl_b64 s[4:5], 4.0, s4
1784 ; SI-NEXT: v_mov_b32_e32 v0, s4
1785 ; SI-NEXT: v_mov_b32_e32 v1, s5
1786 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1787 ; SI-NEXT: s_endpgm
1788 ;
1789 ; VI-LABEL: s_shl_inline_imm_4_0_i64:
1790 ; VI: ; %bb.0:
1791 ; VI-NEXT: s_load_dword s4, s[0:1], 0x34
1792 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1793 ; VI-NEXT: s_mov_b32 s3, 0xf000
1794 ; VI-NEXT: s_mov_b32 s2, -1
1795 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1796 ; VI-NEXT: s_lshl_b64 s[4:5], 4.0, s4
1797 ; VI-NEXT: v_mov_b32_e32 v0, s4
1798 ; VI-NEXT: v_mov_b32_e32 v1, s5
1799 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1800 ; VI-NEXT: s_endpgm
1801 ;
1802 ; EG-LABEL: s_shl_inline_imm_4_0_i64:
1803 ; EG: ; %bb.0:
1804 ; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]
1805 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
1806 ; EG-NEXT: CF_END
1807 ; EG-NEXT: PAD
1808 ; EG-NEXT: ALU clause starting at 4:
1809 ; EG-NEXT: NOT_INT * T0.W, KC0[2].W,
1810 ; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,
1811 ; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y,
1812 ; EG-NEXT: 537395200(1.151965e-19), 32(4.484155e-44)
1813 ; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0,
1814 ; EG-NEXT: MOV T0.X, 0.0,
1815 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
1816 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
1817 %shl = shl i64 4616189618054758400, %a
1818 store i64 %shl, ptr addrspace(1) %out, align 8
1819 ret void
1820 }
1822 define amdgpu_kernel void @s_shl_inline_imm_neg_4_0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {
1823 ; SI-LABEL: s_shl_inline_imm_neg_4_0_i64:
1824 ; SI: ; %bb.0:
1825 ; SI-NEXT: s_load_dword s4, s[0:1], 0xd
1826 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
1827 ; SI-NEXT: s_mov_b32 s3, 0xf000
1828 ; SI-NEXT: s_mov_b32 s2, -1
1829 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1830 ; SI-NEXT: s_lshl_b64 s[4:5], -4.0, s4
1831 ; SI-NEXT: v_mov_b32_e32 v0, s4
1832 ; SI-NEXT: v_mov_b32_e32 v1, s5
1833 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1834 ; SI-NEXT: s_endpgm
1835 ;
1836 ; VI-LABEL: s_shl_inline_imm_neg_4_0_i64:
1837 ; VI: ; %bb.0:
1838 ; VI-NEXT: s_load_dword s4, s[0:1], 0x34
1839 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1840 ; VI-NEXT: s_mov_b32 s3, 0xf000
1841 ; VI-NEXT: s_mov_b32 s2, -1
1842 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1843 ; VI-NEXT: s_lshl_b64 s[4:5], -4.0, s4
1844 ; VI-NEXT: v_mov_b32_e32 v0, s4
1845 ; VI-NEXT: v_mov_b32_e32 v1, s5
1846 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1847 ; VI-NEXT: s_endpgm
1848 ;
1849 ; EG-LABEL: s_shl_inline_imm_neg_4_0_i64:
1850 ; EG: ; %bb.0:
1851 ; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]
1852 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
1853 ; EG-NEXT: CF_END
1854 ; EG-NEXT: PAD
1855 ; EG-NEXT: ALU clause starting at 4:
1856 ; EG-NEXT: NOT_INT * T0.W, KC0[2].W,
1857 ; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,
1858 ; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y,
1859 ; EG-NEXT: 1611137024(3.919933e+19), 32(4.484155e-44)
1860 ; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0,
1861 ; EG-NEXT: MOV T0.X, 0.0,
1862 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
1863 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
1864 %shl = shl i64 13839561654909534208, %a
1865 store i64 %shl, ptr addrspace(1) %out, align 8
1866 ret void
1867 }
1870 ; Test with the 64-bit integer bitpattern for a 32-bit float in the
1871 ; low 32-bits, which is not a valid 64-bit inline immmediate.
1872 define amdgpu_kernel void @s_shl_inline_imm_f32_4_0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {
1873 ; SI-LABEL: s_shl_inline_imm_f32_4_0_i64:
1874 ; SI: ; %bb.0:
1875 ; SI-NEXT: s_load_dword s4, s[0:1], 0xd
1876 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
1877 ; SI-NEXT: s_mov_b32 s3, 0xf000
1878 ; SI-NEXT: s_mov_b32 s2, -1
1879 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1880 ; SI-NEXT: s_lshl_b64 s[4:5], 0x40800000, s4
1881 ; SI-NEXT: v_mov_b32_e32 v0, s4
1882 ; SI-NEXT: v_mov_b32_e32 v1, s5
1883 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1884 ; SI-NEXT: s_endpgm
1885 ;
1886 ; VI-LABEL: s_shl_inline_imm_f32_4_0_i64:
1887 ; VI: ; %bb.0:
1888 ; VI-NEXT: s_load_dword s4, s[0:1], 0x34
1889 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
1890 ; VI-NEXT: s_mov_b32 s3, 0xf000
1891 ; VI-NEXT: s_mov_b32 s2, -1
1892 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1893 ; VI-NEXT: s_lshl_b64 s[4:5], 0x40800000, s4
1894 ; VI-NEXT: v_mov_b32_e32 v0, s4
1895 ; VI-NEXT: v_mov_b32_e32 v1, s5
1896 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1897 ; VI-NEXT: s_endpgm
1898 ;
1899 ; EG-LABEL: s_shl_inline_imm_f32_4_0_i64:
1900 ; EG: ; %bb.0:
1901 ; EG-NEXT: ALU 11, @4, KC0[CB0:0-32], KC1[]
1902 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
1903 ; EG-NEXT: CF_END
1904 ; EG-NEXT: PAD
1905 ; EG-NEXT: ALU clause starting at 4:
1906 ; EG-NEXT: NOT_INT T0.W, KC0[2].W,
1907 ; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.x,
1908 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
1909 ; EG-NEXT: LSHL T0.Z, literal.x, PS,
1910 ; EG-NEXT: BIT_ALIGN_INT T0.W, 0.0, literal.y, PV.W,
1911 ; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.z,
1912 ; EG-NEXT: 1082130432(4.000000e+00), 541065216(1.626303e-19)
1913 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
1914 ; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, PV.Z,
1915 ; EG-NEXT: CNDE_INT T0.X, T1.W, T0.Z, 0.0,
1916 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
1917 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
1918 %shl = shl i64 1082130432, %a
1919 store i64 %shl, ptr addrspace(1) %out, align 8
1920 ret void
1921 }
1923 ; FIXME: Copy of -1 register
1924 define amdgpu_kernel void @s_shl_inline_imm_f32_neg_4_0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {
1925 ; SI-LABEL: s_shl_inline_imm_f32_neg_4_0_i64:
1926 ; SI: ; %bb.0:
1927 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
1928 ; SI-NEXT: s_load_dword s2, s[0:1], 0xd
1929 ; SI-NEXT: s_mov_b32 s0, -4.0
1930 ; SI-NEXT: s_mov_b32 s1, -1
1931 ; SI-NEXT: s_mov_b32 s7, 0xf000
1932 ; SI-NEXT: s_mov_b32 s6, -1
1933 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1934 ; SI-NEXT: s_lshl_b64 s[0:1], s[0:1], s2
1935 ; SI-NEXT: v_mov_b32_e32 v0, s0
1936 ; SI-NEXT: v_mov_b32_e32 v1, s1
1937 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1938 ; SI-NEXT: s_endpgm
1939 ;
1940 ; VI-LABEL: s_shl_inline_imm_f32_neg_4_0_i64:
1941 ; VI: ; %bb.0:
1942 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
1943 ; VI-NEXT: s_load_dword s2, s[0:1], 0x34
1944 ; VI-NEXT: s_mov_b32 s0, -4.0
1945 ; VI-NEXT: s_mov_b32 s1, -1
1946 ; VI-NEXT: s_mov_b32 s7, 0xf000
1947 ; VI-NEXT: s_mov_b32 s6, -1
1948 ; VI-NEXT: s_waitcnt lgkmcnt(0)
1949 ; VI-NEXT: s_lshl_b64 s[0:1], s[0:1], s2
1950 ; VI-NEXT: v_mov_b32_e32 v0, s0
1951 ; VI-NEXT: v_mov_b32_e32 v1, s1
1952 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1953 ; VI-NEXT: s_endpgm
1954 ;
1955 ; EG-LABEL: s_shl_inline_imm_f32_neg_4_0_i64:
1956 ; EG: ; %bb.0:
1957 ; EG-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[]
1958 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
1959 ; EG-NEXT: CF_END
1960 ; EG-NEXT: PAD
1961 ; EG-NEXT: ALU clause starting at 4:
1962 ; EG-NEXT: AND_INT T0.Z, KC0[2].W, literal.x,
1963 ; EG-NEXT: MOV T0.W, literal.y,
1964 ; EG-NEXT: NOT_INT * T1.W, KC0[2].W,
1965 ; EG-NEXT: 31(4.344025e-44), -532676608(-5.534023e+19)
1966 ; EG-NEXT: BIT_ALIGN_INT T1.Z, literal.x, PV.W, PS,
1967 ; EG-NEXT: LSHL T0.W, literal.y, PV.Z,
1968 ; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.z,
1969 ; EG-NEXT: 2147483647(nan), -1065353216(-4.000000e+00)
1970 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
1971 ; EG-NEXT: CNDE_INT * T0.Y, PS, PV.Z, PV.W,
1972 ; EG-NEXT: CNDE_INT T0.X, T1.W, T0.W, 0.0,
1973 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
1974 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
1975 %shl = shl i64 -1065353216, %a
1976 store i64 %shl, ptr addrspace(1) %out, align 8
1977 ret void
1978 }
1980 define amdgpu_kernel void @s_shl_inline_high_imm_f32_4_0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {
1981 ; SI-LABEL: s_shl_inline_high_imm_f32_4_0_i64:
1982 ; SI: ; %bb.0:
1983 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
1984 ; SI-NEXT: s_load_dword s2, s[0:1], 0xd
1985 ; SI-NEXT: s_mov_b32 s0, 0
1986 ; SI-NEXT: s_mov_b32 s1, 4.0
1987 ; SI-NEXT: s_mov_b32 s7, 0xf000
1988 ; SI-NEXT: s_mov_b32 s6, -1
1989 ; SI-NEXT: s_waitcnt lgkmcnt(0)
1990 ; SI-NEXT: s_lshl_b64 s[0:1], s[0:1], s2
1991 ; SI-NEXT: v_mov_b32_e32 v0, s0
1992 ; SI-NEXT: v_mov_b32_e32 v1, s1
1993 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1994 ; SI-NEXT: s_endpgm
1995 ;
1996 ; VI-LABEL: s_shl_inline_high_imm_f32_4_0_i64:
1997 ; VI: ; %bb.0:
1998 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
1999 ; VI-NEXT: s_load_dword s2, s[0:1], 0x34
2000 ; VI-NEXT: s_mov_b32 s0, 0
2001 ; VI-NEXT: s_mov_b32 s1, 4.0
2002 ; VI-NEXT: s_mov_b32 s7, 0xf000
2003 ; VI-NEXT: s_mov_b32 s6, -1
2004 ; VI-NEXT: s_waitcnt lgkmcnt(0)
2005 ; VI-NEXT: s_lshl_b64 s[0:1], s[0:1], s2
2006 ; VI-NEXT: v_mov_b32_e32 v0, s0
2007 ; VI-NEXT: v_mov_b32_e32 v1, s1
2008 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
2009 ; VI-NEXT: s_endpgm
2010 ;
2011 ; EG-LABEL: s_shl_inline_high_imm_f32_4_0_i64:
2012 ; EG: ; %bb.0:
2013 ; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]
2014 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
2015 ; EG-NEXT: CF_END
2016 ; EG-NEXT: PAD
2017 ; EG-NEXT: ALU clause starting at 4:
2018 ; EG-NEXT: NOT_INT * T0.W, KC0[2].W,
2019 ; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,
2020 ; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y,
2021 ; EG-NEXT: 541065216(1.626303e-19), 32(4.484155e-44)
2022 ; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0,
2023 ; EG-NEXT: MOV T0.X, 0.0,
2024 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
2025 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
2026 %shl = shl i64 4647714815446351872, %a
2027 store i64 %shl, ptr addrspace(1) %out, align 8
2028 ret void
2029 }
2031 define amdgpu_kernel void @s_shl_inline_high_imm_f32_neg_4_0_i64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, i64 %a) {
2032 ; SI-LABEL: s_shl_inline_high_imm_f32_neg_4_0_i64:
2033 ; SI: ; %bb.0:
2034 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
2035 ; SI-NEXT: s_load_dword s2, s[0:1], 0xd
2036 ; SI-NEXT: s_mov_b32 s0, 0
2037 ; SI-NEXT: s_mov_b32 s1, -4.0
2038 ; SI-NEXT: s_mov_b32 s7, 0xf000
2039 ; SI-NEXT: s_mov_b32 s6, -1
2040 ; SI-NEXT: s_waitcnt lgkmcnt(0)
2041 ; SI-NEXT: s_lshl_b64 s[0:1], s[0:1], s2
2042 ; SI-NEXT: v_mov_b32_e32 v0, s0
2043 ; SI-NEXT: v_mov_b32_e32 v1, s1
2044 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
2045 ; SI-NEXT: s_endpgm
2046 ;
2047 ; VI-LABEL: s_shl_inline_high_imm_f32_neg_4_0_i64:
2048 ; VI: ; %bb.0:
2049 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
2050 ; VI-NEXT: s_load_dword s2, s[0:1], 0x34
2051 ; VI-NEXT: s_mov_b32 s0, 0
2052 ; VI-NEXT: s_mov_b32 s1, -4.0
2053 ; VI-NEXT: s_mov_b32 s7, 0xf000
2054 ; VI-NEXT: s_mov_b32 s6, -1
2055 ; VI-NEXT: s_waitcnt lgkmcnt(0)
2056 ; VI-NEXT: s_lshl_b64 s[0:1], s[0:1], s2
2057 ; VI-NEXT: v_mov_b32_e32 v0, s0
2058 ; VI-NEXT: v_mov_b32_e32 v1, s1
2059 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
2060 ; VI-NEXT: s_endpgm
2061 ;
2062 ; EG-LABEL: s_shl_inline_high_imm_f32_neg_4_0_i64:
2063 ; EG: ; %bb.0:
2064 ; EG-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]
2065 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
2066 ; EG-NEXT: CF_END
2067 ; EG-NEXT: PAD
2068 ; EG-NEXT: ALU clause starting at 4:
2069 ; EG-NEXT: NOT_INT * T0.W, KC0[2].W,
2070 ; EG-NEXT: BIT_ALIGN_INT T0.W, literal.x, 0.0, PV.W,
2071 ; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y,
2072 ; EG-NEXT: 1614807040(5.534023e+19), 32(4.484155e-44)
2073 ; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, 0.0,
2074 ; EG-NEXT: MOV T0.X, 0.0,
2075 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
2076 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
2077 %shl = shl i64 13871086852301127680, %a
2078 store i64 %shl, ptr addrspace(1) %out, align 8
2079 ret void
2080 }
2082 define amdgpu_kernel void @test_mul2(i32 %p) {
2083 ; SI-LABEL: test_mul2:
2084 ; SI: ; %bb.0:
2085 ; SI-NEXT: s_load_dword s0, s[0:1], 0x9
2086 ; SI-NEXT: s_mov_b32 s3, 0xf000
2087 ; SI-NEXT: s_mov_b32 s2, -1
2088 ; SI-NEXT: s_waitcnt lgkmcnt(0)
2089 ; SI-NEXT: s_lshl_b32 s0, s0, 1
2090 ; SI-NEXT: v_mov_b32_e32 v0, s0
2091 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
2092 ; SI-NEXT: s_waitcnt vmcnt(0)
2093 ; SI-NEXT: s_endpgm
2094 ;
2095 ; VI-LABEL: test_mul2:
2096 ; VI: ; %bb.0:
2097 ; VI-NEXT: s_load_dword s0, s[0:1], 0x24
2098 ; VI-NEXT: s_mov_b32 s3, 0xf000
2099 ; VI-NEXT: s_mov_b32 s2, -1
2100 ; VI-NEXT: s_waitcnt lgkmcnt(0)
2101 ; VI-NEXT: s_lshl_b32 s0, s0, 1
2102 ; VI-NEXT: v_mov_b32_e32 v0, s0
2103 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
2104 ; VI-NEXT: s_waitcnt vmcnt(0)
2105 ; VI-NEXT: s_endpgm
2106 ;
2107 ; EG-LABEL: test_mul2:
2108 ; EG: ; %bb.0:
2109 ; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
2110 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
2111 ; EG-NEXT: CF_END
2112 ; EG-NEXT: PAD
2113 ; EG-NEXT: ALU clause starting at 4:
2114 ; EG-NEXT: MOV T0.X, literal.x,
2115 ; EG-NEXT: LSHL * T1.X, KC0[2].Y, 1,
2116 ; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00)
2117 %i = mul i32 %p, 2
2118 store volatile i32 %i, ptr addrspace(1) undef
2119 ret void
2120 }
2122 define void @shl_or_k(ptr addrspace(1) %out, i32 %in) {
2123 ; SI-LABEL: shl_or_k:
2124 ; SI: ; %bb.0:
2125 ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2126 ; SI-NEXT: s_mov_b32 s6, 0
2127 ; SI-NEXT: v_lshlrev_b32_e32 v2, 2, v2
2128 ; SI-NEXT: s_mov_b32 s7, 0xf000
2129 ; SI-NEXT: s_mov_b32 s4, s6
2130 ; SI-NEXT: s_mov_b32 s5, s6
2131 ; SI-NEXT: v_or_b32_e32 v2, 4, v2
2132 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
2133 ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
2134 ; SI-NEXT: s_setpc_b64 s[30:31]
2135 ;
2136 ; VI-LABEL: shl_or_k:
2137 ; VI: ; %bb.0:
2138 ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2139 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v2
2140 ; VI-NEXT: v_or_b32_e32 v2, 4, v2
2141 ; VI-NEXT: flat_store_dword v[0:1], v2
2142 ; VI-NEXT: s_waitcnt vmcnt(0)
2143 ; VI-NEXT: s_setpc_b64 s[30:31]
2144 ;
2145 ; EG-LABEL: shl_or_k:
2146 ; EG: ; %bb.0:
2147 ; EG-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]
2148 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
2149 ; EG-NEXT: CF_END
2150 ; EG-NEXT: PAD
2151 ; EG-NEXT: ALU clause starting at 4:
2152 ; EG-NEXT: LSHL * T0.W, KC0[2].Z, literal.x,
2153 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
2154 ; EG-NEXT: OR_INT T0.X, PV.W, literal.x,
2155 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
2156 ; EG-NEXT: 4(5.605194e-45), 2(2.802597e-45)
2157 %tmp0 = or i32 %in, 1
2158 %tmp2 = shl i32 %tmp0, 2
2159 store i32 %tmp2, ptr addrspace(1) %out
2160 ret void
2161 }
2163 define void @shl_or_k_two_uses(ptr addrspace(1) %out0, ptr addrspace(1) %out1, i32 %in) {
2164 ; SI-LABEL: shl_or_k_two_uses:
2165 ; SI: ; %bb.0:
2166 ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2167 ; SI-NEXT: s_mov_b32 s6, 0
2168 ; SI-NEXT: v_or_b32_e32 v4, 1, v4
2169 ; SI-NEXT: s_mov_b32 s7, 0xf000
2170 ; SI-NEXT: s_mov_b32 s4, s6
2171 ; SI-NEXT: s_mov_b32 s5, s6
2172 ; SI-NEXT: v_lshlrev_b32_e32 v5, 2, v4
2173 ; SI-NEXT: buffer_store_dword v5, v[0:1], s[4:7], 0 addr64
2174 ; SI-NEXT: buffer_store_dword v4, v[2:3], s[4:7], 0 addr64
2175 ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
2176 ; SI-NEXT: s_setpc_b64 s[30:31]
2177 ;
2178 ; VI-LABEL: shl_or_k_two_uses:
2179 ; VI: ; %bb.0:
2180 ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2181 ; VI-NEXT: v_or_b32_e32 v4, 1, v4
2182 ; VI-NEXT: v_lshlrev_b32_e32 v5, 2, v4
2183 ; VI-NEXT: flat_store_dword v[0:1], v5
2184 ; VI-NEXT: flat_store_dword v[2:3], v4
2185 ; VI-NEXT: s_waitcnt vmcnt(0)
2186 ; VI-NEXT: s_setpc_b64 s[30:31]
2187 ;
2188 ; EG-LABEL: shl_or_k_two_uses:
2189 ; EG: ; %bb.0:
2190 ; EG-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]
2191 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.X, T3.X, 0
2192 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
2193 ; EG-NEXT: CF_END
2194 ; EG-NEXT: ALU clause starting at 4:
2195 ; EG-NEXT: LSHR T0.X, KC0[2].Z, literal.x,
2196 ; EG-NEXT: OR_INT * T1.X, KC0[2].W, 1,
2197 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
2198 ; EG-NEXT: LSHL T2.X, PS, literal.x,
2199 ; EG-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,
2200 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
2201 %tmp0 = or i32 %in, 1
2202 %tmp2 = shl i32 %tmp0, 2
2203 store i32 %tmp2, ptr addrspace(1) %out0
2204 store i32 %tmp0, ptr addrspace(1) %out1
2205 ret void
2206 }
2208 attributes #0 = { nounwind readnone }