1 ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=bonaire -enable-misched=0 -verify-machineinstrs < %s | FileCheck %s
2 ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=bonaire -enable-misched=0 -verify-machineinstrs < %s | FileCheck %s
4 declare void @llvm.write_register.i32(metadata, i32) #0
5 declare void @llvm.write_register.i64(metadata, i64) #0
7 ; CHECK-LABEL: {{^}}test_write_m0:
8 define amdgpu_kernel void @test_write_m0(i32 %val) #0 {
9 call void @llvm.write_register.i32(metadata !0, i32 0)
10 call void @llvm.write_register.i32(metadata !0, i32 -1)
11 call void @llvm.write_register.i32(metadata !0, i32 %val)
12 call void @llvm.amdgcn.wave.barrier() #1
16 ; CHECK-LABEL: {{^}}test_write_exec:
17 ; CHECK: s_mov_b64 exec, 0
18 ; CHECK: s_mov_b64 exec, -1
19 ; CHECK: s_mov_b64 exec, s{{\[[0-9]+:[0-9]+\]}}
20 define amdgpu_kernel void @test_write_exec(i64 %val) #0 {
21 call void @llvm.write_register.i64(metadata !1, i64 0)
22 call void @llvm.write_register.i64(metadata !1, i64 -1)
23 call void @llvm.write_register.i64(metadata !1, i64 %val)
24 call void @llvm.amdgcn.wave.barrier() #1
28 ; CHECK-LABEL: {{^}}test_write_flat_scratch_0:
29 ; CHECK: s_mov_b64 flat_scratch, 0
30 define amdgpu_kernel void @test_write_flat_scratch_0(i64 %val) #0 {
31 call void @llvm.write_register.i64(metadata !2, i64 0)
32 call void @llvm.amdgcn.wave.barrier() #1
36 ; CHECK-LABEL: {{^}}test_write_flat_scratch_neg1:
37 ; CHECK: s_mov_b64 flat_scratch, -1
38 define amdgpu_kernel void @test_write_flat_scratch_neg1(i64 %val) #0 {
39 call void @llvm.write_register.i64(metadata !2, i64 -1)
40 call void @llvm.amdgcn.wave.barrier() #1
44 ; CHECK-LABEL: {{^}}test_write_flat_scratch_val:
45 ; CHECK: s_load_dwordx2 flat_scratch, s{{\[[0-9]+:[0-9]+\]}}
46 define amdgpu_kernel void @test_write_flat_scratch_val(i64 %val) #0 {
47 call void @llvm.write_register.i64(metadata !2, i64 %val)
48 call void @llvm.amdgcn.wave.barrier() #1
52 ; CHECK-LABEL: {{^}}test_write_flat_scratch_lo:
53 ; CHECK: s_mov_b32 flat_scratch_lo, 0
54 ; CHECK: s_mov_b32 flat_scratch_lo, s{{[0-9]+}}
55 define amdgpu_kernel void @test_write_flat_scratch_lo(i32 %val) #0 {
56 call void @llvm.write_register.i32(metadata !3, i32 0)
57 call void @llvm.write_register.i32(metadata !3, i32 %val)
58 call void @llvm.amdgcn.wave.barrier() #1
62 ; CHECK-LABEL: {{^}}test_write_flat_scratch_hi:
63 ; CHECK: s_mov_b32 flat_scratch_hi, 0
64 ; CHECK: s_mov_b32 flat_scratch_hi, s{{[0-9]+}}
65 define amdgpu_kernel void @test_write_flat_scratch_hi(i32 %val) #0 {
66 call void @llvm.write_register.i32(metadata !4, i32 0)
67 call void @llvm.write_register.i32(metadata !4, i32 %val)
68 call void @llvm.amdgcn.wave.barrier() #1
72 ; CHECK-LABEL: {{^}}test_write_exec_lo:
73 ; CHECK: s_mov_b32 exec_lo, 0
74 ; CHECK: s_mov_b32 exec_lo, s{{[0-9]+}}
75 define amdgpu_kernel void @test_write_exec_lo(i32 %val) #0 {
76 call void @llvm.write_register.i32(metadata !5, i32 0)
77 call void @llvm.write_register.i32(metadata !5, i32 %val)
78 call void @llvm.amdgcn.wave.barrier() #1
82 ; CHECK-LABEL: {{^}}test_write_exec_hi:
83 ; CHECK: s_mov_b32 exec_hi, 0
84 ; CHECK: s_mov_b32 exec_hi, s{{[0-9]+}}
85 define amdgpu_kernel void @test_write_exec_hi(i32 %val) #0 {
86 call void @llvm.write_register.i32(metadata !6, i32 0)
87 call void @llvm.write_register.i32(metadata !6, i32 %val)
88 call void @llvm.amdgcn.wave.barrier() #1
92 declare void @llvm.amdgcn.wave.barrier() #1
94 attributes #0 = { nounwind }
95 attributes #1 = { convergent nounwind }
99 !2 = !{!"flat_scratch"}
100 !3 = !{!"flat_scratch_lo"}
101 !4 = !{!"flat_scratch_hi"}