1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2 ; RUN: llc -mtriple=arm-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - -O3 \
3 ; RUN: -asm-verbose=0 | FileCheck %s
5 ; This tests exerts the folding of `VT = (and (sign_extend NarrowVT to
6 ; VT) #bitmask)` into `VT = (zero_extend NarrowVT to VT)` when
7 ; #bitmask value is the mask made by all ones that selects the value
8 ; of type NarrowVT inside the value of type VT. The folding is
9 ; implemented in `DAGCombiner::visitAND`.
11 ; With this the folding, the `and` of the "signed extended load" of
12 ; `%b` in `f_i16_i32` is rendered as a zero extended load.
14 define i32 @f_i16_i32(ptr %a, ptr %b) {
15 ; CHECK-LABEL: f_i16_i32:
16 ; CHECK: ldrh r1, [r1]
17 ; CHECK-NEXT: ldrsh r0, [r0]
18 ; CHECK-NEXT: smulbb r0, r0, r1
19 ; CHECK-NEXT: mul r0, r0, r1
21 %1 = load i16, ptr %a, align 2
22 %sext.1 = sext i16 %1 to i32
23 %2 = load i16, ptr %b, align 2
24 %sext.2 = sext i16 %2 to i32
25 %masked = and i32 %sext.2, 65535
26 %mul = mul nsw i32 %sext.2, %sext.1
27 %count.next = mul i32 %mul, %masked