1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=+d,+m,+zfh,+zvfh,+v -target-abi=ilp32d \
3 ; RUN: -verify-machineinstrs < %s | FileCheck %s
4 ; RUN: llc -mtriple=riscv64 -mattr=+d,+m,+zfh,+zvfh,+v -target-abi=lp64d \
5 ; RUN: -verify-machineinstrs < %s | FileCheck %s
6 ; RUN: llc -mtriple=riscv32 -mattr=+d,+m,+zfh,+zvfhmin,+v -target-abi=ilp32d \
7 ; RUN: -verify-machineinstrs < %s | FileCheck %s
8 ; RUN: llc -mtriple=riscv64 -mattr=+d,+m,+zfh,+zvfhmin,+v -target-abi=lp64d \
9 ; RUN: -verify-machineinstrs < %s | FileCheck %s
11 declare <vscale x 1 x i1> @llvm.vp.select.nxv1i1(<vscale x 1 x i1>, <vscale x 1 x i1>, <vscale x 1 x i1>, i32)
13 define <vscale x 1 x i1> @select_nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, <vscale x 1 x i1> %c, i32 zeroext %evl) {
14 ; CHECK-LABEL: select_nxv1i1:
16 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
17 ; CHECK-NEXT: vmandn.mm v9, v9, v0
18 ; CHECK-NEXT: vmand.mm v8, v8, v0
19 ; CHECK-NEXT: vmor.mm v0, v8, v9
21 %v = call <vscale x 1 x i1> @llvm.vp.select.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, <vscale x 1 x i1> %c, i32 %evl)
22 ret <vscale x 1 x i1> %v
25 declare <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>, <vscale x 2 x i1>, i32)
27 define <vscale x 2 x i1> @select_nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b, <vscale x 2 x i1> %c, i32 zeroext %evl) {
28 ; CHECK-LABEL: select_nxv2i1:
30 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
31 ; CHECK-NEXT: vmandn.mm v9, v9, v0
32 ; CHECK-NEXT: vmand.mm v8, v8, v0
33 ; CHECK-NEXT: vmor.mm v0, v8, v9
35 %v = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b, <vscale x 2 x i1> %c, i32 %evl)
36 ret <vscale x 2 x i1> %v
39 declare <vscale x 4 x i1> @llvm.vp.select.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>, <vscale x 4 x i1>, i32)
41 define <vscale x 4 x i1> @select_nxv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b, <vscale x 4 x i1> %c, i32 zeroext %evl) {
42 ; CHECK-LABEL: select_nxv4i1:
44 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
45 ; CHECK-NEXT: vmandn.mm v9, v9, v0
46 ; CHECK-NEXT: vmand.mm v8, v8, v0
47 ; CHECK-NEXT: vmor.mm v0, v8, v9
49 %v = call <vscale x 4 x i1> @llvm.vp.select.nxv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b, <vscale x 4 x i1> %c, i32 %evl)
50 ret <vscale x 4 x i1> %v
53 declare <vscale x 8 x i1> @llvm.vp.select.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>, <vscale x 8 x i1>, i32)
55 define <vscale x 8 x i1> @select_nxv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b, <vscale x 8 x i1> %c, i32 zeroext %evl) {
56 ; CHECK-LABEL: select_nxv8i1:
58 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
59 ; CHECK-NEXT: vmandn.mm v9, v9, v0
60 ; CHECK-NEXT: vmand.mm v8, v8, v0
61 ; CHECK-NEXT: vmor.mm v0, v8, v9
63 %v = call <vscale x 8 x i1> @llvm.vp.select.nxv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b, <vscale x 8 x i1> %c, i32 %evl)
64 ret <vscale x 8 x i1> %v
67 declare <vscale x 16 x i1> @llvm.vp.select.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, i32)
69 define <vscale x 16 x i1> @select_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c, i32 zeroext %evl) {
70 ; CHECK-LABEL: select_nxv16i1:
72 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
73 ; CHECK-NEXT: vmandn.mm v9, v9, v0
74 ; CHECK-NEXT: vmand.mm v8, v8, v0
75 ; CHECK-NEXT: vmor.mm v0, v8, v9
77 %v = call <vscale x 16 x i1> @llvm.vp.select.nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c, i32 %evl)
78 ret <vscale x 16 x i1> %v
81 declare <vscale x 32 x i1> @llvm.vp.select.nxv32i1(<vscale x 32 x i1>, <vscale x 32 x i1>, <vscale x 32 x i1>, i32)
83 define <vscale x 32 x i1> @select_nxv32i1(<vscale x 32 x i1> %a, <vscale x 32 x i1> %b, <vscale x 32 x i1> %c, i32 zeroext %evl) {
84 ; CHECK-LABEL: select_nxv32i1:
86 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
87 ; CHECK-NEXT: vmandn.mm v9, v9, v0
88 ; CHECK-NEXT: vmand.mm v8, v8, v0
89 ; CHECK-NEXT: vmor.mm v0, v8, v9
91 %v = call <vscale x 32 x i1> @llvm.vp.select.nxv32i1(<vscale x 32 x i1> %a, <vscale x 32 x i1> %b, <vscale x 32 x i1> %c, i32 %evl)
92 ret <vscale x 32 x i1> %v
95 declare <vscale x 64 x i1> @llvm.vp.select.nxv64i1(<vscale x 64 x i1>, <vscale x 64 x i1>, <vscale x 64 x i1>, i32)
97 define <vscale x 64 x i1> @select_nxv64i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b, <vscale x 64 x i1> %c, i32 zeroext %evl) {
98 ; CHECK-LABEL: select_nxv64i1:
100 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
101 ; CHECK-NEXT: vmandn.mm v9, v9, v0
102 ; CHECK-NEXT: vmand.mm v8, v8, v0
103 ; CHECK-NEXT: vmor.mm v0, v8, v9
105 %v = call <vscale x 64 x i1> @llvm.vp.select.nxv64i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b, <vscale x 64 x i1> %c, i32 %evl)
106 ret <vscale x 64 x i1> %v
109 declare <vscale x 8 x i7> @llvm.vp.select.nxv8i7(<vscale x 8 x i1>, <vscale x 8 x i7>, <vscale x 8 x i7>, i32)
111 define <vscale x 8 x i7> @select_nxv8i7(<vscale x 8 x i1> %a, <vscale x 8 x i7> %b, <vscale x 8 x i7> %c, i32 zeroext %evl) {
112 ; CHECK-LABEL: select_nxv8i7:
114 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
115 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
117 %v = call <vscale x 8 x i7> @llvm.vp.select.nxv8i7(<vscale x 8 x i1> %a, <vscale x 8 x i7> %b, <vscale x 8 x i7> %c, i32 %evl)
118 ret <vscale x 8 x i7> %v
121 declare <vscale x 1 x i8> @llvm.vp.select.nxv1i8(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, i32)
123 define <vscale x 1 x i8> @select_nxv1i8(<vscale x 1 x i1> %a, <vscale x 1 x i8> %b, <vscale x 1 x i8> %c, i32 zeroext %evl) {
124 ; CHECK-LABEL: select_nxv1i8:
126 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
127 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
129 %v = call <vscale x 1 x i8> @llvm.vp.select.nxv1i8(<vscale x 1 x i1> %a, <vscale x 1 x i8> %b, <vscale x 1 x i8> %c, i32 %evl)
130 ret <vscale x 1 x i8> %v
133 declare <vscale x 2 x i8> @llvm.vp.select.nxv2i8(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, i32)
135 define <vscale x 2 x i8> @select_nxv2i8(<vscale x 2 x i1> %a, <vscale x 2 x i8> %b, <vscale x 2 x i8> %c, i32 zeroext %evl) {
136 ; CHECK-LABEL: select_nxv2i8:
138 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
139 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
141 %v = call <vscale x 2 x i8> @llvm.vp.select.nxv2i8(<vscale x 2 x i1> %a, <vscale x 2 x i8> %b, <vscale x 2 x i8> %c, i32 %evl)
142 ret <vscale x 2 x i8> %v
145 declare <vscale x 4 x i8> @llvm.vp.select.nxv4i8(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, i32)
147 define <vscale x 4 x i8> @select_nxv4i8(<vscale x 4 x i1> %a, <vscale x 4 x i8> %b, <vscale x 4 x i8> %c, i32 zeroext %evl) {
148 ; CHECK-LABEL: select_nxv4i8:
150 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
151 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
153 %v = call <vscale x 4 x i8> @llvm.vp.select.nxv4i8(<vscale x 4 x i1> %a, <vscale x 4 x i8> %b, <vscale x 4 x i8> %c, i32 %evl)
154 ret <vscale x 4 x i8> %v
157 declare <vscale x 8 x i8> @llvm.vp.select.nxv8i8(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, i32)
159 define <vscale x 8 x i8> @select_nxv8i8(<vscale x 8 x i1> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c, i32 zeroext %evl) {
160 ; CHECK-LABEL: select_nxv8i8:
162 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
163 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
165 %v = call <vscale x 8 x i8> @llvm.vp.select.nxv8i8(<vscale x 8 x i1> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c, i32 %evl)
166 ret <vscale x 8 x i8> %v
169 declare <vscale x 14 x i8> @llvm.vp.select.nxv14i8(<vscale x 14 x i1>, <vscale x 14 x i8>, <vscale x 14 x i8>, i32)
171 define <vscale x 14 x i8> @select_nxv14i8(<vscale x 14 x i1> %a, <vscale x 14 x i8> %b, <vscale x 14 x i8> %c, i32 zeroext %evl) {
172 ; CHECK-LABEL: select_nxv14i8:
174 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
175 ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
177 %v = call <vscale x 14 x i8> @llvm.vp.select.nxv14i8(<vscale x 14 x i1> %a, <vscale x 14 x i8> %b, <vscale x 14 x i8> %c, i32 %evl)
178 ret <vscale x 14 x i8> %v
181 declare <vscale x 16 x i8> @llvm.vp.select.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32)
183 define <vscale x 16 x i8> @select_nxv16i8(<vscale x 16 x i1> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, i32 zeroext %evl) {
184 ; CHECK-LABEL: select_nxv16i8:
186 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
187 ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
189 %v = call <vscale x 16 x i8> @llvm.vp.select.nxv16i8(<vscale x 16 x i1> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, i32 %evl)
190 ret <vscale x 16 x i8> %v
193 declare <vscale x 32 x i8> @llvm.vp.select.nxv32i8(<vscale x 32 x i1>, <vscale x 32 x i8>, <vscale x 32 x i8>, i32)
195 define <vscale x 32 x i8> @select_nxv32i8(<vscale x 32 x i1> %a, <vscale x 32 x i8> %b, <vscale x 32 x i8> %c, i32 zeroext %evl) {
196 ; CHECK-LABEL: select_nxv32i8:
198 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
199 ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
201 %v = call <vscale x 32 x i8> @llvm.vp.select.nxv32i8(<vscale x 32 x i1> %a, <vscale x 32 x i8> %b, <vscale x 32 x i8> %c, i32 %evl)
202 ret <vscale x 32 x i8> %v
205 declare <vscale x 64 x i8> @llvm.vp.select.nxv64i8(<vscale x 64 x i1>, <vscale x 64 x i8>, <vscale x 64 x i8>, i32)
207 define <vscale x 64 x i8> @select_nxv64i8(<vscale x 64 x i1> %a, <vscale x 64 x i8> %b, <vscale x 64 x i8> %c, i32 zeroext %evl) {
208 ; CHECK-LABEL: select_nxv64i8:
210 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
211 ; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
213 %v = call <vscale x 64 x i8> @llvm.vp.select.nxv64i8(<vscale x 64 x i1> %a, <vscale x 64 x i8> %b, <vscale x 64 x i8> %c, i32 %evl)
214 ret <vscale x 64 x i8> %v
217 declare <vscale x 1 x i16> @llvm.vp.select.nxv1i16(<vscale x 1 x i1>, <vscale x 1 x i16>, <vscale x 1 x i16>, i32)
219 define <vscale x 1 x i16> @select_nxv1i16(<vscale x 1 x i1> %a, <vscale x 1 x i16> %b, <vscale x 1 x i16> %c, i32 zeroext %evl) {
220 ; CHECK-LABEL: select_nxv1i16:
222 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
223 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
225 %v = call <vscale x 1 x i16> @llvm.vp.select.nxv1i16(<vscale x 1 x i1> %a, <vscale x 1 x i16> %b, <vscale x 1 x i16> %c, i32 %evl)
226 ret <vscale x 1 x i16> %v
229 declare <vscale x 2 x i16> @llvm.vp.select.nxv2i16(<vscale x 2 x i1>, <vscale x 2 x i16>, <vscale x 2 x i16>, i32)
231 define <vscale x 2 x i16> @select_nxv2i16(<vscale x 2 x i1> %a, <vscale x 2 x i16> %b, <vscale x 2 x i16> %c, i32 zeroext %evl) {
232 ; CHECK-LABEL: select_nxv2i16:
234 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
235 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
237 %v = call <vscale x 2 x i16> @llvm.vp.select.nxv2i16(<vscale x 2 x i1> %a, <vscale x 2 x i16> %b, <vscale x 2 x i16> %c, i32 %evl)
238 ret <vscale x 2 x i16> %v
241 declare <vscale x 4 x i16> @llvm.vp.select.nxv4i16(<vscale x 4 x i1>, <vscale x 4 x i16>, <vscale x 4 x i16>, i32)
243 define <vscale x 4 x i16> @select_nxv4i16(<vscale x 4 x i1> %a, <vscale x 4 x i16> %b, <vscale x 4 x i16> %c, i32 zeroext %evl) {
244 ; CHECK-LABEL: select_nxv4i16:
246 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
247 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
249 %v = call <vscale x 4 x i16> @llvm.vp.select.nxv4i16(<vscale x 4 x i1> %a, <vscale x 4 x i16> %b, <vscale x 4 x i16> %c, i32 %evl)
250 ret <vscale x 4 x i16> %v
253 declare <vscale x 8 x i16> @llvm.vp.select.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)
255 define <vscale x 8 x i16> @select_nxv8i16(<vscale x 8 x i1> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, i32 zeroext %evl) {
256 ; CHECK-LABEL: select_nxv8i16:
258 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
259 ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
261 %v = call <vscale x 8 x i16> @llvm.vp.select.nxv8i16(<vscale x 8 x i1> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, i32 %evl)
262 ret <vscale x 8 x i16> %v
265 declare <vscale x 16 x i16> @llvm.vp.select.nxv16i16(<vscale x 16 x i1>, <vscale x 16 x i16>, <vscale x 16 x i16>, i32)
267 define <vscale x 16 x i16> @select_nxv16i16(<vscale x 16 x i1> %a, <vscale x 16 x i16> %b, <vscale x 16 x i16> %c, i32 zeroext %evl) {
268 ; CHECK-LABEL: select_nxv16i16:
270 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
271 ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
273 %v = call <vscale x 16 x i16> @llvm.vp.select.nxv16i16(<vscale x 16 x i1> %a, <vscale x 16 x i16> %b, <vscale x 16 x i16> %c, i32 %evl)
274 ret <vscale x 16 x i16> %v
277 declare <vscale x 32 x i16> @llvm.vp.select.nxv32i16(<vscale x 32 x i1>, <vscale x 32 x i16>, <vscale x 32 x i16>, i32)
279 define <vscale x 32 x i16> @select_nxv32i16(<vscale x 32 x i1> %a, <vscale x 32 x i16> %b, <vscale x 32 x i16> %c, i32 zeroext %evl) {
280 ; CHECK-LABEL: select_nxv32i16:
282 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
283 ; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
285 %v = call <vscale x 32 x i16> @llvm.vp.select.nxv32i16(<vscale x 32 x i1> %a, <vscale x 32 x i16> %b, <vscale x 32 x i16> %c, i32 %evl)
286 ret <vscale x 32 x i16> %v
289 declare <vscale x 1 x i32> @llvm.vp.select.nxv1i32(<vscale x 1 x i1>, <vscale x 1 x i32>, <vscale x 1 x i32>, i32)
291 define <vscale x 1 x i32> @select_nxv1i32(<vscale x 1 x i1> %a, <vscale x 1 x i32> %b, <vscale x 1 x i32> %c, i32 zeroext %evl) {
292 ; CHECK-LABEL: select_nxv1i32:
294 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
295 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
297 %v = call <vscale x 1 x i32> @llvm.vp.select.nxv1i32(<vscale x 1 x i1> %a, <vscale x 1 x i32> %b, <vscale x 1 x i32> %c, i32 %evl)
298 ret <vscale x 1 x i32> %v
301 declare <vscale x 2 x i32> @llvm.vp.select.nxv2i32(<vscale x 2 x i1>, <vscale x 2 x i32>, <vscale x 2 x i32>, i32)
303 define <vscale x 2 x i32> @select_nxv2i32(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, i32 zeroext %evl) {
304 ; CHECK-LABEL: select_nxv2i32:
306 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
307 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
309 %v = call <vscale x 2 x i32> @llvm.vp.select.nxv2i32(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, i32 %evl)
310 ret <vscale x 2 x i32> %v
313 declare <vscale x 4 x i32> @llvm.vp.select.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32)
315 define <vscale x 4 x i32> @select_nxv4i32(<vscale x 4 x i1> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, i32 zeroext %evl) {
316 ; CHECK-LABEL: select_nxv4i32:
318 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
319 ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
321 %v = call <vscale x 4 x i32> @llvm.vp.select.nxv4i32(<vscale x 4 x i1> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, i32 %evl)
322 ret <vscale x 4 x i32> %v
325 declare <vscale x 8 x i32> @llvm.vp.select.nxv8i32(<vscale x 8 x i1>, <vscale x 8 x i32>, <vscale x 8 x i32>, i32)
327 define <vscale x 8 x i32> @select_nxv8i32(<vscale x 8 x i1> %a, <vscale x 8 x i32> %b, <vscale x 8 x i32> %c, i32 zeroext %evl) {
328 ; CHECK-LABEL: select_nxv8i32:
330 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
331 ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
333 %v = call <vscale x 8 x i32> @llvm.vp.select.nxv8i32(<vscale x 8 x i1> %a, <vscale x 8 x i32> %b, <vscale x 8 x i32> %c, i32 %evl)
334 ret <vscale x 8 x i32> %v
337 declare <vscale x 16 x i32> @llvm.vp.select.nxv16i32(<vscale x 16 x i1>, <vscale x 16 x i32>, <vscale x 16 x i32>, i32)
339 define <vscale x 16 x i32> @select_nxv16i32(<vscale x 16 x i1> %a, <vscale x 16 x i32> %b, <vscale x 16 x i32> %c, i32 zeroext %evl) {
340 ; CHECK-LABEL: select_nxv16i32:
342 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
343 ; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
345 %v = call <vscale x 16 x i32> @llvm.vp.select.nxv16i32(<vscale x 16 x i1> %a, <vscale x 16 x i32> %b, <vscale x 16 x i32> %c, i32 %evl)
346 ret <vscale x 16 x i32> %v
349 declare <vscale x 32 x i32> @llvm.vp.select.nxv32i32(<vscale x 32 x i1>, <vscale x 32 x i32>, <vscale x 32 x i32>, i32)
351 define <vscale x 32 x i32> @select_nxv32i32(<vscale x 32 x i1> %a, <vscale x 32 x i32> %b, <vscale x 32 x i32> %c, i32 zeroext %evl) {
352 ; CHECK-LABEL: select_nxv32i32:
354 ; CHECK-NEXT: addi sp, sp, -16
355 ; CHECK-NEXT: .cfi_def_cfa_offset 16
356 ; CHECK-NEXT: csrr a1, vlenb
357 ; CHECK-NEXT: slli a1, a1, 4
358 ; CHECK-NEXT: sub sp, sp, a1
359 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
360 ; CHECK-NEXT: csrr a1, vlenb
361 ; CHECK-NEXT: slli a1, a1, 3
362 ; CHECK-NEXT: add a1, sp, a1
363 ; CHECK-NEXT: addi a1, a1, 16
364 ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
365 ; CHECK-NEXT: vmv1r.v v24, v0
366 ; CHECK-NEXT: csrr a3, vlenb
367 ; CHECK-NEXT: slli a1, a3, 3
368 ; CHECK-NEXT: add a1, a0, a1
369 ; CHECK-NEXT: vl8re32.v v8, (a1)
370 ; CHECK-NEXT: slli a1, a3, 1
371 ; CHECK-NEXT: sub a4, a2, a1
372 ; CHECK-NEXT: sltu a5, a2, a4
373 ; CHECK-NEXT: addi a5, a5, -1
374 ; CHECK-NEXT: and a4, a5, a4
375 ; CHECK-NEXT: srli a3, a3, 2
376 ; CHECK-NEXT: vl8re32.v v0, (a0)
377 ; CHECK-NEXT: addi a0, sp, 16
378 ; CHECK-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill
379 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
380 ; CHECK-NEXT: vslidedown.vx v0, v24, a3
381 ; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
382 ; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0
383 ; CHECK-NEXT: bltu a2, a1, .LBB27_2
384 ; CHECK-NEXT: # %bb.1:
385 ; CHECK-NEXT: mv a2, a1
386 ; CHECK-NEXT: .LBB27_2:
387 ; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
388 ; CHECK-NEXT: vmv1r.v v0, v24
389 ; CHECK-NEXT: csrr a0, vlenb
390 ; CHECK-NEXT: slli a0, a0, 3
391 ; CHECK-NEXT: add a0, sp, a0
392 ; CHECK-NEXT: addi a0, a0, 16
393 ; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
394 ; CHECK-NEXT: addi a0, sp, 16
395 ; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
396 ; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0
397 ; CHECK-NEXT: csrr a0, vlenb
398 ; CHECK-NEXT: slli a0, a0, 4
399 ; CHECK-NEXT: add sp, sp, a0
400 ; CHECK-NEXT: addi sp, sp, 16
402 %v = call <vscale x 32 x i32> @llvm.vp.select.nxv32i32(<vscale x 32 x i1> %a, <vscale x 32 x i32> %b, <vscale x 32 x i32> %c, i32 %evl)
403 ret <vscale x 32 x i32> %v
406 declare i32 @llvm.vscale.i32()
408 define <vscale x 32 x i32> @select_evl_nxv32i32(<vscale x 32 x i1> %a, <vscale x 32 x i32> %b, <vscale x 32 x i32> %c) {
409 ; CHECK-LABEL: select_evl_nxv32i32:
411 ; CHECK-NEXT: addi sp, sp, -16
412 ; CHECK-NEXT: .cfi_def_cfa_offset 16
413 ; CHECK-NEXT: csrr a1, vlenb
414 ; CHECK-NEXT: slli a1, a1, 4
415 ; CHECK-NEXT: sub sp, sp, a1
416 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
417 ; CHECK-NEXT: csrr a1, vlenb
418 ; CHECK-NEXT: slli a1, a1, 3
419 ; CHECK-NEXT: add a1, sp, a1
420 ; CHECK-NEXT: addi a1, a1, 16
421 ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
422 ; CHECK-NEXT: vmv1r.v v24, v0
423 ; CHECK-NEXT: csrr a1, vlenb
424 ; CHECK-NEXT: slli a2, a1, 3
425 ; CHECK-NEXT: add a2, a0, a2
426 ; CHECK-NEXT: vl8re32.v v8, (a2)
427 ; CHECK-NEXT: slli a2, a1, 1
428 ; CHECK-NEXT: sub a3, a1, a2
429 ; CHECK-NEXT: sltu a4, a1, a3
430 ; CHECK-NEXT: addi a4, a4, -1
431 ; CHECK-NEXT: and a3, a4, a3
432 ; CHECK-NEXT: srli a4, a1, 2
433 ; CHECK-NEXT: vl8re32.v v0, (a0)
434 ; CHECK-NEXT: addi a0, sp, 16
435 ; CHECK-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill
436 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
437 ; CHECK-NEXT: vslidedown.vx v0, v24, a4
438 ; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
439 ; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0
440 ; CHECK-NEXT: bltu a1, a2, .LBB28_2
441 ; CHECK-NEXT: # %bb.1:
442 ; CHECK-NEXT: mv a1, a2
443 ; CHECK-NEXT: .LBB28_2:
444 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
445 ; CHECK-NEXT: vmv1r.v v0, v24
446 ; CHECK-NEXT: csrr a0, vlenb
447 ; CHECK-NEXT: slli a0, a0, 3
448 ; CHECK-NEXT: add a0, sp, a0
449 ; CHECK-NEXT: addi a0, a0, 16
450 ; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
451 ; CHECK-NEXT: addi a0, sp, 16
452 ; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
453 ; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0
454 ; CHECK-NEXT: csrr a0, vlenb
455 ; CHECK-NEXT: slli a0, a0, 4
456 ; CHECK-NEXT: add sp, sp, a0
457 ; CHECK-NEXT: addi sp, sp, 16
459 %evl = call i32 @llvm.vscale.i32()
460 %evl0 = mul i32 %evl, 8
461 %v = call <vscale x 32 x i32> @llvm.vp.select.nxv32i32(<vscale x 32 x i1> %a, <vscale x 32 x i32> %b, <vscale x 32 x i32> %c, i32 %evl0)
462 ret <vscale x 32 x i32> %v
465 declare <vscale x 1 x i64> @llvm.vp.select.nxv1i64(<vscale x 1 x i1>, <vscale x 1 x i64>, <vscale x 1 x i64>, i32)
467 define <vscale x 1 x i64> @select_nxv1i64(<vscale x 1 x i1> %a, <vscale x 1 x i64> %b, <vscale x 1 x i64> %c, i32 zeroext %evl) {
468 ; CHECK-LABEL: select_nxv1i64:
470 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
471 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
473 %v = call <vscale x 1 x i64> @llvm.vp.select.nxv1i64(<vscale x 1 x i1> %a, <vscale x 1 x i64> %b, <vscale x 1 x i64> %c, i32 %evl)
474 ret <vscale x 1 x i64> %v
477 declare <vscale x 2 x i64> @llvm.vp.select.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>, i32)
479 define <vscale x 2 x i64> @select_nxv2i64(<vscale x 2 x i1> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, i32 zeroext %evl) {
480 ; CHECK-LABEL: select_nxv2i64:
482 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
483 ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
485 %v = call <vscale x 2 x i64> @llvm.vp.select.nxv2i64(<vscale x 2 x i1> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, i32 %evl)
486 ret <vscale x 2 x i64> %v
489 declare <vscale x 4 x i64> @llvm.vp.select.nxv4i64(<vscale x 4 x i1>, <vscale x 4 x i64>, <vscale x 4 x i64>, i32)
491 define <vscale x 4 x i64> @select_nxv4i64(<vscale x 4 x i1> %a, <vscale x 4 x i64> %b, <vscale x 4 x i64> %c, i32 zeroext %evl) {
492 ; CHECK-LABEL: select_nxv4i64:
494 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
495 ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
497 %v = call <vscale x 4 x i64> @llvm.vp.select.nxv4i64(<vscale x 4 x i1> %a, <vscale x 4 x i64> %b, <vscale x 4 x i64> %c, i32 %evl)
498 ret <vscale x 4 x i64> %v
501 declare <vscale x 8 x i64> @llvm.vp.select.nxv8i64(<vscale x 8 x i1>, <vscale x 8 x i64>, <vscale x 8 x i64>, i32)
503 define <vscale x 8 x i64> @select_nxv8i64(<vscale x 8 x i1> %a, <vscale x 8 x i64> %b, <vscale x 8 x i64> %c, i32 zeroext %evl) {
504 ; CHECK-LABEL: select_nxv8i64:
506 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
507 ; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
509 %v = call <vscale x 8 x i64> @llvm.vp.select.nxv8i64(<vscale x 8 x i1> %a, <vscale x 8 x i64> %b, <vscale x 8 x i64> %c, i32 %evl)
510 ret <vscale x 8 x i64> %v
513 declare <vscale x 1 x half> @llvm.vp.select.nxv1f16(<vscale x 1 x i1>, <vscale x 1 x half>, <vscale x 1 x half>, i32)
515 define <vscale x 1 x half> @select_nxv1f16(<vscale x 1 x i1> %a, <vscale x 1 x half> %b, <vscale x 1 x half> %c, i32 zeroext %evl) {
516 ; CHECK-LABEL: select_nxv1f16:
518 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
519 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
521 %v = call <vscale x 1 x half> @llvm.vp.select.nxv1f16(<vscale x 1 x i1> %a, <vscale x 1 x half> %b, <vscale x 1 x half> %c, i32 %evl)
522 ret <vscale x 1 x half> %v
525 declare <vscale x 2 x half> @llvm.vp.select.nxv2f16(<vscale x 2 x i1>, <vscale x 2 x half>, <vscale x 2 x half>, i32)
527 define <vscale x 2 x half> @select_nxv2f16(<vscale x 2 x i1> %a, <vscale x 2 x half> %b, <vscale x 2 x half> %c, i32 zeroext %evl) {
528 ; CHECK-LABEL: select_nxv2f16:
530 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
531 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
533 %v = call <vscale x 2 x half> @llvm.vp.select.nxv2f16(<vscale x 2 x i1> %a, <vscale x 2 x half> %b, <vscale x 2 x half> %c, i32 %evl)
534 ret <vscale x 2 x half> %v
537 declare <vscale x 4 x half> @llvm.vp.select.nxv4f16(<vscale x 4 x i1>, <vscale x 4 x half>, <vscale x 4 x half>, i32)
539 define <vscale x 4 x half> @select_nxv4f16(<vscale x 4 x i1> %a, <vscale x 4 x half> %b, <vscale x 4 x half> %c, i32 zeroext %evl) {
540 ; CHECK-LABEL: select_nxv4f16:
542 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
543 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
545 %v = call <vscale x 4 x half> @llvm.vp.select.nxv4f16(<vscale x 4 x i1> %a, <vscale x 4 x half> %b, <vscale x 4 x half> %c, i32 %evl)
546 ret <vscale x 4 x half> %v
549 declare <vscale x 8 x half> @llvm.vp.select.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>, i32)
551 define <vscale x 8 x half> @select_nxv8f16(<vscale x 8 x i1> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c, i32 zeroext %evl) {
552 ; CHECK-LABEL: select_nxv8f16:
554 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
555 ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
557 %v = call <vscale x 8 x half> @llvm.vp.select.nxv8f16(<vscale x 8 x i1> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c, i32 %evl)
558 ret <vscale x 8 x half> %v
561 declare <vscale x 16 x half> @llvm.vp.select.nxv16f16(<vscale x 16 x i1>, <vscale x 16 x half>, <vscale x 16 x half>, i32)
563 define <vscale x 16 x half> @select_nxv16f16(<vscale x 16 x i1> %a, <vscale x 16 x half> %b, <vscale x 16 x half> %c, i32 zeroext %evl) {
564 ; CHECK-LABEL: select_nxv16f16:
566 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
567 ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
569 %v = call <vscale x 16 x half> @llvm.vp.select.nxv16f16(<vscale x 16 x i1> %a, <vscale x 16 x half> %b, <vscale x 16 x half> %c, i32 %evl)
570 ret <vscale x 16 x half> %v
573 declare <vscale x 32 x half> @llvm.vp.select.nxv32f16(<vscale x 32 x i1>, <vscale x 32 x half>, <vscale x 32 x half>, i32)
575 define <vscale x 32 x half> @select_nxv32f16(<vscale x 32 x i1> %a, <vscale x 32 x half> %b, <vscale x 32 x half> %c, i32 zeroext %evl) {
576 ; CHECK-LABEL: select_nxv32f16:
578 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
579 ; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
581 %v = call <vscale x 32 x half> @llvm.vp.select.nxv32f16(<vscale x 32 x i1> %a, <vscale x 32 x half> %b, <vscale x 32 x half> %c, i32 %evl)
582 ret <vscale x 32 x half> %v
585 declare <vscale x 1 x float> @llvm.vp.select.nxv1f32(<vscale x 1 x i1>, <vscale x 1 x float>, <vscale x 1 x float>, i32)
587 define <vscale x 1 x float> @select_nxv1f32(<vscale x 1 x i1> %a, <vscale x 1 x float> %b, <vscale x 1 x float> %c, i32 zeroext %evl) {
588 ; CHECK-LABEL: select_nxv1f32:
590 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
591 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
593 %v = call <vscale x 1 x float> @llvm.vp.select.nxv1f32(<vscale x 1 x i1> %a, <vscale x 1 x float> %b, <vscale x 1 x float> %c, i32 %evl)
594 ret <vscale x 1 x float> %v
597 declare <vscale x 2 x float> @llvm.vp.select.nxv2f32(<vscale x 2 x i1>, <vscale x 2 x float>, <vscale x 2 x float>, i32)
599 define <vscale x 2 x float> @select_nxv2f32(<vscale x 2 x i1> %a, <vscale x 2 x float> %b, <vscale x 2 x float> %c, i32 zeroext %evl) {
600 ; CHECK-LABEL: select_nxv2f32:
602 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
603 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
605 %v = call <vscale x 2 x float> @llvm.vp.select.nxv2f32(<vscale x 2 x i1> %a, <vscale x 2 x float> %b, <vscale x 2 x float> %c, i32 %evl)
606 ret <vscale x 2 x float> %v
609 declare <vscale x 4 x float> @llvm.vp.select.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>, i32)
611 define <vscale x 4 x float> @select_nxv4f32(<vscale x 4 x i1> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, i32 zeroext %evl) {
612 ; CHECK-LABEL: select_nxv4f32:
614 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
615 ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
617 %v = call <vscale x 4 x float> @llvm.vp.select.nxv4f32(<vscale x 4 x i1> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, i32 %evl)
618 ret <vscale x 4 x float> %v
621 declare <vscale x 8 x float> @llvm.vp.select.nxv8f32(<vscale x 8 x i1>, <vscale x 8 x float>, <vscale x 8 x float>, i32)
623 define <vscale x 8 x float> @select_nxv8f32(<vscale x 8 x i1> %a, <vscale x 8 x float> %b, <vscale x 8 x float> %c, i32 zeroext %evl) {
624 ; CHECK-LABEL: select_nxv8f32:
626 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
627 ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
629 %v = call <vscale x 8 x float> @llvm.vp.select.nxv8f32(<vscale x 8 x i1> %a, <vscale x 8 x float> %b, <vscale x 8 x float> %c, i32 %evl)
630 ret <vscale x 8 x float> %v
633 declare <vscale x 16 x float> @llvm.vp.select.nxv16f32(<vscale x 16 x i1>, <vscale x 16 x float>, <vscale x 16 x float>, i32)
635 define <vscale x 16 x float> @select_nxv16f32(<vscale x 16 x i1> %a, <vscale x 16 x float> %b, <vscale x 16 x float> %c, i32 zeroext %evl) {
636 ; CHECK-LABEL: select_nxv16f32:
638 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
639 ; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
641 %v = call <vscale x 16 x float> @llvm.vp.select.nxv16f32(<vscale x 16 x i1> %a, <vscale x 16 x float> %b, <vscale x 16 x float> %c, i32 %evl)
642 ret <vscale x 16 x float> %v
645 declare <vscale x 1 x double> @llvm.vp.select.nxv1f64(<vscale x 1 x i1>, <vscale x 1 x double>, <vscale x 1 x double>, i32)
647 define <vscale x 1 x double> @select_nxv1f64(<vscale x 1 x i1> %a, <vscale x 1 x double> %b, <vscale x 1 x double> %c, i32 zeroext %evl) {
648 ; CHECK-LABEL: select_nxv1f64:
650 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
651 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
653 %v = call <vscale x 1 x double> @llvm.vp.select.nxv1f64(<vscale x 1 x i1> %a, <vscale x 1 x double> %b, <vscale x 1 x double> %c, i32 %evl)
654 ret <vscale x 1 x double> %v
657 declare <vscale x 2 x double> @llvm.vp.select.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>, i32)
659 define <vscale x 2 x double> @select_nxv2f64(<vscale x 2 x i1> %a, <vscale x 2 x double> %b, <vscale x 2 x double> %c, i32 zeroext %evl) {
660 ; CHECK-LABEL: select_nxv2f64:
662 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
663 ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
665 %v = call <vscale x 2 x double> @llvm.vp.select.nxv2f64(<vscale x 2 x i1> %a, <vscale x 2 x double> %b, <vscale x 2 x double> %c, i32 %evl)
666 ret <vscale x 2 x double> %v
669 declare <vscale x 4 x double> @llvm.vp.select.nxv4f64(<vscale x 4 x i1>, <vscale x 4 x double>, <vscale x 4 x double>, i32)
671 define <vscale x 4 x double> @select_nxv4f64(<vscale x 4 x i1> %a, <vscale x 4 x double> %b, <vscale x 4 x double> %c, i32 zeroext %evl) {
672 ; CHECK-LABEL: select_nxv4f64:
674 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
675 ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
677 %v = call <vscale x 4 x double> @llvm.vp.select.nxv4f64(<vscale x 4 x i1> %a, <vscale x 4 x double> %b, <vscale x 4 x double> %c, i32 %evl)
678 ret <vscale x 4 x double> %v
681 declare <vscale x 8 x double> @llvm.vp.select.nxv8f64(<vscale x 8 x i1>, <vscale x 8 x double>, <vscale x 8 x double>, i32)
683 define <vscale x 8 x double> @select_nxv8f64(<vscale x 8 x i1> %a, <vscale x 8 x double> %b, <vscale x 8 x double> %c, i32 zeroext %evl) {
684 ; CHECK-LABEL: select_nxv8f64:
686 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
687 ; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
689 %v = call <vscale x 8 x double> @llvm.vp.select.nxv8f64(<vscale x 8 x i1> %a, <vscale x 8 x double> %b, <vscale x 8 x double> %c, i32 %evl)
690 ret <vscale x 8 x double> %v
693 declare <vscale x 16 x double> @llvm.vp.select.nxv16f64(<vscale x 16 x i1>, <vscale x 16 x double>, <vscale x 16 x double>, i32)
695 define <vscale x 16 x double> @select_nxv16f64(<vscale x 16 x i1> %a, <vscale x 16 x double> %b, <vscale x 16 x double> %c, i32 zeroext %evl) {
696 ; CHECK-LABEL: select_nxv16f64:
698 ; CHECK-NEXT: addi sp, sp, -16
699 ; CHECK-NEXT: .cfi_def_cfa_offset 16
700 ; CHECK-NEXT: csrr a1, vlenb
701 ; CHECK-NEXT: slli a1, a1, 4
702 ; CHECK-NEXT: sub sp, sp, a1
703 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
704 ; CHECK-NEXT: csrr a1, vlenb
705 ; CHECK-NEXT: slli a1, a1, 3
706 ; CHECK-NEXT: add a1, sp, a1
707 ; CHECK-NEXT: addi a1, a1, 16
708 ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
709 ; CHECK-NEXT: vmv1r.v v24, v0
710 ; CHECK-NEXT: csrr a1, vlenb
711 ; CHECK-NEXT: slli a3, a1, 3
712 ; CHECK-NEXT: add a3, a0, a3
713 ; CHECK-NEXT: vl8re64.v v8, (a3)
714 ; CHECK-NEXT: sub a3, a2, a1
715 ; CHECK-NEXT: sltu a4, a2, a3
716 ; CHECK-NEXT: addi a4, a4, -1
717 ; CHECK-NEXT: and a3, a4, a3
718 ; CHECK-NEXT: srli a4, a1, 3
719 ; CHECK-NEXT: vl8re64.v v0, (a0)
720 ; CHECK-NEXT: addi a0, sp, 16
721 ; CHECK-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill
722 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
723 ; CHECK-NEXT: vslidedown.vx v0, v24, a4
724 ; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
725 ; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0
726 ; CHECK-NEXT: bltu a2, a1, .LBB48_2
727 ; CHECK-NEXT: # %bb.1:
728 ; CHECK-NEXT: mv a2, a1
729 ; CHECK-NEXT: .LBB48_2:
730 ; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
731 ; CHECK-NEXT: vmv1r.v v0, v24
732 ; CHECK-NEXT: csrr a0, vlenb
733 ; CHECK-NEXT: slli a0, a0, 3
734 ; CHECK-NEXT: add a0, sp, a0
735 ; CHECK-NEXT: addi a0, a0, 16
736 ; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
737 ; CHECK-NEXT: addi a0, sp, 16
738 ; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
739 ; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0
740 ; CHECK-NEXT: csrr a0, vlenb
741 ; CHECK-NEXT: slli a0, a0, 4
742 ; CHECK-NEXT: add sp, sp, a0
743 ; CHECK-NEXT: addi sp, sp, 16
745 %v = call <vscale x 16 x double> @llvm.vp.select.nxv16f64(<vscale x 16 x i1> %a, <vscale x 16 x double> %b, <vscale x 16 x double> %c, i32 %evl)
746 ret <vscale x 16 x double> %v