1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
6 source_filename = "urem.ll"
7 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
9 define i8 @test_urem_i8(i8 %arg1, i8 %arg2) {
10 %res = urem i8 %arg1, %arg2
14 define i16 @test_urem_i16(i16 %arg1, i16 %arg2) {
15 %res = urem i16 %arg1, %arg2
19 define i32 @test_urem_i32(i32 %arg1, i32 %arg2) {
20 %res = urem i32 %arg1, %arg2
24 define i64 @test_urem_i64(i64 %arg1, i64 %arg2) {
25 %res = urem i64 %arg1, %arg2
33 exposesReturnsTwice: false
38 tracksRegLiveness: true
40 - { id: 0, class: gpr, preferred-register: '' }
41 - { id: 1, class: gpr, preferred-register: '' }
42 - { id: 2, class: gpr, preferred-register: '' }
43 - { id: 3, class: gpr, preferred-register: '' }
44 - { id: 4, class: gpr, preferred-register: '' }
47 isFrameAddressTaken: false
48 isReturnAddressTaken: false
57 maxCallFrameSize: 4294967295
58 hasOpaqueSPAdjustment: false
60 hasMustTailInVarArgFunc: false
71 ; CHECK-LABEL: name: test_urem_i8
72 ; CHECK: liveins: $edi, $esi
74 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
75 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
76 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY $esi
77 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY2]].sub_8bit
78 ; CHECK-NEXT: $ax = MOVZX16rr8 [[COPY1]]
79 ; CHECK-NEXT: DIV8r [[COPY3]], implicit-def $al, implicit-def $ah, implicit-def $eflags, implicit $ax
80 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr16 = COPY $ax
81 ; CHECK-NEXT: [[SHR16ri:%[0-9]+]]:gr16 = SHR16ri [[COPY4]], 8, implicit-def $eflags
82 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr8 = SUBREG_TO_REG 0, [[SHR16ri]], %subreg.sub_8bit
83 ; CHECK-NEXT: $al = COPY [[SUBREG_TO_REG]]
84 ; CHECK-NEXT: RET 0, implicit $al
85 %2:gpr(s32) = COPY $edi
86 %0:gpr(s8) = G_TRUNC %2(s32)
87 %3:gpr(s32) = COPY $esi
88 %1:gpr(s8) = G_TRUNC %3(s32)
89 %4:gpr(s8) = G_UREM %0, %1
97 exposesReturnsTwice: false
102 tracksRegLiveness: true
104 - { id: 0, class: gpr, preferred-register: '' }
105 - { id: 1, class: gpr, preferred-register: '' }
106 - { id: 2, class: gpr, preferred-register: '' }
107 - { id: 3, class: gpr, preferred-register: '' }
108 - { id: 4, class: gpr, preferred-register: '' }
111 isFrameAddressTaken: false
112 isReturnAddressTaken: false
121 maxCallFrameSize: 4294967295
122 hasOpaqueSPAdjustment: false
124 hasMustTailInVarArgFunc: false
135 ; CHECK-LABEL: name: test_urem_i16
136 ; CHECK: liveins: $edi, $esi
138 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
139 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
140 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY $esi
141 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr16 = COPY [[COPY2]].sub_16bit
142 ; CHECK-NEXT: $ax = COPY [[COPY1]]
143 ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
144 ; CHECK-NEXT: $dx = COPY [[MOV32r0_]].sub_16bit
145 ; CHECK-NEXT: DIV16r [[COPY3]], implicit-def $ax, implicit-def $dx, implicit-def $eflags, implicit $ax, implicit $dx
146 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr16 = COPY $dx
147 ; CHECK-NEXT: $ax = COPY [[COPY4]]
148 ; CHECK-NEXT: RET 0, implicit $ax
149 %2:gpr(s32) = COPY $edi
150 %0:gpr(s16) = G_TRUNC %2(s32)
151 %3:gpr(s32) = COPY $esi
152 %1:gpr(s16) = G_TRUNC %3(s32)
153 %4:gpr(s16) = G_UREM %0, %1
161 exposesReturnsTwice: false
163 regBankSelected: true
166 tracksRegLiveness: true
168 - { id: 0, class: gpr, preferred-register: '' }
169 - { id: 1, class: gpr, preferred-register: '' }
170 - { id: 2, class: gpr, preferred-register: '' }
173 isFrameAddressTaken: false
174 isReturnAddressTaken: false
183 maxCallFrameSize: 4294967295
184 hasOpaqueSPAdjustment: false
186 hasMustTailInVarArgFunc: false
197 ; CHECK-LABEL: name: test_urem_i32
198 ; CHECK: liveins: $edi, $esi
200 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
201 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
202 ; CHECK-NEXT: $eax = COPY [[COPY]]
203 ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
204 ; CHECK-NEXT: $edx = COPY [[MOV32r0_]]
205 ; CHECK-NEXT: DIV32r [[COPY1]], implicit-def $eax, implicit-def $edx, implicit-def $eflags, implicit $eax, implicit $edx
206 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY $edx
207 ; CHECK-NEXT: $eax = COPY [[COPY2]]
208 ; CHECK-NEXT: RET 0, implicit $eax
209 %0:gpr(s32) = COPY $edi
210 %1:gpr(s32) = COPY $esi
211 %2:gpr(s32) = G_UREM %0, %1
219 exposesReturnsTwice: false
221 regBankSelected: true
224 tracksRegLiveness: true
226 - { id: 0, class: gpr, preferred-register: '' }
227 - { id: 1, class: gpr, preferred-register: '' }
228 - { id: 2, class: gpr, preferred-register: '' }
231 isFrameAddressTaken: false
232 isReturnAddressTaken: false
241 maxCallFrameSize: 4294967295
242 hasOpaqueSPAdjustment: false
244 hasMustTailInVarArgFunc: false
255 ; CHECK-LABEL: name: test_urem_i64
256 ; CHECK: liveins: $rdi, $rsi
258 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
259 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
260 ; CHECK-NEXT: $rax = COPY [[COPY]]
261 ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
262 ; CHECK-NEXT: $rdx = SUBREG_TO_REG 0, [[MOV32r0_]], %subreg.sub_32bit
263 ; CHECK-NEXT: DIV64r [[COPY1]], implicit-def $rax, implicit-def $rdx, implicit-def $eflags, implicit $rax, implicit $rdx
264 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY $rdx
265 ; CHECK-NEXT: $rax = COPY [[COPY2]]
266 ; CHECK-NEXT: RET 0, implicit $rax
267 %0:gpr(s64) = COPY $rdi
268 %1:gpr(s64) = COPY $rsi
269 %2:gpr(s64) = G_UREM %0, %1