| blob | a05da63e43e12eaea617fe886ba8a03b892922e5 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE,SSE2
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE,SSE41
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX-SLOW
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+fast-variable-crosslane-shuffle,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=CHECK,AVX,AVX-FAST-ALL
6 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=CHECK,AVX,AVX-FAST-PERLANE
8 ; fold (shl 0, x) -> 0
9 define <4 x i32> @combine_vec_shl_zero(<4 x i32> %x) {
10 ; SSE-LABEL: combine_vec_shl_zero:
11 ; SSE: # %bb.0:
12 ; SSE-NEXT: xorps %xmm0, %xmm0
13 ; SSE-NEXT: retq
14 ;
15 ; AVX-LABEL: combine_vec_shl_zero:
16 ; AVX: # %bb.0:
17 ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
18 ; AVX-NEXT: retq
19 %1 = shl <4 x i32> zeroinitializer, %x
20 ret <4 x i32> %1
21 }
23 ; fold (shl x, c >= size(x)) -> undef
24 define <4 x i32> @combine_vec_shl_outofrange0(<4 x i32> %x) {
25 ; CHECK-LABEL: combine_vec_shl_outofrange0:
26 ; CHECK: # %bb.0:
27 ; CHECK-NEXT: retq
28 %1 = shl <4 x i32> %x, <i32 33, i32 33, i32 33, i32 33>
29 ret <4 x i32> %1
30 }
32 define <4 x i32> @combine_vec_shl_outofrange1(<4 x i32> %x) {
33 ; CHECK-LABEL: combine_vec_shl_outofrange1:
34 ; CHECK: # %bb.0:
35 ; CHECK-NEXT: retq
36 %1 = shl <4 x i32> %x, <i32 33, i32 34, i32 35, i32 36>
37 ret <4 x i32> %1
38 }
40 define <4 x i32> @combine_vec_shl_outofrange2(<4 x i32> %a0) {
41 ; CHECK-LABEL: combine_vec_shl_outofrange2:
42 ; CHECK: # %bb.0:
43 ; CHECK-NEXT: retq
44 %1 = and <4 x i32> %a0, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
45 %2 = shl <4 x i32> %1, <i32 33, i32 33, i32 33, i32 33>
46 ret <4 x i32> %2
47 }
49 define <4 x i32> @combine_vec_shl_outofrange3(<4 x i32> %a0) {
50 ; CHECK-LABEL: combine_vec_shl_outofrange3:
51 ; CHECK: # %bb.0:
52 ; CHECK-NEXT: retq
53 %1 = shl <4 x i32> %a0, <i32 33, i32 34, i32 35, i32 undef>
54 ret <4 x i32> %1
55 }
57 ; fold (shl x, 0) -> x
58 define <4 x i32> @combine_vec_shl_by_zero(<4 x i32> %x) {
59 ; CHECK-LABEL: combine_vec_shl_by_zero:
60 ; CHECK: # %bb.0:
61 ; CHECK-NEXT: retq
62 %1 = shl <4 x i32> %x, zeroinitializer
63 ret <4 x i32> %1
64 }
66 ; if (shl x, c) is known to be zero, return 0
67 define <4 x i32> @combine_vec_shl_known_zero0(<4 x i32> %x) {
68 ; SSE-LABEL: combine_vec_shl_known_zero0:
69 ; SSE: # %bb.0:
70 ; SSE-NEXT: xorps %xmm0, %xmm0
71 ; SSE-NEXT: retq
72 ;
73 ; AVX-LABEL: combine_vec_shl_known_zero0:
74 ; AVX: # %bb.0:
75 ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
76 ; AVX-NEXT: retq
77 %1 = and <4 x i32> %x, <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>
78 %2 = shl <4 x i32> %1, <i32 16, i32 16, i32 16, i32 16>
79 ret <4 x i32> %2
80 }
82 define <4 x i32> @combine_vec_shl_known_zero1(<4 x i32> %x) {
83 ; SSE2-LABEL: combine_vec_shl_known_zero1:
84 ; SSE2: # %bb.0:
85 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
86 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65536,32768,16384,8192]
87 ; SSE2-NEXT: pmuludq %xmm0, %xmm1
88 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
89 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
90 ; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
91 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
92 ; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
93 ; SSE2-NEXT: movdqa %xmm1, %xmm0
94 ; SSE2-NEXT: retq
95 ;
96 ; SSE41-LABEL: combine_vec_shl_known_zero1:
97 ; SSE41: # %bb.0:
98 ; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
99 ; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
100 ; SSE41-NEXT: retq
101 ;
102 ; AVX-LABEL: combine_vec_shl_known_zero1:
103 ; AVX: # %bb.0:
104 ; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
105 ; AVX-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
106 ; AVX-NEXT: retq
107 %1 = and <4 x i32> %x, <i32 4294901760, i32 8589803520, i32 17179607040, i32 34359214080>
108 %2 = shl <4 x i32> %1, <i32 16, i32 15, i32 14, i32 13>
109 ret <4 x i32> %2
110 }
112 ; fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
113 define <4 x i32> @combine_vec_shl_trunc_and(<4 x i32> %x, <4 x i64> %y) {
114 ; SSE2-LABEL: combine_vec_shl_trunc_and:
115 ; SSE2: # %bb.0:
116 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2]
117 ; SSE2-NEXT: pslld $23, %xmm1
118 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
119 ; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
120 ; SSE2-NEXT: cvttps2dq %xmm1, %xmm1
121 ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
122 ; SSE2-NEXT: pmuludq %xmm1, %xmm0
123 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
124 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
125 ; SSE2-NEXT: pmuludq %xmm2, %xmm1
126 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
127 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
128 ; SSE2-NEXT: retq
129 ;
130 ; SSE41-LABEL: combine_vec_shl_trunc_and:
131 ; SSE41: # %bb.0:
132 ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2]
133 ; SSE41-NEXT: pslld $23, %xmm1
134 ; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
135 ; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
136 ; SSE41-NEXT: cvttps2dq %xmm1, %xmm1
137 ; SSE41-NEXT: pmulld %xmm1, %xmm0
138 ; SSE41-NEXT: retq
139 ;
140 ; AVX-SLOW-LABEL: combine_vec_shl_trunc_and:
141 ; AVX-SLOW: # %bb.0:
142 ; AVX-SLOW-NEXT: vextractf128 $1, %ymm1, %xmm2
143 ; AVX-SLOW-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2]
144 ; AVX-SLOW-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
145 ; AVX-SLOW-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
146 ; AVX-SLOW-NEXT: vzeroupper
147 ; AVX-SLOW-NEXT: retq
148 ;
149 ; AVX-FAST-ALL-LABEL: combine_vec_shl_trunc_and:
150 ; AVX-FAST-ALL: # %bb.0:
151 ; AVX-FAST-ALL-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [0,2,4,6,0,2,4,6]
152 ; AVX-FAST-ALL-NEXT: # ymm2 = mem[0,1,0,1]
153 ; AVX-FAST-ALL-NEXT: vpermd %ymm1, %ymm2, %ymm1
154 ; AVX-FAST-ALL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
155 ; AVX-FAST-ALL-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
156 ; AVX-FAST-ALL-NEXT: vzeroupper
157 ; AVX-FAST-ALL-NEXT: retq
158 ;
159 ; AVX-FAST-PERLANE-LABEL: combine_vec_shl_trunc_and:
160 ; AVX-FAST-PERLANE: # %bb.0:
161 ; AVX-FAST-PERLANE-NEXT: vextractf128 $1, %ymm1, %xmm2
162 ; AVX-FAST-PERLANE-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2]
163 ; AVX-FAST-PERLANE-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
164 ; AVX-FAST-PERLANE-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
165 ; AVX-FAST-PERLANE-NEXT: vzeroupper
166 ; AVX-FAST-PERLANE-NEXT: retq
167 %1 = and <4 x i64> %y, <i64 15, i64 255, i64 4095, i64 65535>
168 %2 = trunc <4 x i64> %1 to <4 x i32>
169 %3 = shl <4 x i32> %x, %2
170 ret <4 x i32> %3
171 }
173 ; fold (shl (shl x, c1), c2) -> (shl x, (add c1, c2))
174 define <4 x i32> @combine_vec_shl_shl0(<4 x i32> %x) {
175 ; SSE-LABEL: combine_vec_shl_shl0:
176 ; SSE: # %bb.0:
177 ; SSE-NEXT: pslld $6, %xmm0
178 ; SSE-NEXT: retq
179 ;
180 ; AVX-LABEL: combine_vec_shl_shl0:
181 ; AVX: # %bb.0:
182 ; AVX-NEXT: vpslld $6, %xmm0, %xmm0
183 ; AVX-NEXT: retq
184 %1 = shl <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2>
185 %2 = shl <4 x i32> %1, <i32 4, i32 4, i32 4, i32 4>
186 ret <4 x i32> %2
187 }
189 define <4 x i32> @combine_vec_shl_shl1(<4 x i32> %x) {
190 ; SSE2-LABEL: combine_vec_shl_shl1:
191 ; SSE2: # %bb.0:
192 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
193 ; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
194 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
195 ; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
196 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
197 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
198 ; SSE2-NEXT: retq
199 ;
200 ; SSE41-LABEL: combine_vec_shl_shl1:
201 ; SSE41: # %bb.0:
202 ; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
203 ; SSE41-NEXT: retq
204 ;
205 ; AVX-LABEL: combine_vec_shl_shl1:
206 ; AVX: # %bb.0:
207 ; AVX-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
208 ; AVX-NEXT: retq
209 %1 = shl <4 x i32> %x, <i32 0, i32 1, i32 2, i32 3>
210 %2 = shl <4 x i32> %1, <i32 4, i32 5, i32 6, i32 7>
211 ret <4 x i32> %2
212 }
214 ; fold (shl (shl x, c1), c2) -> 0
215 define <4 x i32> @combine_vec_shl_shlr_zero0(<4 x i32> %x) {
216 ; SSE-LABEL: combine_vec_shl_shlr_zero0:
217 ; SSE: # %bb.0:
218 ; SSE-NEXT: xorps %xmm0, %xmm0
219 ; SSE-NEXT: retq
220 ;
221 ; AVX-LABEL: combine_vec_shl_shlr_zero0:
222 ; AVX: # %bb.0:
223 ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
224 ; AVX-NEXT: retq
225 %1 = shl <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>
226 %2 = shl <4 x i32> %1, <i32 20, i32 20, i32 20, i32 20>
227 ret <4 x i32> %2
228 }
230 define <4 x i32> @combine_vec_shl_shl_zero1(<4 x i32> %x) {
231 ; SSE-LABEL: combine_vec_shl_shl_zero1:
232 ; SSE: # %bb.0:
233 ; SSE-NEXT: xorps %xmm0, %xmm0
234 ; SSE-NEXT: retq
235 ;
236 ; AVX-LABEL: combine_vec_shl_shl_zero1:
237 ; AVX: # %bb.0:
238 ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
239 ; AVX-NEXT: retq
240 %1 = shl <4 x i32> %x, <i32 17, i32 18, i32 19, i32 20>
241 %2 = shl <4 x i32> %1, <i32 25, i32 26, i32 27, i32 28>
242 ret <4 x i32> %2
243 }
245 ; fold (shl (ext (shl x, c1)), c2) -> (shl (ext x), (add c1, c2))
246 define <8 x i32> @combine_vec_shl_ext_shl0(<8 x i16> %x) {
247 ; SSE2-LABEL: combine_vec_shl_ext_shl0:
248 ; SSE2: # %bb.0:
249 ; SSE2-NEXT: movdqa %xmm0, %xmm1
250 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
251 ; SSE2-NEXT: pslld $20, %xmm0
252 ; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
253 ; SSE2-NEXT: pslld $20, %xmm1
254 ; SSE2-NEXT: retq
255 ;
256 ; SSE41-LABEL: combine_vec_shl_ext_shl0:
257 ; SSE41: # %bb.0:
258 ; SSE41-NEXT: movdqa %xmm0, %xmm1
259 ; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
260 ; SSE41-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
261 ; SSE41-NEXT: pslld $20, %xmm1
262 ; SSE41-NEXT: pslld $20, %xmm0
263 ; SSE41-NEXT: retq
264 ;
265 ; AVX-LABEL: combine_vec_shl_ext_shl0:
266 ; AVX: # %bb.0:
267 ; AVX-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
268 ; AVX-NEXT: vpslld $20, %ymm0, %ymm0
269 ; AVX-NEXT: retq
270 %1 = shl <8 x i16> %x, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
271 %2 = sext <8 x i16> %1 to <8 x i32>
272 %3 = shl <8 x i32> %2, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
273 ret <8 x i32> %3
274 }
276 define <8 x i32> @combine_vec_shl_ext_shl1(<8 x i16> %x) {
277 ; SSE-LABEL: combine_vec_shl_ext_shl1:
278 ; SSE: # %bb.0:
279 ; SSE-NEXT: xorps %xmm0, %xmm0
280 ; SSE-NEXT: xorps %xmm1, %xmm1
281 ; SSE-NEXT: retq
282 ;
283 ; AVX-LABEL: combine_vec_shl_ext_shl1:
284 ; AVX: # %bb.0:
285 ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
286 ; AVX-NEXT: retq
287 %1 = shl <8 x i16> %x, <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>
288 %2 = sext <8 x i16> %1 to <8 x i32>
289 %3 = shl <8 x i32> %2, <i32 31, i32 31, i32 30, i32 30, i32 29, i32 29, i32 28, i32 28>
290 ret <8 x i32> %3
291 }
293 define <8 x i32> @combine_vec_shl_ext_shl2(<8 x i16> %x) {
294 ; SSE2-LABEL: combine_vec_shl_ext_shl2:
295 ; SSE2: # %bb.0:
296 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
297 ; SSE2-NEXT: psrad $16, %xmm1
298 ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
299 ; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
300 ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[0,2,2,3]
301 ; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
302 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[0,2,2,3]
303 ; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
304 ; SSE2-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4,4,5,5,6,6,7,7]
305 ; SSE2-NEXT: psrad $16, %xmm0
306 ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
307 ; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
308 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,2,2,3]
309 ; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
310 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3]
311 ; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
312 ; SSE2-NEXT: movdqa %xmm2, %xmm0
313 ; SSE2-NEXT: retq
314 ;
315 ; SSE41-LABEL: combine_vec_shl_ext_shl2:
316 ; SSE41: # %bb.0:
317 ; SSE41-NEXT: pmovsxwd %xmm0, %xmm2
318 ; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
319 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
320 ; SSE41-NEXT: pmovsxwd %xmm0, %xmm1
321 ; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
322 ; SSE41-NEXT: movdqa %xmm2, %xmm0
323 ; SSE41-NEXT: retq
324 ;
325 ; AVX-LABEL: combine_vec_shl_ext_shl2:
326 ; AVX: # %bb.0:
327 ; AVX-NEXT: vpmovsxwd %xmm0, %ymm0
328 ; AVX-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
329 ; AVX-NEXT: retq
330 %1 = shl <8 x i16> %x, <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>
331 %2 = sext <8 x i16> %1 to <8 x i32>
332 %3 = shl <8 x i32> %2, <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
333 ret <8 x i32> %3
334 }
336 ; fold (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), C))
337 define <8 x i32> @combine_vec_shl_zext_lshr0(<8 x i16> %x) {
338 ; SSE2-LABEL: combine_vec_shl_zext_lshr0:
339 ; SSE2: # %bb.0:
340 ; SSE2-NEXT: movdqa %xmm0, %xmm1
341 ; SSE2-NEXT: pxor %xmm2, %xmm2
342 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
343 ; SSE2-NEXT: movdqa %xmm1, %xmm0
344 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
345 ; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
346 ; SSE2-NEXT: retq
347 ;
348 ; SSE41-LABEL: combine_vec_shl_zext_lshr0:
349 ; SSE41: # %bb.0:
350 ; SSE41-NEXT: movdqa %xmm0, %xmm1
351 ; SSE41-NEXT: pxor %xmm2, %xmm2
352 ; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
353 ; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
354 ; SSE41-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
355 ; SSE41-NEXT: retq
356 ;
357 ; AVX-LABEL: combine_vec_shl_zext_lshr0:
358 ; AVX: # %bb.0:
359 ; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
360 ; AVX-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
361 ; AVX-NEXT: retq
362 %1 = lshr <8 x i16> %x, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
363 %2 = zext <8 x i16> %1 to <8 x i32>
364 %3 = shl <8 x i32> %2, <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4>
365 ret <8 x i32> %3
366 }
368 define <8 x i32> @combine_vec_shl_zext_lshr1(<8 x i16> %x) {
369 ; SSE2-LABEL: combine_vec_shl_zext_lshr1:
370 ; SSE2: # %bb.0:
371 ; SSE2-NEXT: movdqa %xmm0, %xmm1
372 ; SSE2-NEXT: pxor %xmm2, %xmm2
373 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
374 ; SSE2-NEXT: movdqa %xmm1, %xmm0
375 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
376 ; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
377 ; SSE2-NEXT: retq
378 ;
379 ; SSE41-LABEL: combine_vec_shl_zext_lshr1:
380 ; SSE41: # %bb.0:
381 ; SSE41-NEXT: movdqa %xmm0, %xmm1
382 ; SSE41-NEXT: pxor %xmm2, %xmm2
383 ; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
384 ; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
385 ; SSE41-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
386 ; SSE41-NEXT: retq
387 ;
388 ; AVX-LABEL: combine_vec_shl_zext_lshr1:
389 ; AVX: # %bb.0:
390 ; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
391 ; AVX-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
392 ; AVX-NEXT: retq
393 %1 = lshr <8 x i16> %x, <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 15>
394 %2 = zext <8 x i16> %1 to <8 x i32>
395 %3 = shl <8 x i32> %2, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 15>
396 ret <8 x i32> %3
397 }
399 ; fold (shl (sr[la] exact X, C1), C2) -> (shl X, (C2-C1)) if C1 <= C2
400 define <4 x i32> @combine_vec_shl_ge_ashr_exact0(<4 x i32> %x) {
401 ; SSE-LABEL: combine_vec_shl_ge_ashr_exact0:
402 ; SSE: # %bb.0:
403 ; SSE-NEXT: pslld $2, %xmm0
404 ; SSE-NEXT: retq
405 ;
406 ; AVX-LABEL: combine_vec_shl_ge_ashr_exact0:
407 ; AVX: # %bb.0:
408 ; AVX-NEXT: vpslld $2, %xmm0, %xmm0
409 ; AVX-NEXT: retq
410 %1 = ashr exact <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>
411 %2 = shl <4 x i32> %1, <i32 5, i32 5, i32 5, i32 5>
412 ret <4 x i32> %2
413 }
415 define <4 x i32> @combine_vec_shl_ge_ashr_exact1(<4 x i32> %x) {
416 ; SSE2-LABEL: combine_vec_shl_ge_ashr_exact1:
417 ; SSE2: # %bb.0:
418 ; SSE2-NEXT: movdqa %xmm0, %xmm1
419 ; SSE2-NEXT: pslld $2, %xmm1
420 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[2,0]
421 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
422 ; SSE2-NEXT: movaps %xmm1, %xmm0
423 ; SSE2-NEXT: retq
424 ;
425 ; SSE41-LABEL: combine_vec_shl_ge_ashr_exact1:
426 ; SSE41: # %bb.0:
427 ; SSE41-NEXT: movdqa %xmm0, %xmm1
428 ; SSE41-NEXT: pslld $2, %xmm1
429 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
430 ; SSE41-NEXT: retq
431 ;
432 ; AVX-LABEL: combine_vec_shl_ge_ashr_exact1:
433 ; AVX: # %bb.0:
434 ; AVX-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
435 ; AVX-NEXT: retq
436 %1 = ashr exact <4 x i32> %x, <i32 3, i32 4, i32 5, i32 8>
437 %2 = shl <4 x i32> %1, <i32 5, i32 6, i32 7, i32 8>
438 ret <4 x i32> %2
439 }
441 ; fold (shl (sr[la] exact SEL(X,Y), C1), C2) -> (shl SEL(X,Y), (C2-C1)) if C1 <= C2
442 define i32 @combine_shl_ge_sel_ashr_exact0(i32 %x, i32 %y, i32 %z) {
443 ; CHECK-LABEL: combine_shl_ge_sel_ashr_exact0:
444 ; CHECK: # %bb.0:
445 ; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
446 ; CHECK-NEXT: testl %edx, %edx
447 ; CHECK-NEXT: cmovel %esi, %edi
448 ; CHECK-NEXT: leal (,%rdi,4), %eax
449 ; CHECK-NEXT: retq
450 %cmp = icmp ne i32 %z, 0
451 %ashrx = ashr exact i32 %x, 3
452 %ashry = ashr exact i32 %y, 3
453 %sel = select i1 %cmp, i32 %ashrx, i32 %ashry
454 %shl = shl i32 %sel, 5
455 ret i32 %shl
456 }
458 ; fold (shl (sr[la] exact X, C1), C2) -> (sr[la] X, (C2-C1)) if C1 > C2
459 define <4 x i32> @combine_vec_shl_lt_ashr_exact0(<4 x i32> %x) {
460 ; SSE-LABEL: combine_vec_shl_lt_ashr_exact0:
461 ; SSE: # %bb.0:
462 ; SSE-NEXT: psrad $2, %xmm0
463 ; SSE-NEXT: retq
464 ;
465 ; AVX-LABEL: combine_vec_shl_lt_ashr_exact0:
466 ; AVX: # %bb.0:
467 ; AVX-NEXT: vpsrad $2, %xmm0, %xmm0
468 ; AVX-NEXT: retq
469 %1 = ashr exact <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>
470 %2 = shl <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>
471 ret <4 x i32> %2
472 }
474 define <4 x i32> @combine_vec_shl_lt_ashr_exact1(<4 x i32> %x) {
475 ; SSE2-LABEL: combine_vec_shl_lt_ashr_exact1:
476 ; SSE2: # %bb.0:
477 ; SSE2-NEXT: movdqa %xmm0, %xmm1
478 ; SSE2-NEXT: psrad $2, %xmm1
479 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[2,0]
480 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
481 ; SSE2-NEXT: movaps %xmm1, %xmm0
482 ; SSE2-NEXT: retq
483 ;
484 ; SSE41-LABEL: combine_vec_shl_lt_ashr_exact1:
485 ; SSE41: # %bb.0:
486 ; SSE41-NEXT: movdqa %xmm0, %xmm1
487 ; SSE41-NEXT: psrad $2, %xmm1
488 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
489 ; SSE41-NEXT: retq
490 ;
491 ; AVX-LABEL: combine_vec_shl_lt_ashr_exact1:
492 ; AVX: # %bb.0:
493 ; AVX-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
494 ; AVX-NEXT: retq
495 %1 = ashr exact <4 x i32> %x, <i32 5, i32 6, i32 7, i32 8>
496 %2 = shl <4 x i32> %1, <i32 3, i32 4, i32 5, i32 8>
497 ret <4 x i32> %2
498 }
500 ; fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) if C2 > C1
501 define <4 x i32> @combine_vec_shl_gt_lshr0(<4 x i32> %x) {
502 ; SSE-LABEL: combine_vec_shl_gt_lshr0:
503 ; SSE: # %bb.0:
504 ; SSE-NEXT: pslld $2, %xmm0
505 ; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
506 ; SSE-NEXT: retq
507 ;
508 ; AVX-LABEL: combine_vec_shl_gt_lshr0:
509 ; AVX: # %bb.0:
510 ; AVX-NEXT: vpslld $2, %xmm0, %xmm0
511 ; AVX-NEXT: vpbroadcastd {{.*#+}} xmm1 = [4294967264,4294967264,4294967264,4294967264]
512 ; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
513 ; AVX-NEXT: retq
514 %1 = lshr <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>
515 %2 = shl <4 x i32> %1, <i32 5, i32 5, i32 5, i32 5>
516 ret <4 x i32> %2
517 }
519 define <4 x i32> @combine_vec_shl_gt_lshr1(<4 x i32> %x) {
520 ; SSE-LABEL: combine_vec_shl_gt_lshr1:
521 ; SSE: # %bb.0:
522 ; SSE-NEXT: pslld $2, %xmm0
523 ; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
524 ; SSE-NEXT: retq
525 ;
526 ; AVX-LABEL: combine_vec_shl_gt_lshr1:
527 ; AVX: # %bb.0:
528 ; AVX-NEXT: vpslld $2, %xmm0, %xmm0
529 ; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
530 ; AVX-NEXT: retq
531 %1 = lshr <4 x i32> %x, <i32 3, i32 4, i32 5, i32 29>
532 %2 = shl <4 x i32> %1, <i32 5, i32 6, i32 7, i32 31>
533 ret <4 x i32> %2
534 }
536 ; fold (shl (srl x, c1), c2) -> (and (srl x, (sub c1, c2), MASK) if C1 >= C2
537 define <4 x i32> @combine_vec_shl_le_lshr0(<4 x i32> %x) {
538 ; SSE-LABEL: combine_vec_shl_le_lshr0:
539 ; SSE: # %bb.0:
540 ; SSE-NEXT: psrld $2, %xmm0
541 ; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
542 ; SSE-NEXT: retq
543 ;
544 ; AVX-LABEL: combine_vec_shl_le_lshr0:
545 ; AVX: # %bb.0:
546 ; AVX-NEXT: vpsrld $2, %xmm0, %xmm0
547 ; AVX-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1073741816,1073741816,1073741816,1073741816]
548 ; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
549 ; AVX-NEXT: retq
550 %1 = lshr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>
551 %2 = shl <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>
552 ret <4 x i32> %2
553 }
555 define <4 x i32> @combine_vec_shl_le_lshr1(<4 x i32> %x) {
556 ; SSE2-LABEL: combine_vec_shl_le_lshr1:
557 ; SSE2: # %bb.0:
558 ; SSE2-NEXT: movdqa %xmm0, %xmm1
559 ; SSE2-NEXT: psrld $2, %xmm1
560 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[2,0]
561 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
562 ; SSE2-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
563 ; SSE2-NEXT: movaps %xmm1, %xmm0
564 ; SSE2-NEXT: retq
565 ;
566 ; SSE41-LABEL: combine_vec_shl_le_lshr1:
567 ; SSE41: # %bb.0:
568 ; SSE41-NEXT: movdqa %xmm0, %xmm1
569 ; SSE41-NEXT: psrld $2, %xmm1
570 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
571 ; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
572 ; SSE41-NEXT: retq
573 ;
574 ; AVX-LABEL: combine_vec_shl_le_lshr1:
575 ; AVX: # %bb.0:
576 ; AVX-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
577 ; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
578 ; AVX-NEXT: retq
579 %1 = lshr <4 x i32> %x, <i32 5, i32 6, i32 7, i32 8>
580 %2 = shl <4 x i32> %1, <i32 3, i32 4, i32 5, i32 8>
581 ret <4 x i32> %2
582 }
584 ; fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
585 define <4 x i32> @combine_vec_shl_ashr0(<4 x i32> %x) {
586 ; SSE-LABEL: combine_vec_shl_ashr0:
587 ; SSE: # %bb.0:
588 ; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
589 ; SSE-NEXT: retq
590 ;
591 ; AVX-LABEL: combine_vec_shl_ashr0:
592 ; AVX: # %bb.0:
593 ; AVX-NEXT: vbroadcastss {{.*#+}} xmm1 = [4294967264,4294967264,4294967264,4294967264]
594 ; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
595 ; AVX-NEXT: retq
596 %1 = ashr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>
597 %2 = shl <4 x i32> %1, <i32 5, i32 5, i32 5, i32 5>
598 ret <4 x i32> %2
599 }
601 define <4 x i32> @combine_vec_shl_ashr1(<4 x i32> %x) {
602 ; SSE-LABEL: combine_vec_shl_ashr1:
603 ; SSE: # %bb.0:
604 ; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
605 ; SSE-NEXT: retq
606 ;
607 ; AVX-LABEL: combine_vec_shl_ashr1:
608 ; AVX: # %bb.0:
609 ; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
610 ; AVX-NEXT: retq
611 %1 = ashr <4 x i32> %x, <i32 5, i32 6, i32 7, i32 8>
612 %2 = shl <4 x i32> %1, <i32 5, i32 6, i32 7, i32 8>
613 ret <4 x i32> %2
614 }
616 ; fold (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2)
617 define <4 x i32> @combine_vec_shl_add0(<4 x i32> %x) {
618 ; SSE-LABEL: combine_vec_shl_add0:
619 ; SSE: # %bb.0:
620 ; SSE-NEXT: pslld $2, %xmm0
621 ; SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
622 ; SSE-NEXT: retq
623 ;
624 ; AVX-LABEL: combine_vec_shl_add0:
625 ; AVX: # %bb.0:
626 ; AVX-NEXT: vpslld $2, %xmm0, %xmm0
627 ; AVX-NEXT: vpbroadcastd {{.*#+}} xmm1 = [20,20,20,20]
628 ; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
629 ; AVX-NEXT: retq
630 %1 = add <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>
631 %2 = shl <4 x i32> %1, <i32 2, i32 2, i32 2, i32 2>
632 ret <4 x i32> %2
633 }
635 define <4 x i32> @combine_vec_shl_add1(<4 x i32> %x) {
636 ; SSE2-LABEL: combine_vec_shl_add1:
637 ; SSE2: # %bb.0:
638 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
639 ; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
640 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
641 ; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
642 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
643 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
644 ; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
645 ; SSE2-NEXT: retq
646 ;
647 ; SSE41-LABEL: combine_vec_shl_add1:
648 ; SSE41: # %bb.0:
649 ; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
650 ; SSE41-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
651 ; SSE41-NEXT: retq
652 ;
653 ; AVX-LABEL: combine_vec_shl_add1:
654 ; AVX: # %bb.0:
655 ; AVX-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
656 ; AVX-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
657 ; AVX-NEXT: retq
658 %1 = add <4 x i32> %x, <i32 5, i32 6, i32 7, i32 8>
659 %2 = shl <4 x i32> %1, <i32 1, i32 2, i32 3, i32 4>
660 ret <4 x i32> %2
661 }
663 ; fold (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2)
664 define <4 x i32> @combine_vec_shl_or0(<4 x i32> %x) {
665 ; SSE-LABEL: combine_vec_shl_or0:
666 ; SSE: # %bb.0:
667 ; SSE-NEXT: pslld $2, %xmm0
668 ; SSE-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
669 ; SSE-NEXT: retq
670 ;
671 ; AVX-LABEL: combine_vec_shl_or0:
672 ; AVX: # %bb.0:
673 ; AVX-NEXT: vpslld $2, %xmm0, %xmm0
674 ; AVX-NEXT: vpbroadcastd {{.*#+}} xmm1 = [20,20,20,20]
675 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
676 ; AVX-NEXT: retq
677 %1 = or <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>
678 %2 = shl <4 x i32> %1, <i32 2, i32 2, i32 2, i32 2>
679 ret <4 x i32> %2
680 }
682 define <4 x i32> @combine_vec_shl_or1(<4 x i32> %x) {
683 ; SSE2-LABEL: combine_vec_shl_or1:
684 ; SSE2: # %bb.0:
685 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
686 ; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
687 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
688 ; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
689 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
690 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
691 ; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
692 ; SSE2-NEXT: retq
693 ;
694 ; SSE41-LABEL: combine_vec_shl_or1:
695 ; SSE41: # %bb.0:
696 ; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
697 ; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
698 ; SSE41-NEXT: retq
699 ;
700 ; AVX-LABEL: combine_vec_shl_or1:
701 ; AVX: # %bb.0:
702 ; AVX-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
703 ; AVX-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
704 ; AVX-NEXT: retq
705 %1 = or <4 x i32> %x, <i32 5, i32 6, i32 7, i32 8>
706 %2 = shl <4 x i32> %1, <i32 1, i32 2, i32 3, i32 4>
707 ret <4 x i32> %2
708 }
710 ; fold (shl (mul x, c1), c2) -> (mul x, c1 << c2)
711 define <4 x i32> @combine_vec_shl_mul0(<4 x i32> %x) {
712 ; SSE2-LABEL: combine_vec_shl_mul0:
713 ; SSE2: # %bb.0:
714 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [20,20,20,20]
715 ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
716 ; SSE2-NEXT: pmuludq %xmm1, %xmm0
717 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
718 ; SSE2-NEXT: pmuludq %xmm1, %xmm2
719 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
720 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
721 ; SSE2-NEXT: retq
722 ;
723 ; SSE41-LABEL: combine_vec_shl_mul0:
724 ; SSE41: # %bb.0:
725 ; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
726 ; SSE41-NEXT: retq
727 ;
728 ; AVX-LABEL: combine_vec_shl_mul0:
729 ; AVX: # %bb.0:
730 ; AVX-NEXT: vpbroadcastd {{.*#+}} xmm1 = [20,20,20,20]
731 ; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm0
732 ; AVX-NEXT: retq
733 %1 = mul <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>
734 %2 = shl <4 x i32> %1, <i32 2, i32 2, i32 2, i32 2>
735 ret <4 x i32> %2
736 }
738 define <4 x i32> @combine_vec_shl_mul1(<4 x i32> %x) {
739 ; SSE2-LABEL: combine_vec_shl_mul1:
740 ; SSE2: # %bb.0:
741 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
742 ; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
743 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
744 ; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
745 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
746 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
747 ; SSE2-NEXT: retq
748 ;
749 ; SSE41-LABEL: combine_vec_shl_mul1:
750 ; SSE41: # %bb.0:
751 ; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
752 ; SSE41-NEXT: retq
753 ;
754 ; AVX-LABEL: combine_vec_shl_mul1:
755 ; AVX: # %bb.0:
756 ; AVX-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
757 ; AVX-NEXT: retq
758 %1 = mul <4 x i32> %x, <i32 5, i32 6, i32 7, i32 8>
759 %2 = shl <4 x i32> %1, <i32 1, i32 2, i32 3, i32 4>
760 ret <4 x i32> %2
761 }
763 ; fold (add (shl x, c1), c2) -> (or (shl x, c1), c2)
764 define <4 x i32> @combine_vec_add_shl_nonsplat(<4 x i32> %a0) {
765 ; SSE2-LABEL: combine_vec_add_shl_nonsplat:
766 ; SSE2: # %bb.0:
767 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
768 ; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
769 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
770 ; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
771 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
772 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
773 ; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
774 ; SSE2-NEXT: retq
775 ;
776 ; SSE41-LABEL: combine_vec_add_shl_nonsplat:
777 ; SSE41: # %bb.0:
778 ; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
779 ; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
780 ; SSE41-NEXT: retq
781 ;
782 ; AVX-LABEL: combine_vec_add_shl_nonsplat:
783 ; AVX: # %bb.0:
784 ; AVX-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
785 ; AVX-NEXT: vpbroadcastd {{.*#+}} xmm1 = [3,3,3,3]
786 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
787 ; AVX-NEXT: retq
788 %1 = shl <4 x i32> %a0, <i32 2, i32 3, i32 4, i32 5>
789 %2 = add <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>
790 ret <4 x i32> %2
791 }
793 define <4 x i32> @combine_vec_add_shl_and_nonsplat(<4 x i32> %a0) {
794 ; SSE2-LABEL: combine_vec_add_shl_and_nonsplat:
795 ; SSE2: # %bb.0:
796 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
797 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [4,8,16,32]
798 ; SSE2-NEXT: pmuludq %xmm0, %xmm1
799 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
800 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
801 ; SSE2-NEXT: pmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
802 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
803 ; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
804 ; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
805 ; SSE2-NEXT: movdqa %xmm1, %xmm0
806 ; SSE2-NEXT: retq
807 ;
808 ; SSE41-LABEL: combine_vec_add_shl_and_nonsplat:
809 ; SSE41: # %bb.0:
810 ; SSE41-NEXT: pxor %xmm1, %xmm1
811 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3],xmm1[4],xmm0[5],xmm1[6],xmm0[7]
812 ; SSE41-NEXT: pmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
813 ; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
814 ; SSE41-NEXT: retq
815 ;
816 ; AVX-LABEL: combine_vec_add_shl_and_nonsplat:
817 ; AVX: # %bb.0:
818 ; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
819 ; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3],xmm1[4],xmm0[5],xmm1[6],xmm0[7]
820 ; AVX-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
821 ; AVX-NEXT: vpbroadcastd {{.*#+}} xmm1 = [15,15,15,15]
822 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
823 ; AVX-NEXT: retq
824 %1 = and <4 x i32> %a0, <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>
825 %2 = shl <4 x i32> %1, <i32 2, i32 3, i32 4, i32 5>
826 %3 = add <4 x i32> %2, <i32 15, i32 15, i32 15, i32 15>
827 ret <4 x i32> %3
828 }
830 define <4 x i32> @combine_vec_add_shuffle_shl(<4 x i32> %a0) {
831 ; SSE2-LABEL: combine_vec_add_shuffle_shl:
832 ; SSE2: # %bb.0:
833 ; SSE2-NEXT: movdqa %xmm0, %xmm1
834 ; SSE2-NEXT: pslld $3, %xmm1
835 ; SSE2-NEXT: pslld $2, %xmm0
836 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
837 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,3,3,0]
838 ; SSE2-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
839 ; SSE2-NEXT: retq
840 ;
841 ; SSE41-LABEL: combine_vec_add_shuffle_shl:
842 ; SSE41: # %bb.0:
843 ; SSE41-NEXT: movdqa %xmm0, %xmm1
844 ; SSE41-NEXT: pslld $3, %xmm1
845 ; SSE41-NEXT: pslld $2, %xmm0
846 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
847 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
848 ; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
849 ; SSE41-NEXT: retq
850 ;
851 ; AVX-LABEL: combine_vec_add_shuffle_shl:
852 ; AVX: # %bb.0:
853 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
854 ; AVX-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
855 ; AVX-NEXT: vpbroadcastd {{.*#+}} xmm1 = [3,3,3,3]
856 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
857 ; AVX-NEXT: retq
858 %1 = shl <4 x i32> %a0, <i32 2, i32 3, i32 0, i32 1>
859 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 1, i32 0>
860 %3 = add <4 x i32> %2, <i32 3, i32 3, i32 3, i32 3>
861 ret <4 x i32> %3
862 }