llvm/test/MC/AArch64/SME2p1/bfmin-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+b16b16 2>&1 < %s | FileCheck %s
   2
   3 // --------------------------------------------------------------------------//
   4 // Invalid vector list
   5
   6 bfmin {z0.h-z1.h}, {z0.h-z2.h}, z0.h
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
   8 // CHECK-NEXT: bfmin {z0.h-z1.h}, {z0.h-z2.h}, z0.h
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 bfmin {z1.h-z2.h}, {z0.h-z1.h}, z0.h
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
  13 // CHECK-NEXT: bfmin {z1.h-z2.h}, {z0.h-z1.h}, z0.h
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16 bfmin {z1.h-z4.h}, {z0.h-z3.h}, z0.h
  17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
  18 // CHECK-NEXT: bfmin {z1.h-z4.h}, {z0.h-z3.h}, z0.h
  19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  20
  21 // --------------------------------------------------------------------------//
  22 // Invalid single register
  23
  24 bfmin {z0.h-z1.h}, {z2.h-z3.h}, z31.h
  25 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
  26 // CHECK-NEXT: bfmin {z0.h-z1.h}, {z2.h-z3.h}, z31.h
  27 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  28
  29 // --------------------------------------------------------------------------//
  30 // Invalid Register Suffix
  31
  32 bfmin {z0.h-z1.h}, {z2.h-z3.h}, z14.d
  33 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
  34 // CHECK-NEXT: bfmin {z0.h-z1.h}, {z2.h-z3.h}, z14.d
  35 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  36
  37 bfmin {z0.h-z1.h}, {z2.s-z3.s}, z14.h
  38 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  39 // CHECK-NEXT: bfmin {z0.h-z1.h}, {z2.s-z3.s}, z14.h
  40 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  41
  42 bfmin {z0.h-z1.h}, {z2.h-z3.s}, z14.h
  43 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
  44 // CHECK-NEXT: bfmin {z0.h-z1.h}, {z2.h-z3.s}, z14.h
  45 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: