llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td

   1 // RUN: llvm-tblgen -I %p/../../../include -gen-global-isel-combiner \
   2 // RUN:     -combiners=MyCombiner %s | \
   3 // RUN: FileCheck %s
   4
   5 include "llvm/Target/Target.td"
   6 include "llvm/Target/GlobalISel/Combine.td"
   7
   8 def MyTargetISA : InstrInfo;
   9 def MyTarget : Target { let InstructionSet = MyTargetISA; }
  10
  11 def InstTest0 : GICombineRule<
  12   (defs root:$a),
  13   (match  (G_MUL i32:$x, i32:$b, i32:$c),
  14           (G_MUL $a, i32:$b, i32:$x)),
  15   (apply  (G_ADD i64:$tmp, $b, i32:$c),
  16           (G_ADD i8:$a, $b, i64:$tmp))>;
  17
  18 def MyCombiner: GICombiner<"GenMyCombiner", [
  19   InstTest0,
  20 ]>;
  21
  22 // CHECK:       const int64_t *GenMyCombiner::getMatchTable() const {
  23 // CHECK-NEXT:   constexpr static int64_t MatchTable0[] = {
  24 // CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 0*/ 73, // Rule ID 0 //
  25 // CHECK-NEXT:       GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled,
  26 // CHECK-NEXT:       GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL,
  27 // CHECK-NEXT:       GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s8,
  28 // CHECK-NEXT:       GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
  29 // CHECK-NEXT:       GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
  30 // CHECK-NEXT:       GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
  31 // CHECK-NEXT:       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
  32 // CHECK-NEXT:       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
  33 // CHECK-NEXT:       // MIs[1] b
  34 // CHECK-NEXT:       GIM_CheckIsSameOperandIgnoreCopies, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
  35 // CHECK-NEXT:       GIM_CheckIsSafeToFold, /*InsnID*/1,
  36 // CHECK-NEXT:       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
  37 // CHECK-NEXT:       // Combiner Rule #0: InstTest0
  38 // CHECK-NEXT:       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::G_ADD,
  39 // CHECK-NEXT:       GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
  40 // CHECK-NEXT:       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // b
  41 // CHECK-NEXT:       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // c
  42 // CHECK-NEXT:       GIR_EraseFromParent, /*InsnID*/0,
  43 // CHECK-NEXT:       GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::G_ADD,
  44 // CHECK-NEXT:       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // a
  45 // CHECK-NEXT:       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // b
  46 // CHECK-NEXT:       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0,
  47 // CHECK-NEXT:       GIR_Done,
  48 // CHECK-NEXT:     // Label 0: @73
  49 // CHECK-NEXT:     GIM_Reject,
  50 // CHECK-NEXT:     };
  51 // CHECK-NEXT:   return MatchTable0;
  52 // CHECK-NEXT: }