[clang][modules] Don't prevent translation of FW_Private includes when explicitly...
[llvm-project.git] / llvm / test / TableGen / GlobalISelCombinerEmitter / match-table-patfrag-root.td
blob5cb9206ca5f2caf1213f5fcf5e99ac93ec42144b
1 // RUN: llvm-tblgen -I %p/../../../include -gen-global-isel-combiner \
2 // RUN:     -combiners=MyCombiner -gicombiner-debug-cxxpreds %s | \
3 // RUN: FileCheck %s
5 include "llvm/Target/Target.td"
6 include "llvm/Target/GlobalISel/Combine.td"
8 def MyTargetISA : InstrInfo;
9 def MyTarget : Target { let InstructionSet = MyTargetISA; }
11 def MatchFooPerms: GICombinePatFrag<
12     (outs root:$foo),
13     (ins gi_imm:$cst),
14     [
15       (pattern (G_ZEXT $foo, $b), (G_TRUNC $b, $x):$dbg0),
16       (pattern (G_TRUNC $foo, $z):$dbg1),
17       (pattern (G_FPEXT $foo, $z):$dbg1)
18     ]>;
20 def Test0 : GICombineRule<
21   (defs root:$root),
22   (match (MatchFooPerms $root, (i32 10))),
23   (apply (COPY $root, (i32 0)))>;
25 def MyCombiner: GICombiner<"GenMyCombiner", [
26   Test0
27 ]>;
29 // CHECK:      const int64_t *GenMyCombiner::getMatchTable() const {
30 // CHECK-NEXT:   constexpr static int64_t MatchTable0[] = {
31 // CHECK-NEXT:     GIM_SwitchOpcode, /*MI*/0, /*[*/118, 181, /*)*//*default:*//*Label 3*/ 152,
32 // CHECK-NEXT:     /*TargetOpcode::G_TRUNC*//*Label 0*/ 68, 0, 0, 0, 0, 0, 0,
33 // CHECK-NEXT:     /*TargetOpcode::G_ZEXT*//*Label 1*/ 93, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
34 // CHECK-NEXT:     /*TargetOpcode::G_FPEXT*//*Label 2*/ 127,
35 // CHECK-NEXT:     // Label 0: @68
36 // CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 4*/ 92, // Rule ID 1 //
37 // CHECK-NEXT:       GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled,
38 // CHECK-NEXT:       // MIs[0] root
39 // CHECK-NEXT:       // No operand predicates
40 // CHECK-NEXT:       // MIs[0] __Test0_match_0.z
41 // CHECK-NEXT:       // No operand predicates
42 // CHECK-NEXT:       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43 // CHECK-NEXT:       GIR_BuildConstant, /*TempRegID*/0, /*Val*/0,
44 // CHECK-NEXT:       // Combiner Rule #0: Test0 @ [__Test0_match_0[1]]
45 // CHECK-NEXT:       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
46 // CHECK-NEXT:       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // root
47 // CHECK-NEXT:       GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
48 // CHECK-NEXT:       GIR_EraseFromParent, /*InsnID*/0,
49 // CHECK-NEXT:       GIR_Done,
50 // CHECK-NEXT:     // Label 4: @92
51 // CHECK-NEXT:     GIM_Reject,
52 // CHECK-NEXT:     // Label 1: @93
53 // CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 5*/ 126, // Rule ID 0 //
54 // CHECK-NEXT:       GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled,
55 // CHECK-NEXT:       // MIs[0] root
56 // CHECK-NEXT:       // No operand predicates
57 // CHECK-NEXT:       // MIs[0] __Test0_match_0.b
58 // CHECK-NEXT:       GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
59 // CHECK-NEXT:       GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC,
60 // CHECK-NEXT:       // MIs[1] __Test0_match_0.x
61 // CHECK-NEXT:       // No operand predicates
62 // CHECK-NEXT:       GIM_CheckIsSafeToFold, /*InsnID*/1,
63 // CHECK-NEXT:       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
64 // CHECK-NEXT:       GIR_BuildConstant, /*TempRegID*/0, /*Val*/0,
65 // CHECK-NEXT:       // Combiner Rule #0: Test0 @ [__Test0_match_0[0]]
66 // CHECK-NEXT:       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
67 // CHECK-NEXT:       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // root
68 // CHECK-NEXT:       GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
69 // CHECK-NEXT:       GIR_EraseFromParent, /*InsnID*/0,
70 // CHECK-NEXT:       GIR_Done,
71 // CHECK-NEXT:     // Label 5: @126
72 // CHECK-NEXT:     GIM_Reject,
73 // CHECK-NEXT:     // Label 2: @127
74 // CHECK-NEXT:     GIM_Try, /*On fail goto*//*Label 6*/ 151, // Rule ID 2 //
75 // CHECK-NEXT:       GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled,
76 // CHECK-NEXT:       // MIs[0] root
77 // CHECK-NEXT:       // No operand predicates
78 // CHECK-NEXT:       // MIs[0] __Test0_match_0.z
79 // CHECK-NEXT:       // No operand predicates
80 // CHECK-NEXT:       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
81 // CHECK-NEXT:       GIR_BuildConstant, /*TempRegID*/0, /*Val*/0,
82 // CHECK-NEXT:       // Combiner Rule #0: Test0 @ [__Test0_match_0[2]]
83 // CHECK-NEXT:       GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
84 // CHECK-NEXT:       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // root
85 // CHECK-NEXT:       GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
86 // CHECK-NEXT:       GIR_EraseFromParent, /*InsnID*/0,
87 // CHECK-NEXT:       GIR_Done,
88 // CHECK-NEXT:     // Label 6: @151
89 // CHECK-NEXT:     GIM_Reject,
90 // CHECK-NEXT:     // Label 3: @152
91 // CHECK-NEXT:     GIM_Reject,
92 // CHECK-NEXT:     };
93 // CHECK-NEXT:   return MatchTable0;
94 // CHECK-NEXT: }