llvm/test/TableGen/GlobalISelEmitter.td

   1 // RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=false %s -o %T/non-optimized.cpp
   2 // RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=true  %s -o %T/optimized.cpp
   3 // RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o %T/default.cpp
   4
   5 // RUN: FileCheck %s --check-prefixes=CHECK,R19C,R19N -input-file=%T/non-optimized.cpp
   6 // RUN: FileCheck %s --check-prefixes=CHECK,R19C,R19O -input-file=%T/optimized.cpp
   7
   8 // RUN: FileCheck %s --check-prefixes=CHECK,R21C,R21N -input-file=%T/non-optimized.cpp
   9 // RUN: FileCheck %s --check-prefixes=CHECK,R21C,R21O -input-file=%T/optimized.cpp
  10
  11 // RUN: FileCheck %s --check-prefixes=CHECK,R20C,R20N -input-file=%T/non-optimized.cpp
  12 // RUN: FileCheck %s --check-prefixes=CHECK,R20C,R20O -input-file=%T/optimized.cpp
  13
  14 // RUN: FileCheck %s --check-prefixes=CHECK,R00C,R00N -input-file=%T/non-optimized.cpp
  15 // RUN: FileCheck %s --check-prefixes=CHECK,R00C,R00O -input-file=%T/optimized.cpp
  16
  17 // RUN: FileCheck %s --check-prefixes=CHECK,R01C,R01N -input-file=%T/non-optimized.cpp
  18 // RUN: FileCheck %s --check-prefixes=CHECK,R01C,R01O -input-file=%T/optimized.cpp
  19
  20 // RUN: FileCheck %s --check-prefixes=CHECK,R02C,R02N,NOOPT -input-file=%T/non-optimized.cpp
  21 // RUN: FileCheck %s --check-prefixes=CHECK,R02C,R02O       -input-file=%T/optimized.cpp
  22
  23 // RUN: diff %T/default.cpp %T/optimized.cpp
  24
  25 include "llvm/Target/Target.td"
  26 include "GlobalISelEmitterCommon.td"
  27
  28 //===- Define the necessary boilerplate for our test target. --------------===//
  29
  30 let TargetPrefix = "mytarget" in {
  31 def int_mytarget_nop : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
  32 }
  33
  34 def complex : Operand<i32>, ComplexPattern<i32, 2, "SelectComplexPattern", []> {
  35   let MIOperandInfo = (ops i32imm, i32imm);
  36 }
  37 def gi_complex :
  38     GIComplexOperandMatcher<s32, "selectComplexPattern">,
  39     GIComplexPatternEquiv<complex>;
  40 def complex_rr : Operand<i32>, ComplexPattern<i32, 2, "SelectComplexPatternRR", []> {
  41   let MIOperandInfo = (ops GPR32, GPR32);
  42 }
  43 def gi_complex_rr :
  44     GIComplexOperandMatcher<s32, "selectComplexPatternRR">,
  45     GIComplexPatternEquiv<complex_rr>;
  46
  47 def cimm8_xform : SDNodeXForm<imm, [{
  48     uint64_t Val = N->getZExtValue() << 1;
  49     return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i64);
  50   }]>;
  51
  52 def cimm8 : Operand<i32>, ImmLeaf<i32, [{return isInt<8>(Imm);}], cimm8_xform>;
  53
  54 def gi_cimm8 : GICustomOperandRenderer<"renderImm">,
  55                 GISDNodeXFormEquiv<cimm8_xform>;
  56
  57 def gi_cimm9 : GICustomOperandRenderer<"renderImm">;
  58
  59 def m1 : OperandWithDefaultOps <i32, (ops (i32 -1))>;
  60 def Z : OperandWithDefaultOps <i32, (ops R0)>;
  61 def m1Z : OperandWithDefaultOps <i32, (ops (i32 -1), R0)>;
  62
  63 def HasA : Predicate<"Subtarget->hasA()">;
  64 def HasB : Predicate<"Subtarget->hasB()">;
  65 def HasC : Predicate<"Subtarget->hasC()"> { let RecomputePerFunction = 1; }
  66
  67 //===- Test the function boilerplate. -------------------------------------===//
  68
  69 // CHECK: const unsigned MAX_SUBTARGET_PREDICATES = 3;
  70 // CHECK: using PredicateBitset = llvm::Bitset<MAX_SUBTARGET_PREDICATES>;
  71
  72 // CHECK-LABEL: #ifdef GET_GLOBALISEL_TEMPORARIES_DECL
  73 // CHECK-NEXT:    mutable MatcherState State;
  74 // CHECK-NEXT:    typedef ComplexRendererFns(MyTargetInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
  75 // CHECK-NEXT:    typedef void(MyTargetInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
  76 // CHECK-NEXT:    const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo;
  77 // CHECK-NEXT:    static MyTargetInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
  78 // CHECK-NEXT:    static MyTargetInstructionSelector::CustomRendererFn CustomRenderers[];
  79 // CHECK-NEXT:    bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
  80 // CHECK-NEXT:    bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
  81 // CHECK-NEXT:    bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
  82 // CHECK-NEXT:    const int64_t *getMatchTable() const override;
  83 // CHECK-NEXT:    bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override;
  84 // CHECK-NEXT:    bool testSimplePredicate(unsigned PredicateID) const override;
  85 // CHECK-NEXT:    void runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override;
  86 // CHECK-NEXT:  #endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
  87
  88 // CHECK-LABEL: #ifdef GET_GLOBALISEL_TEMPORARIES_INIT
  89 // CHECK-NEXT:    , State(3),
  90 // CHECK-NEXT:    ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
  91 // CHECK-NEXT:  #endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
  92
  93 // CHECK-LABEL: // LLT Objects.
  94 // CHECK-NEXT:  enum {
  95 // CHECK-NEXT:    GILLT_p0s32
  96 // CHECK-NEXT:    GILLT_s32,
  97 // CHECK-NEXT:  }
  98 // CHECK-NEXT:  const static size_t NumTypeObjects = 2;
  99 // CHECK-NEXT:  const static LLT TypeObjects[] = {
 100 // CHECK-NEXT:    LLT::pointer(0, 32),
 101 // CHECK-NEXT:    LLT::scalar(32),
 102 // CHECK-NEXT:  };
 103
 104 // CHECK-LABEL: enum SubtargetFeatureBits : uint8_t {
 105 // CHECK-NEXT:    Feature_HasABit = 0,
 106 // CHECK-NEXT:    Feature_HasBBit = 1,
 107 // CHECK-NEXT:    Feature_HasCBit = 2,
 108 // CHECK-NEXT:  };
 109
 110 // CHECK-LABEL: PredicateBitset MyTargetInstructionSelector::
 111 // CHECK-NEXT:  computeAvailableModuleFeatures(const MyTargetSubtarget *Subtarget) const {
 112 // CHECK-NEXT:    PredicateBitset Features;
 113 // CHECK-NEXT:    if (Subtarget->hasA())
 114 // CHECK-NEXT:      Features.set(Feature_HasABit);
 115 // CHECK-NEXT:    if (Subtarget->hasB())
 116 // CHECK-NEXT:      Features.set(Feature_HasBBit);
 117 // CHECK-NEXT:    return Features;
 118 // CHECK-NEXT:  }
 119
 120 // CHECK-LABEL: PredicateBitset MyTargetInstructionSelector::
 121 // CHECK-NEXT:  computeAvailableFunctionFeatures(const MyTargetSubtarget *Subtarget, const MachineFunction *MF) const {
 122 // CHECK-NEXT:    PredicateBitset Features;
 123 // CHECK-NEXT:    if (Subtarget->hasC())
 124 // CHECK-NEXT:      Features.set(Feature_HasCBit);
 125 // CHECK-NEXT:    return Features;
 126 // CHECK-NEXT:  }
 127
 128 // CHECK-LABEL: // Feature bitsets.
 129 // CHECK-NEXT:  enum {
 130 // CHECK-NEXT:    GIFBS_Invalid,
 131 // CHECK-NEXT:    GIFBS_HasA,
 132 // CHECK-NEXT:    GIFBS_HasA_HasB_HasC,
 133 // CHECK-NEXT:  }
 134 // CHECK-NEXT:  constexpr static PredicateBitset FeatureBitsets[] {
 135 // CHECK-NEXT:    {}, // GIFBS_Invalid
 136 // CHECK-NEXT:    {Feature_HasABit, },
 137 // CHECK-NEXT:    {Feature_HasABit, Feature_HasBBit, Feature_HasCBit, },
 138 // CHECK-NEXT:  };
 139
 140 // CHECK-LABEL: // ComplexPattern predicates.
 141 // CHECK-NEXT:  enum {
 142 // CHECK-NEXT:    GICP_Invalid,
 143 // CHECK-NEXT:    GICP_gi_complex,
 144 // CHECK-NEXT:    GICP_gi_complex_rr,
 145 // CHECK-NEXT:  };
 146
 147 // CHECK-LABEL: MyTargetInstructionSelector::ComplexMatcherMemFn
 148 // CHECK-NEXT:  MyTargetInstructionSelector::ComplexPredicateFns[] = {
 149 // CHECK-NEXT:    nullptr, // GICP_Invalid
 150 // CHECK-NEXT:    &MyTargetInstructionSelector::selectComplexPattern, // gi_complex
 151 // CHECK-NEXT:    &MyTargetInstructionSelector::selectComplexPatternRR, // gi_complex_rr
 152 // CHECK-NEXT:  }
 153
 154 // CHECK-LABEL: // PatFrag predicates.
 155 // CHECK-NEXT:  enum {
 156 // CHECK-NEXT:   GICXXPred_MI_Predicate_frag = GICXXPred_Invalid + 1,
 157 // CHECK-NEXT:  };
 158
 159 // CHECK-LABEL: // PatFrag predicates.
 160 // CHECK-NEXT:  enum {
 161 // CHECK-NEXT:    GICXXPred_I64_Predicate_cimm8 = GICXXPred_Invalid + 1,
 162 // CHECK-NEXT:    GICXXPred_I64_Predicate_simm8,
 163 // CHECK-NEXT:  };
 164
 165 // CHECK-NEXT: bool MyTargetInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
 166 // CHECK-NEXT:   switch (PredicateID) {
 167 // CHECK-NEXT:   case GICXXPred_I64_Predicate_cimm8: {
 168 // CHECK-NEXT:     return isInt<8>(Imm);
 169 // CHECK-NEXT:   }
 170 // CHECK-NEXT:   case GICXXPred_I64_Predicate_simm8: {
 171 // CHECK-NEXT:     return isInt<8>(Imm);
 172 // CHECK-NEXT:   }
 173 // CHECK-NEXT:   }
 174 // CHECK-NEXT:   llvm_unreachable("Unknown predicate");
 175 // CHECK-NEXT:   return false;
 176 // CHECK-NEXT: }
 177
 178 // CHECK-LABEL: // PatFrag predicates.
 179 // CHECK-NEXT:  enum {
 180 // CHECK-NEXT:    GICXXPred_APFloat_Predicate_fpimmz = GICXXPred_Invalid + 1,
 181 // CHECK-NEXT:  };
 182 // CHECK-NEXT:  bool MyTargetInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
 183 // CHECK-NEXT:    switch (PredicateID) {
 184 // CHECK-NEXT:    case GICXXPred_APFloat_Predicate_fpimmz: {
 185 // CHECK-NEXT:      return Imm->isExactlyValue(0.0);
 186 // CHECK-NEXT:    }
 187 // CHECK-NEXT:    }
 188 // CHECK-NEXT:    llvm_unreachable("Unknown predicate");
 189 // CHECK-NEXT:    return false;
 190 // CHECK-NEXT:  }
 191
 192 // CHECK-LABEL: // PatFrag predicates.
 193 // CHECK-NEXT:  enum {
 194 // CHECK-NEXT:    GICXXPred_APInt_Predicate_simm9 = GICXXPred_Invalid + 1,
 195 // CHECK-NEXT:  };
 196 // CHECK-NEXT:  bool MyTargetInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
 197 // CHECK-NEXT:    switch (PredicateID) {
 198 // CHECK-NEXT:    case GICXXPred_APInt_Predicate_simm9: {
 199 // CHECK-NEXT:      return isInt<9>(Imm->getSExtValue());
 200 // CHECK-NEXT:    }
 201 // CHECK-NEXT:    }
 202 // CHECK-NEXT:    llvm_unreachable("Unknown predicate");
 203 // CHECK-NEXT:    return false;
 204 // CHECK-NEXT:  }
 205
 206 // CHECK-LABEL: // Custom renderers.
 207 // CHECK-NEXT: enum {
 208 // CHECK-NEXT:   GICR_Invalid,
 209 // CHECK-NEXT:   GICR_renderImm,
 210 // CHECK-NEXT: };
 211 // CHECK-NEXT: MyTargetInstructionSelector::CustomRendererFn
 212 // CHECK-NEXT: MyTargetInstructionSelector::CustomRenderers[] = {
 213 // CHECK-NEXT:   nullptr, // GICR_Invalid
 214 // CHECK-NEXT:   &MyTargetInstructionSelector::renderImm,
 215 // CHECK-NEXT: };
 216
 217 // CHECK: bool MyTargetInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
 218 // CHECK-NEXT: const PredicateBitset AvailableFeatures = getAvailableFeatures();
 219 // CHECK-NEXT: MachineIRBuilder B(I);
 220 // CHECK-NEXT: State.MIs.clear();
 221 // CHECK-NEXT: State.MIs.push_back(&I);
 222
 223 // CHECK:      if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) {
 224 // CHECK-NEXT:   return true;
 225 // CHECK-NEXT: }
 226
 227 // CHECK: const int64_t *
 228 // CHECK-LABEL: MyTargetInstructionSelector::getMatchTable() const {
 229 // CHECK-NEXT: MatchTable0[] = {
 230
 231 //===- Test a pattern with multiple ComplexPatterns in multiple instrs ----===//
 232 //
 233 // R19O-NEXT:  GIM_SwitchOpcode, /*MI*/0, /*[*/{{[0-9]+}}, {{[0-9]+}}, /*)*//*default:*//*Label [[DEFAULT_NUM:[0-9]+]]*/ [[DEFAULT:[0-9]+]],
 234 // R19O-NEXT:  /*TargetOpcode::G_ADD*//*Label [[CASE_ADD_NUM:[0-9]+]]*/ [[CASE_ADD:[0-9]+]],
 235 // R19O:       /*TargetOpcode::G_SELECT*//*Label [[CASE_SELECT_NUM:[0-9]+]]*/ [[CASE_SELECT:[0-9]+]],
 236 // R19O:       // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]]
 237 // R19O:       // Label [[CASE_SELECT_NUM]]: @[[CASE_SELECT]]
 238 // R19O-NEXT:  GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ [[GROUP:[0-9]+]],
 239 // R19O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 240 // R19O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 241 // R19O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 242 // R19O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
 243 //
 244 // R19C-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 245 //
 246 // R19O-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 247 // R19O-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 248 // R19N-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
 249 // R19N-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SELECT,
 250 // R19N-NEXT:    // MIs[0] dst
 251 // R19N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 252 // R19N-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 253 // R19N-NEXT:    // MIs[0] src1
 254 // R19N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 255 // R19N-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 256 // R19N-NEXT:    // MIs[0] complex_rr:src2a:src2b
 257 // R19N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 258 //
 259 // R19N-NEXT:    GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_complex_rr,
 260 // R19N-NEXT:    // MIs[0] Operand 3
 261 // R19N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
 262 // R19C-NEXT:    GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
 263 // R19N-NEXT:    GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
 264 // R19C-NEXT:    GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SELECT,
 265 // R19N-NEXT:    // MIs[1] Operand 0
 266 // R19N-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
 267 // R19N-NEXT:    // MIs[1] src3
 268 // R19C-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
 269 // R19O-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
 270 // R19O-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
 271 // R19N-NEXT:    GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 272 // R19N-NEXT:    // MIs[1] src4
 273 // R19N-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
 274 // R19N-NEXT:    GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/1, GICP_gi_complex,
 275 // R19N-NEXT:    // MIs[1] complex:src5a:src5b
 276 // R19N-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
 277 // R19N-NEXT:    GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/2, GICP_gi_complex,
 278 // R19O-NEXT:    GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 279 // R19C-NEXT:    GIM_CheckIsSafeToFold, /*InsnID*/1,
 280 // R19O-NEXT:    GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_complex_rr,
 281 // R19O-NEXT:    GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/1, GICP_gi_complex,
 282 // R19O-NEXT:    GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/2, GICP_gi_complex,
 283 // R19C-NEXT:    // (select:{ *:[i32] } GPR32:{ *:[i32] }:$src1, (complex_rr:{ *:[i32] } GPR32:{ *:[i32] }:$src2a, GPR32:{ *:[i32] }:$src2b), (select:{ *:[i32] } GPR32:{ *:[i32] }:$src3, complex:{ *:[i32] }:$src4, (complex:{ *:[i32] } i32imm:{ *:[i32] }:$src5a, i32imm:{ *:[i32] }:$src5b)))  =>  (INSN3:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2b, GPR32:{ *:[i32] }:$src2a, (INSN4:{ *:[i32] } GPR32:{ *:[i32] }:$src3, complex:{ *:[i32] }:$src4, i32imm:{ *:[i32] }:$src5a, i32imm:{ *:[i32] }:$src5b))
 284 // R19C-NEXT:    GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
 285 // R19C-NEXT:    GIR_BuildMI, /*InsnID*/1, /*Opcode*/MyTarget::INSN4,
 286 // R19C-NEXT:    GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
 287 // R19C-NEXT:    GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src3
 288 // R19C-NEXT:    GIR_ComplexRenderer, /*InsnID*/1, /*RendererID*/1,
 289 // R19C-NEXT:    GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/2, /*SubOperand*/0, // src5a
 290 // R19C-NEXT:    GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/2, /*SubOperand*/1, // src5b
 291 // R19C-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
 292 // R19C-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::INSN3,
 293 // R19C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 294 // R19C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
 295 // R19C-NEXT:    GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src2b
 296 // R19C-NEXT:    GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src2a
 297 // R19C-NEXT:    GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
 298 // R19C-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 299 // R19C-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 300 // R19C-NEXT:    // GIR_Coverage, 19,
 301 // R19C-NEXT:    GIR_Done,
 302 // R19C-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 303 //
 304 // R19O:       // Label [[GROUP_NUM]]: @[[GROUP]]
 305 // R19O-NEXT:  GIM_Reject,
 306 // R19O:       // Label [[DEFAULT_NUM]]: @[[DEFAULT]]
 307 // R19O-NEXT:  GIM_Reject,
 308 // R19O-NEXT:  };
 309
 310 def INSN3 : I<(outs GPR32:$dst),
 311               (ins GPR32Op:$src1, GPR32:$src2a, GPR32:$src2b, GPR32:$scr), []>;
 312 def INSN4 : I<(outs GPR32:$scr),
 313               (ins GPR32:$src3, complex:$src4, i32imm:$src5a, i32imm:$src5b), []>;
 314 def : Pat<(select GPR32:$src1, (complex_rr GPR32:$src2a, GPR32:$src2b),
 315                                (select GPR32:$src3,
 316                                        complex:$src4,
 317                                        (complex i32imm:$src5a, i32imm:$src5b))),
 318           (INSN3 GPR32:$src1, GPR32:$src2b, GPR32:$src2a,
 319                  (INSN4 GPR32:$src3, complex:$src4, i32imm:$src5a,
 320                         i32imm:$src5b))>;
 321
 322 // R21O-NEXT:  GIM_SwitchOpcode, /*MI*/0, /*[*/{{[0-9]+}}, {{[0-9]+}}, /*)*//*default:*//*Label [[DEFAULT_NUM:[0-9]+]]*/ [[DEFAULT:[0-9]+]],
 323 // R21O-NEXT:  /*TargetOpcode::G_ADD*//*Label [[CASE_ADD_NUM:[0-9]+]]*/ [[CASE_ADD:[0-9]+]],
 324 // R21O:       /*TargetOpcode::G_SELECT*//*Label [[CASE_SELECT_NUM:[0-9]+]]*/ [[CASE_SELECT:[0-9]+]],
 325 // R21O:       // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]]
 326 // R21O:       // Label [[CASE_SELECT_NUM]]: @[[CASE_SELECT]]
 327 // R21O-NEXT:  GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ [[GROUP:[0-9]+]],
 328 // R21O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 329 // R21O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 330 // R21O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 331 // R21O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
 332 //
 333 // R21C-NEXT:  GIM_Try, /*On fail goto*//*Label [[PREV_NUM:[0-9]+]]*/ [[PREV:[0-9]+]], // Rule ID 19 //
 334 // R21C-NOT:     GIR_Done,
 335 // R21C:         // GIR_Coverage, 19,
 336 // R21C-NEXT:    GIR_Done,
 337 // R21C-NEXT:  // Label [[PREV_NUM]]: @[[PREV]]
 338 // R21C-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], // Rule ID 21 //
 339 //
 340 // R21O-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 341 // R21O-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 342 // R21N-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
 343 // R21N-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SELECT,
 344 // R21N-NEXT:    // MIs[0] dst
 345 // R21N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 346 // R21N-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 347 // R21N-NEXT:    // MIs[0] src1
 348 // R21N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 349 // R21N-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 350 // R21N-NEXT:    // MIs[0] src2
 351 // R21N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 352 //
 353 // R21O-NEXT:    GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_frag,
 354 // R21C-NEXT:    GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_complex,
 355 // R21N-NEXT:    // MIs[0] src3
 356 // R21N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
 357 // R21C-NEXT:    GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_complex,
 358 // R21N-NEXT:    GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_frag,
 359 // R21C-NEXT:    // (select:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src2, complex:{ *:[i32] }:$src3)<<P:Predicate_frag>> => (INSN2:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src3, complex:{ *:[i32] }:$src2)
 360
 361 // R21C-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::INSN2,
 362 // R21C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 363 // R21C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
 364 // R21C-NEXT:    GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/1,
 365 // R21C-NEXT:    GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0,
 366 // R21C-NEXT:    GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
 367 // R21C-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 368 // R21C-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 369 // R21C-NEXT:    // GIR_Coverage, 21,
 370 // R21C-NEXT:    GIR_Done,
 371 // R21C-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 372 //
 373 // R21O-NEXT:  GIM_Reject,
 374 // R21O-NEXT:  // Label [[GROUP_NUM]]: @[[GROUP]]
 375 // R21O-NEXT:  GIM_Reject,
 376 // R21O:       // Label [[DEFAULT_NUM]]: @[[DEFAULT]]
 377 // R21O-NEXT:  GIM_Reject,
 378 // R21O-NEXT:  };
 379
 380 //===- Test a pattern with ComplexPattern operands. -----------------------===//
 381 //
 382 // R20O-NEXT:  GIM_SwitchOpcode, /*MI*/0, /*[*/{{[0-9]+}}, {{[0-9]+}}, /*)*//*default:*//*Label [[DEFAULT_NUM:[0-9]+]]*/ [[DEFAULT:[0-9]+]],
 383 // R20O-NEXT:  /*TargetOpcode::G_ADD*//*Label [[CASE_ADD_NUM:[0-9]+]]*/ [[CASE_ADD:[0-9]+]],
 384 // R20O:       /*TargetOpcode::G_SUB*//*Label [[CASE_SUB_NUM:[0-9]+]]*/ [[CASE_SUB:[0-9]+]],
 385 // R20O:       // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]]
 386 // R20O:       // Label [[CASE_SUB_NUM]]: @[[CASE_SUB]]
 387 // R20O-NEXT:  GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ [[GROUP:[0-9]+]],
 388 // R20O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 389 // R20O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 390 // R20O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 391 // R20O-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 392 //
 393 // R20N:       GIM_Try, /*On fail goto*//*Label [[PREV_NUM:[0-9]+]]*/ [[PREV:[0-9]+]], // Rule ID 21 //
 394 // R20N:       // Label [[PREV_NUM]]: @[[PREV]]
 395 //
 396 // R20C-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], // Rule ID 20 //
 397 //
 398 // R20N-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 399 // R20N-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SUB,
 400 // R20N-NEXT:    // MIs[0] dst
 401 // R20N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 402 // R20N-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 403 // R20N-NEXT:    // MIs[0] src1
 404 // R20N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 405 //
 406 // R20N-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 407 // R20N-NEXT:    // MIs[0] src2
 408 // R20N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 409 // R20O-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 410 // R20C-NEXT:    GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_complex,
 411 // R20C-NEXT:    // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src2) => (INSN1:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src2)
 412 // R20C-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::INSN1,
 413 // R20C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 414 // R20C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
 415 // R20C-NEXT:    GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0,
 416 // R20C-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 417 // R20C-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 418 // R20C-NEXT:    // GIR_Coverage, 20,
 419 // R20C-NEXT:    GIR_Done,
 420 // R20C-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 421 //
 422 // R20O:       // Label [[GROUP_NUM]]: @[[GROUP]]
 423 // R20O-NEXT:  GIM_Reject,
 424 // R20O:       // Label [[DEFAULT_NUM]]: @[[DEFAULT]]
 425 // R20O-NEXT:  GIM_Reject,
 426 // R20O-NEXT:  };
 427
 428 def INSN1 : I<(outs GPR32:$dst), (ins GPR32:$src1, complex:$src2), []>;
 429 def : Pat<(sub GPR32:$src1, complex:$src2), (INSN1 GPR32:$src1, complex:$src2)>;
 430
 431 //===- Test a pattern with multiple ComplexPattern operands. --------------===//
 432 //
 433 def : GINodeEquiv<G_SELECT, select>;
 434 let mayLoad = 1 in {
 435   def INSN2 : I<(outs GPR32:$dst), (ins GPR32Op:$src1, complex:$src2, complex:$src3), []>;
 436 }
 437 def frag : PatFrag<(ops node:$a, node:$b, node:$c),
 438                    (select node:$a, node:$b, node:$c),
 439                    [{ return true; // C++ code }]> {
 440   let GISelPredicateCode = [{ return true; // C++ code }];
 441 }
 442 def : Pat<(frag GPR32:$src1, complex:$src2, complex:$src3),
 443           (INSN2 GPR32:$src1, complex:$src3, complex:$src2)>;
 444
 445 //===- Test a more complex multi-instruction match. -----------------------===//
 446 //
 447 // R00O-NEXT:  GIM_SwitchOpcode, /*MI*/0, /*[*/{{[0-9]+}}, {{[0-9]+}}, /*)*//*default:*//*Label [[DEFAULT_NUM:[0-9]+]]*/ [[DEFAULT:[0-9]+]],
 448 // R00O-NEXT:  /*TargetOpcode::G_ADD*//*Label [[CASE_ADD_NUM:[0-9]+]]*/ [[CASE_ADD:[0-9]+]],
 449 // R00O:       /*TargetOpcode::G_SUB*//*Label [[CASE_SUB_NUM:[0-9]+]]*/ [[CASE_SUB:[0-9]+]],
 450 // R00O:       // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]]
 451 // R00O:       // Label [[CASE_SUB_NUM]]: @[[CASE_SUB]]
 452 // R00O-NEXT:  GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ [[GROUP:[0-9]+]],
 453 // R00O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 454 // R00O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 455 // R00O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 456 // R00O-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 457 //
 458 // R00C:       GIM_Try, /*On fail goto*//*Label [[PREV_NUM:[0-9]+]]*/ [[PREV:[0-9]+]], // Rule ID 20 //
 459 // R00C:       // Label [[PREV_NUM]]: @[[PREV]]
 460 //
 461 // R00C-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], // Rule ID 0 //
 462 // R00C-NEXT:    GIM_CheckFeatures, GIFBS_HasA,
 463 // R00N-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 464 // R00N-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SUB,
 465 // R00N-NEXT:    // MIs[0] dst
 466 // R00N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 467 // R00N-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 468 // R00N-NEXT:    // MIs[0] Operand 1
 469 // R00N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 470 // R00C-NEXT:    GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
 471 // R00N-NEXT:    GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
 472 // R00C-NEXT:    GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB,
 473 // R00N-NEXT:    // MIs[1] Operand 0
 474 // R00N-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
 475 // R00N-NEXT:    // MIs[1] src1
 476 // R00C-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
 477 // R00O-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
 478 // R00N-NEXT:    GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 479 // R00N-NEXT:    // MIs[1] src2
 480 // R00N-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
 481 // R00N-NEXT:    GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
 482 // R00N-NEXT:    // MIs[0] Operand 2
 483 // R00N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 484 // R00O-NEXT:    GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 485 // R00O-NEXT:    GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
 486 // R00C-NEXT:    GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
 487 // R00N-NEXT:    GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
 488 // R00C-NEXT:    GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SUB,
 489 // R00N-NEXT:    // MIs[2] Operand 0
 490 // R00N-NEXT:    GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s32,
 491 // R00N-NEXT:    // MIs[2] src3
 492 // R00C-NEXT:    GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
 493 // R00O-NEXT:    GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
 494 // R00N-NEXT:    GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 495 // R00N-NEXT:    // MIs[2] src4
 496 // R00N-NEXT:    GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
 497 // R00N-NEXT:    GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
 498 // R00O-NEXT:    GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 499 // R00O-NEXT:    GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
 500 // R00C-NEXT:    GIM_CheckIsSafeToFold, /*InsnID*/1,
 501 // R00C-NEXT:    GIM_CheckIsSafeToFold, /*InsnID*/2,
 502 // R00C-NEXT:    // (sub:{ *:[i32] } (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2), (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src3, GPR32:{ *:[i32] }:$src4)) => (INSNBOB:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src3, GPR32:{ *:[i32] }:$src4)
 503 // R00C-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::INSNBOB,
 504 // R00C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 505 // R00C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
 506 // R00C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
 507 // R00C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src3
 508 // R00C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src4
 509 // R00C-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 510 // R00C-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 511 // R00C-NEXT:    // GIR_Coverage, 0,
 512 // R00C-NEXT:    GIR_Done,
 513 // R00C-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 514 //
 515 // R00O-NEXT:  GIM_Reject,
 516 // R00O-NEXT:  // Label [[GROUP_NUM]]: @[[GROUP]]
 517 // R00O-NEXT:  GIM_Reject,
 518 // R00O:       // Label [[DEFAULT_NUM]]: @[[DEFAULT]]
 519 // R00O-NEXT:  GIM_Reject,
 520 // R00O-NEXT:  };
 521
 522 def INSNBOB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3, GPR32:$src4),
 523                  [(set GPR32:$dst,
 524                       (sub (sub GPR32:$src1, GPR32:$src2), (sub GPR32:$src3, GPR32:$src4)))]>,
 525                Requires<[HasA]>;
 526
 527 //===- Test a simple pattern with an intrinsic. ---------------------------===//
 528 //
 529 // R01O-NEXT:  GIM_SwitchOpcode, /*MI*/0, /*[*/{{[0-9]+}}, {{[0-9]+}}, /*)*//*default:*//*Label [[DEFAULT_NUM:[0-9]+]]*/ [[DEFAULT:[0-9]+]],
 530 // R01O-NEXT:  /*TargetOpcode::G_ADD*//*Label [[CASE_ADD_NUM:[0-9]+]]*/ [[CASE_ADD:[0-9]+]],
 531 // R01O:       /*TargetOpcode::G_INTRINSIC*//*Label [[CASE_INTRINSIC_NUM:[0-9]+]]*/ [[CASE_INTRINSIC:[0-9]+]],
 532 // R01O:       // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]]
 533 // R01O:       // Label [[CASE_INTRINSIC_NUM]]: @[[CASE_INTRINSIC]]
 534 //
 535 // R01N:       GIM_Try, /*On fail goto*//*Label [[PREV_NUM:[0-9]+]]*/ [[PREV:[0-9]+]], // Rule ID 0 //
 536 // R01N:       // Label [[PREV_NUM]]: @[[PREV]]
 537 //
 538 // R01C-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], // Rule ID 1 //
 539 // R01C-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 540 //
 541 // R01O-NEXT:    GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mytarget_nop,
 542 // R01O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 543 // R01O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 544 // R01O-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 545 //
 546 // R01N-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC,
 547 // R01N-NEXT:    // MIs[0] dst
 548 // R01N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 549 // R01N-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 550 // R01N-NEXT:    // MIs[0] Operand 1
 551 // R01N-NEXT:    GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mytarget_nop,
 552 // R01N-NEXT:    // MIs[0] src1
 553 // R01N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 554 //
 555 // R01C-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
 556 // R01C-NEXT:    // (intrinsic_wo_chain:{ *:[i32] } [[ID:[0-9]+]]:{ *:[iPTR] }, GPR32:{ *:[i32] }:$src1) => (MOV:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
 557 // R01C-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOV,
 558 // R01C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 559 // R01C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
 560 // R01C-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 561 // R01C-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 562 // R01C-NEXT:    // GIR_Coverage, 1,
 563 // R01C-NEXT:    GIR_Done,
 564 // R01C-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 565 //
 566 // R01O-NEXT:  GIM_Reject,
 567 // R01O:       // Label [[DEFAULT_NUM]]: @[[DEFAULT]]
 568 // R01O-NEXT:  GIM_Reject,
 569
 570 def MOV : I<(outs GPR32:$dst), (ins GPR32:$src1),
 571             [(set GPR32:$dst, (int_mytarget_nop GPR32:$src1))]>;
 572
 573 //===- Test a simple pattern with a default operand. ----------------------===//
 574 //
 575 // R02O-NEXT:  GIM_SwitchOpcode, /*MI*/0, /*[*/{{[0-9]+}}, {{[0-9]+}}, /*)*//*default:*//*Label [[DEFAULT_NUM:[0-9]+]]*/ [[DEFAULT:[0-9]+]],
 576 // R02O-NEXT:  /*TargetOpcode::G_ADD*//*Label [[CASE_ADD_NUM:[0-9]+]]*/ [[CASE_ADD:[0-9]+]],
 577 // R02O:       /*TargetOpcode::G_XOR*//*Label [[CASE_XOR_NUM:[0-9]+]]*/ [[CASE_XOR:[0-9]+]],
 578 // R02O:       // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]]
 579 // R02O:       // Label [[CASE_XOR_NUM]]: @[[CASE_XOR]]
 580 // R02O-NEXT:  GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ [[GROUP:[0-9]+]],
 581 // R02O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 582 // R02O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 583 // R02O-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 584 // R02O-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 585 // R02O-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 586 //
 587 // R02N:       GIM_Try, /*On fail goto*//*Label [[PREV_NUM:[0-9]+]]*/ [[PREV:[0-9]+]], // Rule ID 1 //
 588 // R02N:       // Label [[PREV_NUM]]: @[[PREV]]
 589 //
 590 // R02C-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], // Rule ID 2 //
 591 //
 592 // R02N-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 593 // R02N-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_XOR,
 594 // R02N-NEXT:    // MIs[0] dst
 595 // R02N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 596 // R02N-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 597 // R02N-NEXT:    // MIs[0] src1
 598 // R02N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 599 // R02N-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 600 // R02N-NEXT:    // MIs[0] Operand 2
 601 // R02N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 602 //
 603 // R02C-NEXT:    GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -2
 604 // R02C-NEXT:    // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -2:{ *:[i32] }) => (XORI:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
 605 // R02C-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::XORI,
 606 // R02C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 607 // R02C-NEXT:    GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
 608 // R02C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
 609 // R02C-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 610 // R02C-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 611 // R02C-NEXT:    // GIR_Coverage, 2,
 612 // R02C-NEXT:    GIR_Done,
 613 // R02C-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 614 //
 615 // R02O:       // Label [[DEFAULT_NUM]]: @[[DEFAULT]]
 616 // R02O-NEXT:  GIM_Reject,
 617
 618 // The -2 is just to distinguish it from the 'not' case below.
 619 def XORI : I<(outs GPR32:$dst), (ins m1:$src2, GPR32:$src1),
 620              [(set GPR32:$dst, (xor GPR32:$src1, -2))]>;
 621
 622 //===- Test a simple pattern with a default register operand. -------------===//
 623 //
 624 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 625 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 626 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_XOR,
 627 // NOOPT-NEXT:    // MIs[0] dst
 628 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 629 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 630 // NOOPT-NEXT:    // MIs[0] src1
 631 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 632 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 633 // NOOPT-NEXT:    // MIs[0] Operand 2
 634 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 635 // NOOPT-NEXT:    GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -3
 636 // NOOPT-NEXT:    // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -3:{ *:[i32] }) => (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
 637 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::XOR,
 638 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 639 // NOOPT-NEXT:    GIR_AddRegister, /*InsnID*/0, MyTarget::R0,
 640 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
 641 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 642 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 643 // NOOPT-NEXT:    // GIR_Coverage, 3,
 644 // NOOPT-NEXT:    GIR_Done,
 645 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 646
 647 // The -3 is just to distinguish it from the 'not' case below and the other default op case above.
 648 def XOR : I<(outs GPR32:$dst), (ins Z:$src2, GPR32:$src1),
 649             [(set GPR32:$dst, (xor GPR32:$src1, -3))]>;
 650
 651 //===- Test a simple pattern with a multiple default operands. ------------===//
 652 //
 653 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 654 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 655 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_XOR,
 656 // NOOPT-NEXT:    // MIs[0] dst
 657 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 658 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 659 // NOOPT-NEXT:    // MIs[0] src1
 660 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 661 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 662 // NOOPT-NEXT:    // MIs[0] Operand 2
 663 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 664 // NOOPT-NEXT:    GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -4
 665 // NOOPT-NEXT:    // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -4:{ *:[i32] }) => (XORlike:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
 666 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::XORlike,
 667 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 668 // NOOPT-NEXT:    GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
 669 // NOOPT-NEXT:    GIR_AddRegister, /*InsnID*/0, MyTarget::R0,
 670 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
 671 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 672 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 673 // NOOPT-NEXT:    // GIR_Coverage, 4,
 674 // NOOPT-NEXT:    GIR_Done,
 675 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 676
 677 // The -4 is just to distinguish it from the other 'not' cases.
 678 def XORlike : I<(outs GPR32:$dst), (ins m1Z:$src2, GPR32:$src1),
 679                 [(set GPR32:$dst, (xor GPR32:$src1, -4))]>;
 680
 681 //===- Test a simple pattern with multiple operands with defaults. --------===//
 682 //
 683 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 684 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 685 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_XOR,
 686 // NOOPT-NEXT:    // MIs[0] dst
 687 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 688 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 689 // NOOPT-NEXT:    // MIs[0] src1
 690 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 691 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 692 // NOOPT-NEXT:    // MIs[0] Operand 2
 693 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 694 // NOOPT-NEXT:    GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -5,
 695 // NOOPT-NEXT:    // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -5:{ *:[i32] }) => (XORManyDefaults:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
 696 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::XORManyDefaults,
 697 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 698 // NOOPT-NEXT:    GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
 699 // NOOPT-NEXT:    GIR_AddRegister, /*InsnID*/0, MyTarget::R0,
 700 // NOOPT-NEXT:    GIR_AddRegister, /*InsnID*/0, MyTarget::R0,
 701 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
 702 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 703 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 704 // NOOPT-NEXT:    // GIR_Coverage, 5,
 705 // NOOPT-NEXT:    GIR_Done,
 706 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 707
 708 // The -5 is just to distinguish it from the other cases.
 709 def XORManyDefaults : I<(outs GPR32:$dst), (ins m1Z:$src3, Z:$src2, GPR32:$src1),
 710                         [(set GPR32:$dst, (xor GPR32:$src1, -5))]>;
 711
 712 //===- Test a simple pattern with constant immediate operands. ------------===//
 713 //
 714 // This must precede the 3-register variants because constant immediates have
 715 // priority over register banks.
 716 //
 717 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 718 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 719 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_XOR,
 720 // NOOPT-NEXT:    // MIs[0] dst
 721 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 722 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 723 // NOOPT-NEXT:    // MIs[0] Wm
 724 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 725 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 726 // NOOPT-NEXT:    // MIs[0] Operand 2
 727 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 728 // NOOPT-NEXT:    GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
 729 // NOOPT-NEXT:    // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Wm, -1:{ *:[i32] }) => (ORN:{ *:[i32] } R0:{ *:[i32] }, GPR32:{ *:[i32] }:$Wm)
 730 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::ORN,
 731 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 732 // NOOPT-NEXT:    GIR_AddRegister, /*InsnID*/0, MyTarget::R0,
 733 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Wm
 734 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 735 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 736 // NOOPT-NEXT:    // GIR_Coverage, 22,
 737 // NOOPT-NEXT:    GIR_Done,
 738 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 739
 740 def ORN : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
 741 def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>;
 742
 743 //===- Test a nested instruction match. -----------------------------------===//
 744 //
 745 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 746 // NOOPT-NEXT:    GIM_CheckFeatures, GIFBS_HasA,
 747 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 748 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL,
 749 // NOOPT-NEXT:    // MIs[0] dst
 750 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 751 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 752 // NOOPT-NEXT:    // MIs[0] Operand 1
 753 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 754 // NOOPT-NEXT:    GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
 755 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
 756 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
 757 // NOOPT-NEXT:    // MIs[1] Operand 0
 758 // NOOPT-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
 759 // NOOPT-NEXT:    // MIs[1] src1
 760 // NOOPT-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
 761 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 762 // NOOPT-NEXT:    // MIs[1] src2
 763 // NOOPT-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
 764 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
 765 // NOOPT-NEXT:    // MIs[0] src3
 766 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 767 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
 768 // NOOPT-NEXT:    GIM_CheckIsSafeToFold, /*InsnID*/1,
 769 // NOOPT-NEXT:    // (mul:{ *:[i32] } (add:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2), GPR32:{ *:[i32] }:$src3)  =>  (MULADD:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src3)
 770 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MULADD,
 771 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 772 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
 773 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
 774 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src3
 775 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 776 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 777 // NOOPT-NEXT:    // GIR_Coverage, 6,
 778 // NOOPT-NEXT:    GIR_Done,
 779 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 780
 781 // We also get a second rule by commutativity.
 782 //
 783 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 784 // NOOPT-NEXT:    GIM_CheckFeatures, GIFBS_HasA,
 785 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 786 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL,
 787 // NOOPT-NEXT:    // MIs[0] dst
 788 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 789 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 790 // NOOPT-NEXT:    // MIs[0] src3
 791 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 792 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 793 // NOOPT-NEXT:    // MIs[0] Operand 2
 794 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 795 // NOOPT-NEXT:    GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2,
 796 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
 797 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
 798 // NOOPT-NEXT:    // MIs[1] Operand 0
 799 // NOOPT-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32,
 800 // NOOPT-NEXT:    // MIs[1] src1
 801 // NOOPT-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
 802 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 803 // NOOPT-NEXT:    // MIs[1] src2
 804 // NOOPT-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
 805 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
 806 // NOOPT-NEXT:    GIM_CheckIsSafeToFold, /*InsnID*/1,
 807 // NOOPT-NEXT:    // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src3, (add:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2))  =>  (MULADD:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src3)
 808 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MULADD,
 809 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 810 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
 811 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
 812 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src3
 813 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 814 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 815 // NOOPT-NEXT:    // GIR_Coverage, 26,
 816 // NOOPT-NEXT:    GIR_Done,
 817 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 818
 819 def MULADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3),
 820                [(set GPR32:$dst,
 821                      (mul (add GPR32:$src1, GPR32:$src2), GPR32:$src3))]>,
 822              Requires<[HasA]>;
 823
 824 //===- Test a simple pattern with just a specific leaf immediate. ---------===//
 825 //
 826 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 827 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 828 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_CONSTANT,
 829 // NOOPT-NEXT:    // MIs[0] dst
 830 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 831 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 832 // NOOPT-NEXT:    // MIs[0] Operand 1
 833 // NOOPT-NEXT:    GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, 1,
 834 // NOOPT-NEXT:    // 1:{ *:[i32] }  =>  (MOV1:{ *:[i32] })
 835 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOV1,
 836 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 837 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 838 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 839 // NOOPT-NEXT:    // GIR_Coverage, 7,
 840 // NOOPT-NEXT:    GIR_Done,
 841 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 842
 843 def MOV1 : I<(outs GPR32:$dst), (ins), [(set GPR32:$dst, 1)]>;
 844
 845 //===- Test a simple pattern with a leaf immediate and a predicate. -------===//
 846 //
 847 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 848 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 849 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_CONSTANT,
 850 // NOOPT-NEXT:    GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GICXXPred_I64_Predicate_simm8,
 851 // NOOPT-NEXT:    // MIs[0] dst
 852 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 853 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 854 // NOOPT-NEXT:    // MIs[0] Operand 1
 855 // NOOPT-NEXT:    // No operand predicates
 856 // NOOPT-NEXT:    // (imm:{ *:[i32] })<<P:Predicate_simm8>>:$imm => (MOVimm8:{ *:[i32] } (imm:{ *:[i32] }):$imm)
 857 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOVimm8,
 858 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 859 // NOOPT-NEXT:    GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
 860 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 861 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 862 // NOOPT-NEXT:    // GIR_Coverage, 8,
 863 // NOOPT-NEXT:    GIR_Done,
 864 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 865
 866 def simm8 : ImmLeaf<i32, [{ return isInt<8>(Imm); }]>;
 867 def MOVimm8 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, simm8:$imm)]>;
 868
 869 //===- Same again but use an IntImmLeaf. ----------------------------------===//
 870 //
 871 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 872 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 873 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_CONSTANT,
 874 // NOOPT-NEXT:    GIM_CheckAPIntImmPredicate, /*MI*/0, /*Predicate*/GICXXPred_APInt_Predicate_simm9,
 875 // NOOPT-NEXT:    // MIs[0] dst
 876 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 877 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 878 // NOOPT-NEXT:    // MIs[0] Operand 1
 879 // NOOPT-NEXT:    // No operand predicates
 880 // NOOPT-NEXT:    // (imm:{ *:[i32] })<<P:Predicate_simm9>>:$imm =>  (MOVimm9:{ *:[i32] } (imm:{ *:[i32] }):$imm)
 881 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOVimm9,
 882 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 883 // NOOPT-NEXT:    GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
 884 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 885 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 886 // NOOPT-NEXT:    // GIR_Coverage, 9,
 887 // NOOPT-NEXT:    GIR_Done,
 888 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 889
 890 def simm9 : IntImmLeaf<i32, [{ return isInt<9>(Imm->getSExtValue()); }]>;
 891 def MOVimm9 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, simm9:$imm)]>;
 892
 893 //===- Test a pattern with a custom renderer. -----------------------------===//
 894 //
 895 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 896 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 897 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_CONSTANT,
 898 // NOOPT-NEXT:    GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GICXXPred_I64_Predicate_cimm8,
 899 // NOOPT-NEXT:    // MIs[0] dst
 900 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 901 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 902 // NOOPT-NEXT:    // MIs[0] Operand 1
 903 // NOOPT-NEXT:    // No operand predicates
 904 // NOOPT-NEXT:    // (imm:{ *:[i32] })<<P:Predicate_cimm8>><<X:cimm8_xform>>:$imm  =>  (MOVcimm8:{ *:[i32] } (cimm8_xform:{ *:[i32] } (imm:{ *:[i32] }):$imm))
 905 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOVcimm8,
 906 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 907 // NOOPT-NEXT:    GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GICR_renderImm, // imm
 908 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 909 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 910 // NOOPT-NEXT:    // GIR_Coverage, 10,
 911 // NOOPT-NEXT:    GIR_Done,
 912 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 913
 914 def MOVcimm8 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, cimm8:$imm)]>;
 915
 916 //===- Test a simple pattern with a FP immediate and a predicate. ---------===//
 917 //
 918 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 919 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 920 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FCONSTANT,
 921 // NOOPT-NEXT:    GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GICXXPred_APFloat_Predicate_fpimmz,
 922 // NOOPT-NEXT:    // MIs[0] dst
 923 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 924 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::FPR32RegClassID,
 925 // NOOPT-NEXT:    // MIs[0] Operand 1
 926 // NOOPT-NEXT:    // No operand predicates
 927 // NOOPT-NEXT:    // (fpimm:{ *:[f32] })<<P:Predicate_fpimmz>>:$imm =>  (MOVfpimmz:{ *:[f32] } (fpimm:{ *:[f32] }):$imm)
 928 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOVfpimmz,
 929 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 930 // NOOPT-NEXT:    GIR_CopyFConstantAsFPImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
 931 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 932 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 933 // NOOPT-NEXT:    // GIR_Coverage, 17,
 934 // NOOPT-NEXT:    GIR_Done,
 935 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 936
 937 //===- Test a simple pattern with inferred pointer operands. ---------------===//
 938 //
 939 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 940 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 941 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LOAD,
 942 // NOOPT-NEXT:    GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
 943 // NOOPT-NEXT:    GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
 944 // NOOPT-NEXT:    // MIs[0] dst
 945 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 946 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 947 // NOOPT-NEXT:    // MIs[0] src1
 948 // NOOPT-NEXT:    GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
 949 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 950 // NOOPT-NEXT:    // (ld:{ *:[i32] } GPR32:{ *:[i32] }:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
 951 // NOOPT-NEXT:    GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::LOAD,
 952 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 953 // NOOPT-NEXT:    // GIR_Coverage, 11,
 954 // NOOPT-NEXT:    GIR_Done,
 955 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 956
 957 def LOAD : I<(outs GPR32:$dst), (ins GPR32:$src1),
 958             [(set GPR32:$dst, (load GPR32:$src1))]>;
 959
 960 //===- Test a simple pattern with explicit pointer operands. ---------------===//
 961
 962 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 963 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 964 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LOAD,
 965 // NOOPT-NEXT:    GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
 966 // NOOPT-NEXT:    GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
 967 // NOOPT-NEXT:    // MIs[0] dst
 968 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_p0s32,
 969 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 970 // NOOPT-NEXT:    // MIs[0] src
 971 // NOOPT-NEXT:    GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
 972 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 973 // NOOPT-NEXT:    // (ld:{ *:[i32] } GPR32:{ *:[i32] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LOAD:{ *:[i32] } GPR32:{ *:[i32] }:$src)
 974 // NOOPT-NEXT:    GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::LOAD,
 975 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 976 // NOOPT-NEXT:    // GIR_Coverage, 23,
 977 // NOOPT-NEXT:    GIR_Done,
 978 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 979
 980 def : Pat<(load GPR32:$src),
 981           (p0 (LOAD GPR32:$src))>;
 982
 983 //===- Test a simple pattern with a sextload -------------------------------===//
 984 //
 985 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 986 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 987 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SEXTLOAD,
 988 // NOOPT-NEXT:    GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
 989 // NOOPT-NEXT:    GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
 990 // NOOPT-NEXT:    // MIs[0] dst
 991 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 992 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 993 // NOOPT-NEXT:    // MIs[0] src1
 994 // NOOPT-NEXT:    GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
 995 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 996 // NOOPT-NEXT:    // (ld:{ *:[i32] } GPR32:{ *:[i32] }:$src1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (SEXTLOAD:{ *:[i32] } GPR32:{ *:[i32] }:$src1)
 997 // NOOPT-NEXT:    GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::SEXTLOAD,
 998 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 999 // NOOPT-NEXT:    // GIR_Coverage, 12,
1000 // NOOPT-NEXT:    GIR_Done,
1001 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
1002
1003 def SEXTLOAD : I<(outs GPR32:$dst), (ins GPR32:$src1),
1004                  [(set GPR32:$dst, (sextloadi16 GPR32:$src1))]>;
1005
1006 //===- Test a simple pattern with regclass operands. ----------------------===//
1007 //
1008 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
1009 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
1010 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD,
1011 // NOOPT-NEXT:    // MIs[0] dst
1012 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
1013 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
1014 // NOOPT-NEXT:    // MIs[0] src1
1015 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1016 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID
1017 // NOOPT-NEXT:    // MIs[0] src2
1018 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1019 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
1020 // NOOPT-NEXT:    // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) => (ADD:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2)
1021 // NOOPT-NEXT:    GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::ADD,
1022 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1023 // NOOPT-NEXT:    // GIR_Coverage, 13,
1024 // NOOPT-NEXT:    GIR_Done,
1025 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
1026
1027 def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2),
1028             [(set GPR32:$dst, (add GPR32:$src1, GPR32:$src2))]>;
1029
1030 //===- Test a pattern with a tied operand in the matcher ------------------===//
1031 //
1032 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
1033 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
1034 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD,
1035 // NOOPT-NEXT:    // MIs[0] dst
1036 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
1037 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
1038 // NOOPT-NEXT:    // MIs[0] src{{$}}
1039 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1040 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
1041 // NOOPT-NEXT:    // MIs[0] src{{$}}
1042 // NOOPT-NEXT:    GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
1043 // NOOPT-NEXT:    // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src) => (DOUBLE:{ *:[i32] } GPR32:{ *:[i32] }:$src)
1044 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::DOUBLE,
1045 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1046 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
1047 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
1048 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1049 // NOOPT-NEXT:    // GIR_Coverage, 14,
1050 // NOOPT-NEXT:    GIR_Done,
1051 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
1052
1053 def DOUBLE : I<(outs GPR32:$dst), (ins GPR32:$src), [(set GPR32:$dst, (add GPR32:$src, GPR32:$src))]>;
1054
1055 //===- Test a simple pattern with ValueType operands. ----------------------===//
1056 //
1057 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
1058 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
1059 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD,
1060 // NOOPT-NEXT:    // MIs[0] dst
1061 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
1062 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
1063 // NOOPT-NEXT:    // MIs[0] src1
1064 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1065 // NOOPT-NEXT:    // MIs[0] src2
1066 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1067 // NOOPT-NEXT:    // (add:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) => (ADD:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
1068 // NOOPT-NEXT:    GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::ADD,
1069 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1070 // NOOPT-NEXT:    // GIR_Coverage, 24,
1071 // NOOPT-NEXT:    GIR_Done,
1072 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
1073
1074 def : Pat<(add i32:$src1, i32:$src2),
1075           (ADD i32:$src1, i32:$src2)>;
1076
1077 //===- Test another simple pattern with regclass operands. ----------------===//
1078 //
1079 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
1080 // NOOPT-NEXT:    GIM_CheckFeatures, GIFBS_HasA_HasB_HasC,
1081 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
1082 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL,
1083 // NOOPT-NEXT:    // MIs[0] dst
1084 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
1085 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
1086 // NOOPT-NEXT:    // MIs[0] src1
1087 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1088 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
1089 // NOOPT-NEXT:    // MIs[0] src2
1090 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
1091 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
1092 // NOOPT-NEXT:    // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) => (MUL:{ *:[i32] } GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src1)
1093 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MUL,
1094 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1095 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
1096 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
1097 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
1098 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1099 // NOOPT-NEXT:    // GIR_Coverage, 15,
1100 // NOOPT-NEXT:    GIR_Done,
1101 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
1102
1103 def MUL : I<(outs GPR32:$dst), (ins GPR32:$src2, GPR32:$src1),
1104              [(set GPR32:$dst, (mul GPR32:$src1, GPR32:$src2))]>,
1105           Requires<[HasA, HasB, HasC]>;
1106
1107 //===- Test a COPY_TO_REGCLASS --------------------------------------------===//
1108 //
1109 //
1110 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
1111 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
1112 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_BITCAST,
1113 // NOOPT-NEXT:    // MIs[0] dst
1114 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
1115 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
1116 // NOOPT-NEXT:    // MIs[0] src1
1117 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
1118 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::FPR32RegClassID,
1119 // NOOPT-NEXT:    // (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$src1) => (COPY_TO_REGCLASS:{ *:[i32] } FPR32:{ *:[f32] }:$src1, GPR32:{ *:[i32] })
1120 // NOOPT-NEXT:    GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
1121 // NOOPT-NEXT:    GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, MyTarget::GPR32RegClassID,
1122 // NOOPT-NEXT:    // GIR_Coverage, 25,
1123 // NOOPT-NEXT:    GIR_Done,
1124 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
1125
1126 def : Pat<(i32 (bitconvert FPR32:$src1)),
1127           (COPY_TO_REGCLASS FPR32:$src1, GPR32)>;
1128
1129 //===- Test a simple pattern with just a leaf immediate. ------------------===//
1130 //
1131 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
1132 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
1133 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_CONSTANT,
1134 // NOOPT-NEXT:    // MIs[0] dst
1135 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
1136 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
1137 // NOOPT-NEXT:    // MIs[0] Operand 1
1138 // NOOPT-NEXT:    // No operand predicates
1139 // NOOPT-NEXT:    // (imm:{ *:[i32] }):$imm =>  (MOVimm:{ *:[i32] } (imm:{ *:[i32] }):$imm)
1140 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOVimm,
1141 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
1142 // NOOPT-NEXT:    GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
1143 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
1144 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1145 // NOOPT-NEXT:    // GIR_Coverage, 16,
1146 // NOOPT-NEXT:    GIR_Done,
1147 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
1148
1149 def MOVimm : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, imm:$imm)]>;
1150
1151 def fpimmz : FPImmLeaf<f32, [{ return Imm->isExactlyValue(0.0); }]>;
1152 def MOVfpimmz : I<(outs FPR32:$dst), (ins f32imm:$imm), [(set FPR32:$dst, fpimmz:$imm)]>;
1153
1154 //===- Test a pattern with an MBB operand. --------------------------------===//
1155 //
1156 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
1157 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/1,
1158 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_BR,
1159 // NOOPT-NEXT:    // MIs[0] target
1160 // NOOPT-NEXT:    GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
1161 // NOOPT-NEXT:    // (br (bb:{ *:[Other] }):$target) => (BR (bb:{ *:[Other] }):$target)
1162 // NOOPT-NEXT:    GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::BR,
1163 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
1164 // NOOPT-NEXT:    // GIR_Coverage, 18,
1165 // NOOPT-NEXT:    GIR_Done,
1166 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
1167
1168 def BR : I<(outs), (ins unknown:$target),
1169             [(br bb:$target)]>;
1170
1171 // NOOPT-NEXT:    GIM_Reject,
1172 // NOOPT-NEXT:  };
1173 // NOOPT-NEXT:  return MatchTable0;