llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-stats.s

   1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
   2 # RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --all-stats --iterations=2 < %s | FileCheck %s
   3
   4 ldr     w4, [x2], #4
   5 ldr     w5, [x3]
   6 madd    w0, w5, w4, w0
   7 add     x3, x3, x13
   8 subs    x1, x1, #1
   9 str     w0, [x21, x18, lsl #2]
  10
  11 # CHECK:      Iterations:        2
  12 # CHECK-NEXT: Instructions:      12
  13 # CHECK-NEXT: Total Cycles:      17
  14 # CHECK-NEXT: Total uOps:        14
  15
  16 # CHECK:      Dispatch Width:    2
  17 # CHECK-NEXT: uOps Per Cycle:    0.82
  18 # CHECK-NEXT: IPC:               0.71
  19 # CHECK-NEXT: Block RThroughput: 3.5
  20
  21 # CHECK:      Instruction Info:
  22 # CHECK-NEXT: [1]: #uOps
  23 # CHECK-NEXT: [2]: Latency
  24 # CHECK-NEXT: [3]: RThroughput
  25 # CHECK-NEXT: [4]: MayLoad
  26 # CHECK-NEXT: [5]: MayStore
  27 # CHECK-NEXT: [6]: HasSideEffects (U)
  28
  29 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
  30 # CHECK-NEXT:  2      3     1.00    *                   ldr     w4, [x2], #4
  31 # CHECK-NEXT:  1      3     1.00    *                   ldr     w5, [x3]
  32 # CHECK-NEXT:  1      4     1.00                        madd    w0, w5, w4, w0
  33 # CHECK-NEXT:  1      3     0.50                        add     x3, x3, x13
  34 # CHECK-NEXT:  1      3     0.50                        subs    x1, x1, #1
  35 # CHECK-NEXT:  1      1     1.00           *            str     w0, [x21, x18, lsl #2]
  36
  37 # CHECK:      Dynamic Dispatch Stall Cycles:
  38 # CHECK-NEXT: RAT     - Register unavailable:                      8  (47.1%)
  39 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
  40 # CHECK-NEXT: SCHEDQ  - Scheduler full:                            0
  41 # CHECK-NEXT: LQ      - Load queue full:                           0
  42 # CHECK-NEXT: SQ      - Store queue full:                          0
  43 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
  44 # CHECK-NEXT: USH     - Uncategorised Structural Hazard:           0
  45
  46 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
  47 # CHECK-NEXT: [# dispatched], [# cycles]
  48 # CHECK-NEXT:  0,              7  (41.2%)
  49 # CHECK-NEXT:  1,              6  (35.3%)
  50 # CHECK-NEXT:  2,              4  (23.5%)
  51
  52 # CHECK:      Schedulers - number of cycles where we saw N micro opcodes issued:
  53 # CHECK-NEXT: [# issued], [# cycles]
  54 # CHECK-NEXT:  0,          7  (41.2%)
  55 # CHECK-NEXT:  1,          6  (35.3%)
  56 # CHECK-NEXT:  2,          4  (23.5%)
  57
  58 # CHECK:      Scheduler's queue usage:
  59 # CHECK-NEXT: No scheduler resources used.
  60
  61 # CHECK:      Register File statistics:
  62 # CHECK-NEXT: Total number of mappings created:    14
  63 # CHECK-NEXT: Max number of mappings used:         4
  64
  65 # CHECK:      Resources:
  66 # CHECK-NEXT: [0.0] - CortexA55UnitALU
  67 # CHECK-NEXT: [0.1] - CortexA55UnitALU
  68 # CHECK-NEXT: [1]   - CortexA55UnitB
  69 # CHECK-NEXT: [2]   - CortexA55UnitDiv
  70 # CHECK-NEXT: [3.0] - CortexA55UnitFPALU
  71 # CHECK-NEXT: [3.1] - CortexA55UnitFPALU
  72 # CHECK-NEXT: [4]   - CortexA55UnitFPDIV
  73 # CHECK-NEXT: [5.0] - CortexA55UnitFPMAC
  74 # CHECK-NEXT: [5.1] - CortexA55UnitFPMAC
  75 # CHECK-NEXT: [6]   - CortexA55UnitLd
  76 # CHECK-NEXT: [7]   - CortexA55UnitMAC
  77 # CHECK-NEXT: [8]   - CortexA55UnitSt
  78
  79 # CHECK:      Resource pressure per iteration:
  80 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3.0]  [3.1]  [4]    [5.0]  [5.1]  [6]    [7]    [8]
  81 # CHECK-NEXT: 1.00   1.00    -      -      -      -      -      -      -     2.00   1.00   1.00
  82
  83 # CHECK:      Resource pressure by instruction:
  84 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3.0]  [3.1]  [4]    [5.0]  [5.1]  [6]    [7]    [8]    Instructions:
  85 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -     1.00    -      -     ldr   w4, [x2], #4
  86 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -     1.00    -      -     ldr   w5, [x3]
  87 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -     1.00    -     madd  w0, w5, w4, w0
  88 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -     add   x3, x3, x13
  89 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -     subs  x1, x1, #1
  90 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -     1.00   str   w0, [x21, x18, lsl #2]