llvm/test/tools/llvm-mca/AArch64/Cortex/shifted-register.s

   1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
   2 # RUN: llvm-mca -march=aarch64 -mcpu=cortex-a57 -resource-pressure=false < %s | FileCheck %s
   3
   4   add   w0, w1, w2, lsl #0
   5   sub   x3, x4, x5, lsl #1
   6   adds  x6, x7, x8, lsr #2
   7   subs  x9, x10, x11, asr #3
   8
   9 # CHECK:      Iterations:        100
  10 # CHECK-NEXT: Instructions:      400
  11 # CHECK-NEXT: Total Cycles:      304
  12 # CHECK-NEXT: Total uOps:        400
  13
  14 # CHECK:      Dispatch Width:    3
  15 # CHECK-NEXT: uOps Per Cycle:    1.32
  16 # CHECK-NEXT: IPC:               1.32
  17 # CHECK-NEXT: Block RThroughput: 3.0
  18
  19 # CHECK:      Instruction Info:
  20 # CHECK-NEXT: [1]: #uOps
  21 # CHECK-NEXT: [2]: Latency
  22 # CHECK-NEXT: [3]: RThroughput
  23 # CHECK-NEXT: [4]: MayLoad
  24 # CHECK-NEXT: [5]: MayStore
  25 # CHECK-NEXT: [6]: HasSideEffects (U)
  26
  27 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
  28 # CHECK-NEXT:  1      1     0.50                        add     w0, w1, w2
  29 # CHECK-NEXT:  1      2     1.00                        sub     x3, x4, x5, lsl #1
  30 # CHECK-NEXT:  1      2     1.00                        adds    x6, x7, x8, lsr #2
  31 # CHECK-NEXT:  1      2     1.00                        subs    x9, x10, x11, asr #3