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[clang][modules] Don't prevent translation of FW_Private includes when explicitly...
[llvm-project.git] / llvm / test / tools / llvm-mca / RISCV / SiFive7 / reductions.s
blob11d0fbed87244f49abe02a80c6e4070abc14174c
1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2 # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s | FileCheck %s
3
4 # Single-Width Integer Reductions
5 vsetvli zero, zero, e8, mf8, tu, mu
6 vredsum.vs v4, v8, v12
7 vsetvli zero, zero, e8, mf4, tu, mu
8 vredsum.vs v4, v8, v12
9 vsetvli zero, zero, e8, mf2, tu, mu
10 vredsum.vs v4, v8, v12
11 vsetvli zero, zero, e8, m1, tu, mu
12 vredsum.vs v4, v8, v12
13 vsetvli zero, zero, e8, m2, tu, mu
14 vredsum.vs v4, v8, v12
15 vsetvli zero, zero, e8, m4, tu, mu
16 vredsum.vs v4, v8, v12
17 vsetvli zero, zero, e8, m8, tu, mu
18 vredsum.vs v4, v8, v12
19 vsetvli zero, zero, e16, mf4, tu, mu
20 vredand.vs v4, v8, v12
21 vsetvli zero, zero, e16, mf2, tu, mu
22 vredand.vs v4, v8, v12
23 vsetvli zero, zero, e16, m1, tu, mu
24 vredand.vs v4, v8, v12
25 vsetvli zero, zero, e16, m2, tu, mu
26 vredand.vs v4, v8, v12
27 vsetvli zero, zero, e16, m4, tu, mu
28 vredand.vs v4, v8, v12
29 vsetvli zero, zero, e16, m8, tu, mu
30 vredand.vs v4, v8, v12
31 vsetvli zero, zero, e32, mf2, tu, mu
32 vredor.vs v4, v8, v12
33 vsetvli zero, zero, e32, m1, tu, mu
34 vredor.vs v4, v8, v12
35 vsetvli zero, zero, e32, m2, tu, mu
36 vredor.vs v4, v8, v12
37 vsetvli zero, zero, e32, m4, tu, mu
38 vredor.vs v4, v8, v12
39 vsetvli zero, zero, e32, m8, tu, mu
40 vredor.vs v4, v8, v12
41 vsetvli zero, zero, e64, m1, tu, mu
42 vredxor.vs v4, v8, v12
43 vsetvli zero, zero, e64, m2, tu, mu
44 vredxor.vs v4, v8, v12
45 vsetvli zero, zero, e64, m4, tu, mu
46 vredxor.vs v4, v8, v12
47 vsetvli zero, zero, e64, m8, tu, mu
48 vredxor.vs v4, v8, v12
49 # Single-Width Integer Min/Max Reductions
50 vsetvli zero, zero, e8, mf8, tu, mu
51 vredmaxu.vs v4, v8, v12
52 vsetvli zero, zero, e8, mf4, tu, mu
53 vredmaxu.vs v4, v8, v12
54 vsetvli zero, zero, e8, mf2, tu, mu
55 vredmaxu.vs v4, v8, v12
56 vsetvli zero, zero, e8, m1, tu, mu
57 vredmaxu.vs v4, v8, v12
58 vsetvli zero, zero, e8, m2, tu, mu
59 vredmaxu.vs v4, v8, v12
60 vsetvli zero, zero, e8, m4, tu, mu
61 vredmaxu.vs v4, v8, v12
62 vsetvli zero, zero, e8, m8, tu, mu
63 vredmaxu.vs v4, v8, v12
64 vsetvli zero, zero, e16, mf4, tu, mu
65 vredmax.vs v4, v8, v12
66 vsetvli zero, zero, e16, mf2, tu, mu
67 vredmax.vs v4, v8, v12
68 vsetvli zero, zero, e16, m1, tu, mu
69 vredmax.vs v4, v8, v12
70 vsetvli zero, zero, e16, m2, tu, mu
71 vredmax.vs v4, v8, v12
72 vsetvli zero, zero, e16, m4, tu, mu
73 vredmax.vs v4, v8, v12
74 vsetvli zero, zero, e16, m8, tu, mu
75 vredmax.vs v4, v8, v12
76 vsetvli zero, zero, e32, mf2, tu, mu
77 vredminu.vs v4, v8, v12
78 vsetvli zero, zero, e32, m1, tu, mu
79 vredminu.vs v4, v8, v12
80 vsetvli zero, zero, e32, m2, tu, mu
81 vredminu.vs v4, v8, v12
82 vsetvli zero, zero, e32, m4, tu, mu
83 vredminu.vs v4, v8, v12
84 vsetvli zero, zero, e32, m8, tu, mu
85 vredminu.vs v4, v8, v12
86 vsetvli zero, zero, e64, m1, tu, mu
87 vredmin.vs v4, v8, v12
88 vsetvli zero, zero, e64, m2, tu, mu
89 vredmin.vs v4, v8, v12
90 vsetvli zero, zero, e64, m4, tu, mu
91 vredmin.vs v4, v8, v12
92 vsetvli zero, zero, e64, m8, tu, mu
93 vredmin.vs v4, v8, v12
94 # Widening Integer Reductions
95 vsetvli zero, zero, e8, mf8, tu, mu
96 vwredsumu.vs v4, v8, v12
97 vsetvli zero, zero, e8, mf4, tu, mu
98 vwredsumu.vs v4, v8, v12
99 vsetvli zero, zero, e8, mf2, tu, mu
100 vwredsumu.vs v4, v8, v12
101 vsetvli zero, zero, e8, m1, tu, mu
102 vwredsumu.vs v4, v8, v12
103 vsetvli zero, zero, e8, m2, tu, mu
104 vwredsumu.vs v4, v8, v12
105 vsetvli zero, zero, e8, m4, tu, mu
106 vwredsumu.vs v4, v8, v12
107 vsetvli zero, zero, e8, m8, tu, mu
108 vwredsumu.vs v4, v8, v12
109 vsetvli zero, zero, e16, mf4, tu, mu
110 vwredsumu.vs v4, v8, v12
111 vsetvli zero, zero, e16, mf2, tu, mu
112 vwredsumu.vs v4, v8, v12
113 vsetvli zero, zero, e16, m1, tu, mu
114 vwredsumu.vs v4, v8, v12
115 vsetvli zero, zero, e16, m2, tu, mu
116 vwredsumu.vs v4, v8, v12
117 vsetvli zero, zero, e16, m4, tu, mu
118 vwredsumu.vs v4, v8, v12
119 vsetvli zero, zero, e16, m8, tu, mu
120 vwredsumu.vs v4, v8, v12
121 vsetvli zero, zero, e32, mf2, tu, mu
122 vwredsum.vs v4, v8, v12
123 vsetvli zero, zero, e32, m1, tu, mu
124 vwredsum.vs v4, v8, v12
125 vsetvli zero, zero, e32, m2, tu, mu
126 vwredsum.vs v4, v8, v12
127 vsetvli zero, zero, e32, m4, tu, mu
128 vwredsum.vs v4, v8, v12
129 vsetvli zero, zero, e32, m8, tu, mu
130 vwredsum.vs v4, v8, v12
131 vsetvli zero, zero, e64, m1, tu, mu
132 vwredsum.vs v4, v8, v12
133 vsetvli zero, zero, e64, m2, tu, mu
134 vwredsum.vs v4, v8, v12
135 vsetvli zero, zero, e64, m4, tu, mu
136 vwredsum.vs v4, v8, v12
137 vsetvli zero, zero, e64, m8, tu, mu
138 vwredsum.vs v4, v8, v12
139
140 # Vector Single-Width FP Reduction Instructions
141 # vfwredosum.vs
142 # SEW will not be e8, or e64
143 # LMUL will not be mf8
144 vsetvli zero, zero, e16, mf4, tu, mu
145 vfwredosum.vs v4, v8, v12
146 vsetvli zero, zero, e16, mf2, tu, mu
147 vfwredosum.vs v4, v8, v12
148 vsetvli zero, zero, e16, m1, tu, mu
149 vfwredosum.vs v4, v8, v12
150 vsetvli zero, zero, e16, m2, tu, mu
151 vfwredosum.vs v4, v8, v12
152 vsetvli zero, zero, e16, m4, tu, mu
153 vfwredosum.vs v4, v8, v12
154 vsetvli zero, zero, e16, m8, tu, mu
155 vfwredosum.vs v4, v8, v12
156 vsetvli zero, zero, e32, mf2, tu, mu
157 vfwredosum.vs v4, v8, v12
158 vsetvli zero, zero, e32, m1, tu, mu
159 vfwredosum.vs v4, v8, v12
160 vsetvli zero, zero, e32, m2, tu, mu
161 vfwredosum.vs v4, v8, v12
162 vsetvli zero, zero, e32, m4, tu, mu
163 vfwredosum.vs v4, v8, v12
164 vsetvli zero, zero, e32, m8, tu, mu
165 vfwredosum.vs v4, v8, v12
166 # vfwredusum.vs
167 vsetvli zero, zero, e16, mf4, tu, mu
168 vfwredusum.vs v4, v8, v12
169 vsetvli zero, zero, e16, mf2, tu, mu
170 vfwredusum.vs v4, v8, v12
171 vsetvli zero, zero, e16, m1, tu, mu
172 vfwredusum.vs v4, v8, v12
173 vsetvli zero, zero, e16, m2, tu, mu
174 vfwredusum.vs v4, v8, v12
175 vsetvli zero, zero, e16, m4, tu, mu
176 vfwredusum.vs v4, v8, v12
177 vsetvli zero, zero, e16, m8, tu, mu
178 vfwredusum.vs v4, v8, v12
179 vsetvli zero, zero, e32, mf2, tu, mu
180 vfwredusum.vs v4, v8, v12
181 vsetvli zero, zero, e32, m1, tu, mu
182 vfwredusum.vs v4, v8, v12
183 vsetvli zero, zero, e32, m2, tu, mu
184 vfwredusum.vs v4, v8, v12
185 vsetvli zero, zero, e32, m4, tu, mu
186 vfwredusum.vs v4, v8, v12
187 vsetvli zero, zero, e32, m8, tu, mu
188 vfwredusum.vs v4, v8, v12
189
190 # Single Width Floating Point Min/Max Reductions
191 # SEW wont be e8
192 # LMUL wont be mf8
193 vsetvli zero, zero, e16, mf4, tu, mu
194 vfredmax.vs v4, v8, v12
195 vsetvli zero, zero, e16, mf2, tu, mu
196 vfredmax.vs v4, v8, v12
197 vsetvli zero, zero, e16, m1, tu, mu
198 vfredmax.vs v4, v8, v12
199 vsetvli zero, zero, e16, m2, tu, mu
200 vfredmax.vs v4, v8, v12
201 vsetvli zero, zero, e16, m4, tu, mu
202 vfredmax.vs v4, v8, v12
203 vsetvli zero, zero, e16, m8, tu, mu
204 vfredmax.vs v4, v8, v12
205 vsetvli zero, zero, e32, mf2, tu, mu
206 vfredmin.vs v4, v8, v12
207 vsetvli zero, zero, e32, m1, tu, mu
208 vfredmin.vs v4, v8, v12
209 vsetvli zero, zero, e32, m2, tu, mu
210 vfredmin.vs v4, v8, v12
211 vsetvli zero, zero, e32, m4, tu, mu
212 vfredmin.vs v4, v8, v12
213 vsetvli zero, zero, e32, m8, tu, mu
214 vfredmin.vs v4, v8, v12
215 vsetvli zero, zero, e64, m1, tu, mu
216 vfredmin.vs v4, v8, v12
217 vsetvli zero, zero, e64, m2, tu, mu
218 vfredmin.vs v4, v8, v12
219 vsetvli zero, zero, e64, m4, tu, mu
220 vfredmin.vs v4, v8, v12
221 vsetvli zero, zero, e64, m8, tu, mu
222 vfredmin.vs v4, v8, v12
223
224 # CHECK: Iterations: 1
225 # CHECK-NEXT: Instructions: 206
226 # CHECK-NEXT: Total Cycles: 8644
227 # CHECK-NEXT: Total uOps: 206
228
229 # CHECK: Dispatch Width: 2
230 # CHECK-NEXT: uOps Per Cycle: 0.02
231 # CHECK-NEXT: IPC: 0.02
232 # CHECK-NEXT: Block RThroughput: 8640.0
233
234 # CHECK: Instruction Info:
235 # CHECK-NEXT: [1]: #uOps
236 # CHECK-NEXT: [2]: Latency
237 # CHECK-NEXT: [3]: RThroughput
238 # CHECK-NEXT: [4]: MayLoad
239 # CHECK-NEXT: [5]: MayStore
240 # CHECK-NEXT: [6]: HasSideEffects (U)
241
242 # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
243 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
244 # CHECK-NEXT: 1 46 46.00 vredsum.vs v4, v8, v12
245 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
246 # CHECK-NEXT: 1 46 46.00 vredsum.vs v4, v8, v12
247 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
248 # CHECK-NEXT: 1 46 46.00 vredsum.vs v4, v8, v12
249 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
250 # CHECK-NEXT: 1 47 47.00 vredsum.vs v4, v8, v12
251 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
252 # CHECK-NEXT: 1 49 49.00 vredsum.vs v4, v8, v12
253 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu
254 # CHECK-NEXT: 1 53 53.00 vredsum.vs v4, v8, v12
255 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu
256 # CHECK-NEXT: 1 61 61.00 vredsum.vs v4, v8, v12
257 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
258 # CHECK-NEXT: 1 41 41.00 vredand.vs v4, v8, v12
259 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
260 # CHECK-NEXT: 1 41 41.00 vredand.vs v4, v8, v12
261 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
262 # CHECK-NEXT: 1 42 42.00 vredand.vs v4, v8, v12
263 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
264 # CHECK-NEXT: 1 44 44.00 vredand.vs v4, v8, v12
265 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
266 # CHECK-NEXT: 1 48 48.00 vredand.vs v4, v8, v12
267 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
268 # CHECK-NEXT: 1 56 56.00 vredand.vs v4, v8, v12
269 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
270 # CHECK-NEXT: 1 36 36.00 vredor.vs v4, v8, v12
271 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
272 # CHECK-NEXT: 1 37 37.00 vredor.vs v4, v8, v12
273 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
274 # CHECK-NEXT: 1 39 39.00 vredor.vs v4, v8, v12
275 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
276 # CHECK-NEXT: 1 43 43.00 vredor.vs v4, v8, v12
277 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
278 # CHECK-NEXT: 1 51 51.00 vredor.vs v4, v8, v12
279 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu
280 # CHECK-NEXT: 1 32 32.00 vredxor.vs v4, v8, v12
281 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu
282 # CHECK-NEXT: 1 34 34.00 vredxor.vs v4, v8, v12
283 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu
284 # CHECK-NEXT: 1 38 38.00 vredxor.vs v4, v8, v12
285 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
286 # CHECK-NEXT: 1 46 46.00 vredxor.vs v4, v8, v12
287 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
288 # CHECK-NEXT: 1 46 46.00 vredmaxu.vs v4, v8, v12
289 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
290 # CHECK-NEXT: 1 46 46.00 vredmaxu.vs v4, v8, v12
291 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
292 # CHECK-NEXT: 1 46 46.00 vredmaxu.vs v4, v8, v12
293 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
294 # CHECK-NEXT: 1 47 47.00 vredmaxu.vs v4, v8, v12
295 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
296 # CHECK-NEXT: 1 49 49.00 vredmaxu.vs v4, v8, v12
297 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu
298 # CHECK-NEXT: 1 53 53.00 vredmaxu.vs v4, v8, v12
299 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu
300 # CHECK-NEXT: 1 61 61.00 vredmaxu.vs v4, v8, v12
301 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
302 # CHECK-NEXT: 1 41 41.00 vredmax.vs v4, v8, v12
303 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
304 # CHECK-NEXT: 1 41 41.00 vredmax.vs v4, v8, v12
305 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
306 # CHECK-NEXT: 1 42 42.00 vredmax.vs v4, v8, v12
307 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
308 # CHECK-NEXT: 1 44 44.00 vredmax.vs v4, v8, v12
309 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
310 # CHECK-NEXT: 1 48 48.00 vredmax.vs v4, v8, v12
311 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
312 # CHECK-NEXT: 1 56 56.00 vredmax.vs v4, v8, v12
313 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
314 # CHECK-NEXT: 1 36 36.00 vredminu.vs v4, v8, v12
315 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
316 # CHECK-NEXT: 1 37 37.00 vredminu.vs v4, v8, v12
317 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
318 # CHECK-NEXT: 1 39 39.00 vredminu.vs v4, v8, v12
319 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
320 # CHECK-NEXT: 1 43 43.00 vredminu.vs v4, v8, v12
321 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
322 # CHECK-NEXT: 1 51 51.00 vredminu.vs v4, v8, v12
323 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu
324 # CHECK-NEXT: 1 32 32.00 vredmin.vs v4, v8, v12
325 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu
326 # CHECK-NEXT: 1 34 34.00 vredmin.vs v4, v8, v12
327 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu
328 # CHECK-NEXT: 1 38 38.00 vredmin.vs v4, v8, v12
329 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
330 # CHECK-NEXT: 1 46 46.00 vredmin.vs v4, v8, v12
331 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
332 # CHECK-NEXT: 1 46 46.00 vwredsumu.vs v4, v8, v12
333 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
334 # CHECK-NEXT: 1 46 46.00 vwredsumu.vs v4, v8, v12
335 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
336 # CHECK-NEXT: 1 46 46.00 vwredsumu.vs v4, v8, v12
337 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m1, tu, mu
338 # CHECK-NEXT: 1 47 47.00 vwredsumu.vs v4, v8, v12
339 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m2, tu, mu
340 # CHECK-NEXT: 1 49 49.00 vwredsumu.vs v4, v8, v12
341 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m4, tu, mu
342 # CHECK-NEXT: 1 53 53.00 vwredsumu.vs v4, v8, v12
343 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, m8, tu, mu
344 # CHECK-NEXT: 1 61 61.00 vwredsumu.vs v4, v8, v12
345 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
346 # CHECK-NEXT: 1 41 41.00 vwredsumu.vs v4, v8, v12
347 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
348 # CHECK-NEXT: 1 41 41.00 vwredsumu.vs v4, v8, v12
349 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
350 # CHECK-NEXT: 1 42 42.00 vwredsumu.vs v4, v8, v12
351 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
352 # CHECK-NEXT: 1 44 44.00 vwredsumu.vs v4, v8, v12
353 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
354 # CHECK-NEXT: 1 48 48.00 vwredsumu.vs v4, v8, v12
355 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
356 # CHECK-NEXT: 1 56 56.00 vwredsumu.vs v4, v8, v12
357 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
358 # CHECK-NEXT: 1 36 36.00 vwredsum.vs v4, v8, v12
359 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
360 # CHECK-NEXT: 1 37 37.00 vwredsum.vs v4, v8, v12
361 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
362 # CHECK-NEXT: 1 39 39.00 vwredsum.vs v4, v8, v12
363 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
364 # CHECK-NEXT: 1 43 43.00 vwredsum.vs v4, v8, v12
365 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
366 # CHECK-NEXT: 1 51 51.00 vwredsum.vs v4, v8, v12
367 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu
368 # CHECK-NEXT: 1 61 61.00 vwredsum.vs v4, v8, v12
369 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu
370 # CHECK-NEXT: 1 61 61.00 vwredsum.vs v4, v8, v12
371 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu
372 # CHECK-NEXT: 1 61 61.00 vwredsum.vs v4, v8, v12
373 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
374 # CHECK-NEXT: 1 61 61.00 vwredsum.vs v4, v8, v12
375 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
376 # CHECK-NEXT: 1 48 48.00 vfwredosum.vs v4, v8, v12
377 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
378 # CHECK-NEXT: 1 96 96.00 vfwredosum.vs v4, v8, v12
379 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
380 # CHECK-NEXT: 1 192 192.00 vfwredosum.vs v4, v8, v12
381 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
382 # CHECK-NEXT: 1 384 384.00 vfwredosum.vs v4, v8, v12
383 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
384 # CHECK-NEXT: 1 768 768.00 vfwredosum.vs v4, v8, v12
385 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
386 # CHECK-NEXT: 1 1536 1536.00 vfwredosum.vs v4, v8, v12
387 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
388 # CHECK-NEXT: 1 48 48.00 vfwredosum.vs v4, v8, v12
389 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
390 # CHECK-NEXT: 1 96 96.00 vfwredosum.vs v4, v8, v12
391 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
392 # CHECK-NEXT: 1 192 192.00 vfwredosum.vs v4, v8, v12
393 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
394 # CHECK-NEXT: 1 384 384.00 vfwredosum.vs v4, v8, v12
395 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
396 # CHECK-NEXT: 1 768 768.00 vfwredosum.vs v4, v8, v12
397 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
398 # CHECK-NEXT: 1 41 41.00 vfwredusum.vs v4, v8, v12
399 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
400 # CHECK-NEXT: 1 41 41.00 vfwredusum.vs v4, v8, v12
401 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
402 # CHECK-NEXT: 1 42 42.00 vfwredusum.vs v4, v8, v12
403 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
404 # CHECK-NEXT: 1 44 44.00 vfwredusum.vs v4, v8, v12
405 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
406 # CHECK-NEXT: 1 48 48.00 vfwredusum.vs v4, v8, v12
407 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
408 # CHECK-NEXT: 1 56 56.00 vfwredusum.vs v4, v8, v12
409 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
410 # CHECK-NEXT: 1 36 36.00 vfwredusum.vs v4, v8, v12
411 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
412 # CHECK-NEXT: 1 37 37.00 vfwredusum.vs v4, v8, v12
413 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
414 # CHECK-NEXT: 1 39 39.00 vfwredusum.vs v4, v8, v12
415 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
416 # CHECK-NEXT: 1 43 43.00 vfwredusum.vs v4, v8, v12
417 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
418 # CHECK-NEXT: 1 51 51.00 vfwredusum.vs v4, v8, v12
419 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
420 # CHECK-NEXT: 1 41 41.00 vfredmax.vs v4, v8, v12
421 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
422 # CHECK-NEXT: 1 41 41.00 vfredmax.vs v4, v8, v12
423 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m1, tu, mu
424 # CHECK-NEXT: 1 42 42.00 vfredmax.vs v4, v8, v12
425 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m2, tu, mu
426 # CHECK-NEXT: 1 44 44.00 vfredmax.vs v4, v8, v12
427 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m4, tu, mu
428 # CHECK-NEXT: 1 48 48.00 vfredmax.vs v4, v8, v12
429 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e16, m8, tu, mu
430 # CHECK-NEXT: 1 56 56.00 vfredmax.vs v4, v8, v12
431 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
432 # CHECK-NEXT: 1 36 36.00 vfredmin.vs v4, v8, v12
433 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
434 # CHECK-NEXT: 1 37 37.00 vfredmin.vs v4, v8, v12
435 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m2, tu, mu
436 # CHECK-NEXT: 1 39 39.00 vfredmin.vs v4, v8, v12
437 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m4, tu, mu
438 # CHECK-NEXT: 1 43 43.00 vfredmin.vs v4, v8, v12
439 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m8, tu, mu
440 # CHECK-NEXT: 1 51 51.00 vfredmin.vs v4, v8, v12
441 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu
442 # CHECK-NEXT: 1 32 32.00 vfredmin.vs v4, v8, v12
443 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m2, tu, mu
444 # CHECK-NEXT: 1 34 34.00 vfredmin.vs v4, v8, v12
445 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m4, tu, mu
446 # CHECK-NEXT: 1 38 38.00 vfredmin.vs v4, v8, v12
447 # CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m8, tu, mu
448 # CHECK-NEXT: 1 46 46.00 vfredmin.vs v4, v8, v12
449
450 # CHECK: Resources:
451 # CHECK-NEXT: [0] - SiFive7FDiv
452 # CHECK-NEXT: [1] - SiFive7IDiv
453 # CHECK-NEXT: [2] - SiFive7PipeA
454 # CHECK-NEXT: [3] - SiFive7PipeB
455 # CHECK-NEXT: [4] - SiFive7PipeV
456 # CHECK-NEXT: [5] - SiFive7VA
457 # CHECK-NEXT: [6] - SiFive7VL
458 # CHECK-NEXT: [7] - SiFive7VS
459
460 # CHECK: Resource pressure per iteration:
461 # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
462 # CHECK-NEXT: - - 103.00 - 8640.00 8640.00 - -
463
464 # CHECK: Resource pressure by instruction:
465 # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
466 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
467 # CHECK-NEXT: - - - - 46.00 46.00 - - vredsum.vs v4, v8, v12
468 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
469 # CHECK-NEXT: - - - - 46.00 46.00 - - vredsum.vs v4, v8, v12
470 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
471 # CHECK-NEXT: - - - - 46.00 46.00 - - vredsum.vs v4, v8, v12
472 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
473 # CHECK-NEXT: - - - - 47.00 47.00 - - vredsum.vs v4, v8, v12
474 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
475 # CHECK-NEXT: - - - - 49.00 49.00 - - vredsum.vs v4, v8, v12
476 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu
477 # CHECK-NEXT: - - - - 53.00 53.00 - - vredsum.vs v4, v8, v12
478 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu
479 # CHECK-NEXT: - - - - 61.00 61.00 - - vredsum.vs v4, v8, v12
480 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
481 # CHECK-NEXT: - - - - 41.00 41.00 - - vredand.vs v4, v8, v12
482 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
483 # CHECK-NEXT: - - - - 41.00 41.00 - - vredand.vs v4, v8, v12
484 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
485 # CHECK-NEXT: - - - - 42.00 42.00 - - vredand.vs v4, v8, v12
486 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
487 # CHECK-NEXT: - - - - 44.00 44.00 - - vredand.vs v4, v8, v12
488 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
489 # CHECK-NEXT: - - - - 48.00 48.00 - - vredand.vs v4, v8, v12
490 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
491 # CHECK-NEXT: - - - - 56.00 56.00 - - vredand.vs v4, v8, v12
492 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
493 # CHECK-NEXT: - - - - 36.00 36.00 - - vredor.vs v4, v8, v12
494 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
495 # CHECK-NEXT: - - - - 37.00 37.00 - - vredor.vs v4, v8, v12
496 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
497 # CHECK-NEXT: - - - - 39.00 39.00 - - vredor.vs v4, v8, v12
498 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
499 # CHECK-NEXT: - - - - 43.00 43.00 - - vredor.vs v4, v8, v12
500 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
501 # CHECK-NEXT: - - - - 51.00 51.00 - - vredor.vs v4, v8, v12
502 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
503 # CHECK-NEXT: - - - - 32.00 32.00 - - vredxor.vs v4, v8, v12
504 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu
505 # CHECK-NEXT: - - - - 34.00 34.00 - - vredxor.vs v4, v8, v12
506 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu
507 # CHECK-NEXT: - - - - 38.00 38.00 - - vredxor.vs v4, v8, v12
508 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
509 # CHECK-NEXT: - - - - 46.00 46.00 - - vredxor.vs v4, v8, v12
510 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
511 # CHECK-NEXT: - - - - 46.00 46.00 - - vredmaxu.vs v4, v8, v12
512 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
513 # CHECK-NEXT: - - - - 46.00 46.00 - - vredmaxu.vs v4, v8, v12
514 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
515 # CHECK-NEXT: - - - - 46.00 46.00 - - vredmaxu.vs v4, v8, v12
516 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
517 # CHECK-NEXT: - - - - 47.00 47.00 - - vredmaxu.vs v4, v8, v12
518 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
519 # CHECK-NEXT: - - - - 49.00 49.00 - - vredmaxu.vs v4, v8, v12
520 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu
521 # CHECK-NEXT: - - - - 53.00 53.00 - - vredmaxu.vs v4, v8, v12
522 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu
523 # CHECK-NEXT: - - - - 61.00 61.00 - - vredmaxu.vs v4, v8, v12
524 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
525 # CHECK-NEXT: - - - - 41.00 41.00 - - vredmax.vs v4, v8, v12
526 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
527 # CHECK-NEXT: - - - - 41.00 41.00 - - vredmax.vs v4, v8, v12
528 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
529 # CHECK-NEXT: - - - - 42.00 42.00 - - vredmax.vs v4, v8, v12
530 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
531 # CHECK-NEXT: - - - - 44.00 44.00 - - vredmax.vs v4, v8, v12
532 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
533 # CHECK-NEXT: - - - - 48.00 48.00 - - vredmax.vs v4, v8, v12
534 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
535 # CHECK-NEXT: - - - - 56.00 56.00 - - vredmax.vs v4, v8, v12
536 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
537 # CHECK-NEXT: - - - - 36.00 36.00 - - vredminu.vs v4, v8, v12
538 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
539 # CHECK-NEXT: - - - - 37.00 37.00 - - vredminu.vs v4, v8, v12
540 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
541 # CHECK-NEXT: - - - - 39.00 39.00 - - vredminu.vs v4, v8, v12
542 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
543 # CHECK-NEXT: - - - - 43.00 43.00 - - vredminu.vs v4, v8, v12
544 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
545 # CHECK-NEXT: - - - - 51.00 51.00 - - vredminu.vs v4, v8, v12
546 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
547 # CHECK-NEXT: - - - - 32.00 32.00 - - vredmin.vs v4, v8, v12
548 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu
549 # CHECK-NEXT: - - - - 34.00 34.00 - - vredmin.vs v4, v8, v12
550 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu
551 # CHECK-NEXT: - - - - 38.00 38.00 - - vredmin.vs v4, v8, v12
552 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
553 # CHECK-NEXT: - - - - 46.00 46.00 - - vredmin.vs v4, v8, v12
554 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
555 # CHECK-NEXT: - - - - 46.00 46.00 - - vwredsumu.vs v4, v8, v12
556 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
557 # CHECK-NEXT: - - - - 46.00 46.00 - - vwredsumu.vs v4, v8, v12
558 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
559 # CHECK-NEXT: - - - - 46.00 46.00 - - vwredsumu.vs v4, v8, v12
560 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
561 # CHECK-NEXT: - - - - 47.00 47.00 - - vwredsumu.vs v4, v8, v12
562 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
563 # CHECK-NEXT: - - - - 49.00 49.00 - - vwredsumu.vs v4, v8, v12
564 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu
565 # CHECK-NEXT: - - - - 53.00 53.00 - - vwredsumu.vs v4, v8, v12
566 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu
567 # CHECK-NEXT: - - - - 61.00 61.00 - - vwredsumu.vs v4, v8, v12
568 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
569 # CHECK-NEXT: - - - - 41.00 41.00 - - vwredsumu.vs v4, v8, v12
570 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
571 # CHECK-NEXT: - - - - 41.00 41.00 - - vwredsumu.vs v4, v8, v12
572 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
573 # CHECK-NEXT: - - - - 42.00 42.00 - - vwredsumu.vs v4, v8, v12
574 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
575 # CHECK-NEXT: - - - - 44.00 44.00 - - vwredsumu.vs v4, v8, v12
576 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
577 # CHECK-NEXT: - - - - 48.00 48.00 - - vwredsumu.vs v4, v8, v12
578 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
579 # CHECK-NEXT: - - - - 56.00 56.00 - - vwredsumu.vs v4, v8, v12
580 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
581 # CHECK-NEXT: - - - - 36.00 36.00 - - vwredsum.vs v4, v8, v12
582 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
583 # CHECK-NEXT: - - - - 37.00 37.00 - - vwredsum.vs v4, v8, v12
584 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
585 # CHECK-NEXT: - - - - 39.00 39.00 - - vwredsum.vs v4, v8, v12
586 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
587 # CHECK-NEXT: - - - - 43.00 43.00 - - vwredsum.vs v4, v8, v12
588 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
589 # CHECK-NEXT: - - - - 51.00 51.00 - - vwredsum.vs v4, v8, v12
590 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
591 # CHECK-NEXT: - - - - 61.00 61.00 - - vwredsum.vs v4, v8, v12
592 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu
593 # CHECK-NEXT: - - - - 61.00 61.00 - - vwredsum.vs v4, v8, v12
594 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu
595 # CHECK-NEXT: - - - - 61.00 61.00 - - vwredsum.vs v4, v8, v12
596 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
597 # CHECK-NEXT: - - - - 61.00 61.00 - - vwredsum.vs v4, v8, v12
598 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
599 # CHECK-NEXT: - - - - 48.00 48.00 - - vfwredosum.vs v4, v8, v12
600 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
601 # CHECK-NEXT: - - - - 96.00 96.00 - - vfwredosum.vs v4, v8, v12
602 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
603 # CHECK-NEXT: - - - - 192.00 192.00 - - vfwredosum.vs v4, v8, v12
604 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
605 # CHECK-NEXT: - - - - 384.00 384.00 - - vfwredosum.vs v4, v8, v12
606 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
607 # CHECK-NEXT: - - - - 768.00 768.00 - - vfwredosum.vs v4, v8, v12
608 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
609 # CHECK-NEXT: - - - - 1536.00 1536.00 - - vfwredosum.vs v4, v8, v12
610 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
611 # CHECK-NEXT: - - - - 48.00 48.00 - - vfwredosum.vs v4, v8, v12
612 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
613 # CHECK-NEXT: - - - - 96.00 96.00 - - vfwredosum.vs v4, v8, v12
614 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
615 # CHECK-NEXT: - - - - 192.00 192.00 - - vfwredosum.vs v4, v8, v12
616 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
617 # CHECK-NEXT: - - - - 384.00 384.00 - - vfwredosum.vs v4, v8, v12
618 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
619 # CHECK-NEXT: - - - - 768.00 768.00 - - vfwredosum.vs v4, v8, v12
620 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
621 # CHECK-NEXT: - - - - 41.00 41.00 - - vfwredusum.vs v4, v8, v12
622 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
623 # CHECK-NEXT: - - - - 41.00 41.00 - - vfwredusum.vs v4, v8, v12
624 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
625 # CHECK-NEXT: - - - - 42.00 42.00 - - vfwredusum.vs v4, v8, v12
626 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
627 # CHECK-NEXT: - - - - 44.00 44.00 - - vfwredusum.vs v4, v8, v12
628 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
629 # CHECK-NEXT: - - - - 48.00 48.00 - - vfwredusum.vs v4, v8, v12
630 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
631 # CHECK-NEXT: - - - - 56.00 56.00 - - vfwredusum.vs v4, v8, v12
632 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
633 # CHECK-NEXT: - - - - 36.00 36.00 - - vfwredusum.vs v4, v8, v12
634 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
635 # CHECK-NEXT: - - - - 37.00 37.00 - - vfwredusum.vs v4, v8, v12
636 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
637 # CHECK-NEXT: - - - - 39.00 39.00 - - vfwredusum.vs v4, v8, v12
638 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
639 # CHECK-NEXT: - - - - 43.00 43.00 - - vfwredusum.vs v4, v8, v12
640 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
641 # CHECK-NEXT: - - - - 51.00 51.00 - - vfwredusum.vs v4, v8, v12
642 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
643 # CHECK-NEXT: - - - - 41.00 41.00 - - vfredmax.vs v4, v8, v12
644 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
645 # CHECK-NEXT: - - - - 41.00 41.00 - - vfredmax.vs v4, v8, v12
646 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
647 # CHECK-NEXT: - - - - 42.00 42.00 - - vfredmax.vs v4, v8, v12
648 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
649 # CHECK-NEXT: - - - - 44.00 44.00 - - vfredmax.vs v4, v8, v12
650 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
651 # CHECK-NEXT: - - - - 48.00 48.00 - - vfredmax.vs v4, v8, v12
652 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
653 # CHECK-NEXT: - - - - 56.00 56.00 - - vfredmax.vs v4, v8, v12
654 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
655 # CHECK-NEXT: - - - - 36.00 36.00 - - vfredmin.vs v4, v8, v12
656 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
657 # CHECK-NEXT: - - - - 37.00 37.00 - - vfredmin.vs v4, v8, v12
658 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
659 # CHECK-NEXT: - - - - 39.00 39.00 - - vfredmin.vs v4, v8, v12
660 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
661 # CHECK-NEXT: - - - - 43.00 43.00 - - vfredmin.vs v4, v8, v12
662 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
663 # CHECK-NEXT: - - - - 51.00 51.00 - - vfredmin.vs v4, v8, v12
664 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
665 # CHECK-NEXT: - - - - 32.00 32.00 - - vfredmin.vs v4, v8, v12
666 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu
667 # CHECK-NEXT: - - - - 34.00 34.00 - - vfredmin.vs v4, v8, v12
668 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu
669 # CHECK-NEXT: - - - - 38.00 38.00 - - vfredmin.vs v4, v8, v12
670 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
671 # CHECK-NEXT: - - - - 46.00 46.00 - - vfredmin.vs v4, v8, v12
LLVM monorepo