clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_ldr.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3
   2 // REQUIRES: aarch64-registered-target
   3 // RUN: %clang_cc1 -triple aarch64 -target-feature +sme -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
   4 // RUN: %clang_cc1 -triple aarch64 -target-feature +sme -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
   5 // RUN: %clang_cc1 -triple aarch64 -target-feature +sme -S -O1 -Werror -o /dev/null %s
   6
   7 #include <arm_sme.h>
   8
   9 // CHECK-C-LABEL: @test_svldr_vnum_za(
  10 // CHECK-CXX-LABEL: @_Z18test_svldr_vnum_zajPKv(
  11 // CHECK-NEXT:  entry:
  12 // CHECK-NEXT:    tail call void @llvm.aarch64.sme.ldr(i32 [[SLICE_BASE:%.*]], ptr [[PTR:%.*]], i32 0)
  13 // CHECK-NEXT:    ret void
  14 //
  15 void test_svldr_vnum_za(uint32_t slice_base, const void *ptr) __arm_out("za") {
  16   svldr_vnum_za(slice_base, ptr, 0);
  17 }
  18
  19 // CHECK-C-LABEL: @test_svldr_vnum_za_1(
  20 // CHECK-CXX-LABEL: @_Z20test_svldr_vnum_za_1jPKv(
  21 // CHECK-NEXT:  entry:
  22 // CHECK-NEXT:    tail call void @llvm.aarch64.sme.ldr(i32 [[SLICE_BASE:%.*]], ptr [[PTR:%.*]], i32 15)
  23 // CHECK-NEXT:    ret void
  24 //
  25 void test_svldr_vnum_za_1(uint32_t slice_base, const void *ptr) __arm_out("za") {
  26   svldr_vnum_za(slice_base, ptr, 15);
  27 }
  28
  29 // CHECK-C-LABEL: @test_svldr_za(
  30 // CHECK-CXX-LABEL: @_Z13test_svldr_zajPKv(
  31 // CHECK-NEXT:  entry:
  32 // CHECK-NEXT:    tail call void @llvm.aarch64.sme.ldr(i32 [[SLICE_BASE:%.*]], ptr [[PTR:%.*]], i32 0)
  33 // CHECK-NEXT:    ret void
  34 //
  35 void test_svldr_za(uint32_t slice_base, const void *ptr) __arm_out("za") {
  36   svldr_za(slice_base, ptr);
  37 }
  38
  39 // CHECK-C-LABEL: @test_svldr_vnum_za_var(
  40 // CHECK-CXX-LABEL: @_Z22test_svldr_vnum_za_varjPKvl(
  41 // CHECK-NEXT:  entry:
  42 // CHECK-NEXT:    [[TMP0:%.*]] = trunc i64 [[VNUM:%.*]] to i32
  43 // CHECK-NEXT:    tail call void @llvm.aarch64.sme.ldr(i32 [[SLICE_BASE:%.*]], ptr [[PTR:%.*]], i32 [[TMP0:%.*]])
  44 // CHECK-NEXT:    ret void
  45 //
  46 void test_svldr_vnum_za_var(uint32_t slice_base, const void *ptr, int64_t vnum) __arm_out("za") {
  47   svldr_vnum_za(slice_base, ptr, vnum);
  48 }
  49
  50 // CHECK-C-LABEL: @test_svldr_vnum_za_2(
  51 // CHECK-CXX-LABEL: @_Z20test_svldr_vnum_za_2jPKv(
  52 // CHECK-NEXT:  entry:
  53 // CHECK-NEXT:    tail call void @llvm.aarch64.sme.ldr(i32 [[SLICE_BASE:%.*]], ptr [[PTR:%.*]], i32 16)
  54 // CHECK-NEXT:    ret void
  55 //
  56 void test_svldr_vnum_za_2(uint32_t slice_base, const void *ptr) __arm_out("za") {
  57   svldr_vnum_za(slice_base, ptr, 16);
  58 }