clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_asrd.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // REQUIRES: aarch64-registered-target
   3 // RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
   4 // RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
   5 // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
   6 // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
   7 // RUN: %clang_cc1 -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
   8 // RUN: %clang_cc1 -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
   9
  10 #include <arm_sve.h>
  11
  12 #if defined __ARM_FEATURE_SME
  13 #define MODE_ATTR __arm_streaming
  14 #else
  15 #define MODE_ATTR
  16 #endif
  17
  18 #ifdef SVE_OVERLOADED_FORMS
  19 // A simple used,unused... macro, long enough to represent any SVE builtin.
  20 #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
  21 #else
  22 #define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
  23 #endif
  24
  25 // CHECK-LABEL: @test_svasrd_n_s8_z(
  26 // CHECK-NEXT:  entry:
  27 // CHECK-NEXT:    [[TMP0:%.*]] = select <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> zeroinitializer
  28 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> [[TMP0]], i32 1)
  29 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP1]]
  30 //
  31 // CPP-CHECK-LABEL: @_Z18test_svasrd_n_s8_zu10__SVBool_tu10__SVInt8_t(
  32 // CPP-CHECK-NEXT:  entry:
  33 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = select <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> zeroinitializer
  34 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> [[TMP0]], i32 1)
  35 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP1]]
  36 //
  37 svint8_t test_svasrd_n_s8_z(svbool_t pg, svint8_t op1) MODE_ATTR
  38 {
  39   return SVE_ACLE_FUNC(svasrd,_n_s8,_z,)(pg, op1, 1);
  40 }
  41
  42 // CHECK-LABEL: @test_svasrd_n_s8_z_1(
  43 // CHECK-NEXT:  entry:
  44 // CHECK-NEXT:    [[TMP0:%.*]] = select <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> zeroinitializer
  45 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> [[TMP0]], i32 8)
  46 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP1]]
  47 //
  48 // CPP-CHECK-LABEL: @_Z20test_svasrd_n_s8_z_1u10__SVBool_tu10__SVInt8_t(
  49 // CPP-CHECK-NEXT:  entry:
  50 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = select <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> zeroinitializer
  51 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> [[TMP0]], i32 8)
  52 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP1]]
  53 //
  54 svint8_t test_svasrd_n_s8_z_1(svbool_t pg, svint8_t op1) MODE_ATTR
  55 {
  56   return SVE_ACLE_FUNC(svasrd,_n_s8,_z,)(pg, op1, 8);
  57 }
  58
  59 // CHECK-LABEL: @test_svasrd_n_s16_z(
  60 // CHECK-NEXT:  entry:
  61 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
  62 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> zeroinitializer
  63 // CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[TMP1]], i32 1)
  64 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP2]]
  65 //
  66 // CPP-CHECK-LABEL: @_Z19test_svasrd_n_s16_zu10__SVBool_tu11__SVInt16_t(
  67 // CPP-CHECK-NEXT:  entry:
  68 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
  69 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> zeroinitializer
  70 // CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[TMP1]], i32 1)
  71 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP2]]
  72 //
  73 svint16_t test_svasrd_n_s16_z(svbool_t pg, svint16_t op1) MODE_ATTR
  74 {
  75   return SVE_ACLE_FUNC(svasrd,_n_s16,_z,)(pg, op1, 1);
  76 }
  77
  78 // CHECK-LABEL: @test_svasrd_n_s16_z_1(
  79 // CHECK-NEXT:  entry:
  80 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
  81 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> zeroinitializer
  82 // CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[TMP1]], i32 16)
  83 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP2]]
  84 //
  85 // CPP-CHECK-LABEL: @_Z21test_svasrd_n_s16_z_1u10__SVBool_tu11__SVInt16_t(
  86 // CPP-CHECK-NEXT:  entry:
  87 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
  88 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> zeroinitializer
  89 // CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[TMP1]], i32 16)
  90 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP2]]
  91 //
  92 svint16_t test_svasrd_n_s16_z_1(svbool_t pg, svint16_t op1) MODE_ATTR
  93 {
  94   return SVE_ACLE_FUNC(svasrd,_n_s16,_z,)(pg, op1, 16);
  95 }
  96
  97 // CHECK-LABEL: @test_svasrd_n_s32_z(
  98 // CHECK-NEXT:  entry:
  99 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 100 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> zeroinitializer
 101 // CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[TMP1]], i32 1)
 102 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP2]]
 103 //
 104 // CPP-CHECK-LABEL: @_Z19test_svasrd_n_s32_zu10__SVBool_tu11__SVInt32_t(
 105 // CPP-CHECK-NEXT:  entry:
 106 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 107 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> zeroinitializer
 108 // CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[TMP1]], i32 1)
 109 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP2]]
 110 //
 111 svint32_t test_svasrd_n_s32_z(svbool_t pg, svint32_t op1) MODE_ATTR
 112 {
 113   return SVE_ACLE_FUNC(svasrd,_n_s32,_z,)(pg, op1, 1);
 114 }
 115
 116 // CHECK-LABEL: @test_svasrd_n_s32_z_1(
 117 // CHECK-NEXT:  entry:
 118 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 119 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> zeroinitializer
 120 // CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[TMP1]], i32 32)
 121 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP2]]
 122 //
 123 // CPP-CHECK-LABEL: @_Z21test_svasrd_n_s32_z_1u10__SVBool_tu11__SVInt32_t(
 124 // CPP-CHECK-NEXT:  entry:
 125 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 126 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> zeroinitializer
 127 // CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[TMP1]], i32 32)
 128 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP2]]
 129 //
 130 svint32_t test_svasrd_n_s32_z_1(svbool_t pg, svint32_t op1) MODE_ATTR
 131 {
 132   return SVE_ACLE_FUNC(svasrd,_n_s32,_z,)(pg, op1, 32);
 133 }
 134
 135 // CHECK-LABEL: @test_svasrd_n_s64_z(
 136 // CHECK-NEXT:  entry:
 137 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 138 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> zeroinitializer
 139 // CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[TMP1]], i32 1)
 140 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP2]]
 141 //
 142 // CPP-CHECK-LABEL: @_Z19test_svasrd_n_s64_zu10__SVBool_tu11__SVInt64_t(
 143 // CPP-CHECK-NEXT:  entry:
 144 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 145 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> zeroinitializer
 146 // CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[TMP1]], i32 1)
 147 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP2]]
 148 //
 149 svint64_t test_svasrd_n_s64_z(svbool_t pg, svint64_t op1) MODE_ATTR
 150 {
 151   return SVE_ACLE_FUNC(svasrd,_n_s64,_z,)(pg, op1, 1);
 152 }
 153
 154 // CHECK-LABEL: @test_svasrd_n_s64_z_1(
 155 // CHECK-NEXT:  entry:
 156 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 157 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> zeroinitializer
 158 // CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[TMP1]], i32 64)
 159 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP2]]
 160 //
 161 // CPP-CHECK-LABEL: @_Z21test_svasrd_n_s64_z_1u10__SVBool_tu11__SVInt64_t(
 162 // CPP-CHECK-NEXT:  entry:
 163 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 164 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> zeroinitializer
 165 // CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[TMP1]], i32 64)
 166 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP2]]
 167 //
 168 svint64_t test_svasrd_n_s64_z_1(svbool_t pg, svint64_t op1) MODE_ATTR
 169 {
 170   return SVE_ACLE_FUNC(svasrd,_n_s64,_z,)(pg, op1, 64);
 171 }
 172
 173 // CHECK-LABEL: @test_svasrd_n_s8_m(
 174 // CHECK-NEXT:  entry:
 175 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i32 1)
 176 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 177 //
 178 // CPP-CHECK-LABEL: @_Z18test_svasrd_n_s8_mu10__SVBool_tu10__SVInt8_t(
 179 // CPP-CHECK-NEXT:  entry:
 180 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i32 1)
 181 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 182 //
 183 svint8_t test_svasrd_n_s8_m(svbool_t pg, svint8_t op1) MODE_ATTR
 184 {
 185   return SVE_ACLE_FUNC(svasrd,_n_s8,_m,)(pg, op1, 1);
 186 }
 187
 188 // CHECK-LABEL: @test_svasrd_n_s16_m(
 189 // CHECK-NEXT:  entry:
 190 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
 191 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], i32 1)
 192 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 193 //
 194 // CPP-CHECK-LABEL: @_Z19test_svasrd_n_s16_mu10__SVBool_tu11__SVInt16_t(
 195 // CPP-CHECK-NEXT:  entry:
 196 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
 197 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], i32 1)
 198 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 199 //
 200 svint16_t test_svasrd_n_s16_m(svbool_t pg, svint16_t op1) MODE_ATTR
 201 {
 202   return SVE_ACLE_FUNC(svasrd,_n_s16,_m,)(pg, op1, 1);
 203 }
 204
 205 // CHECK-LABEL: @test_svasrd_n_s32_m(
 206 // CHECK-NEXT:  entry:
 207 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 208 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], i32 1)
 209 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 210 //
 211 // CPP-CHECK-LABEL: @_Z19test_svasrd_n_s32_mu10__SVBool_tu11__SVInt32_t(
 212 // CPP-CHECK-NEXT:  entry:
 213 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 214 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], i32 1)
 215 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 216 //
 217 svint32_t test_svasrd_n_s32_m(svbool_t pg, svint32_t op1) MODE_ATTR
 218 {
 219   return SVE_ACLE_FUNC(svasrd,_n_s32,_m,)(pg, op1, 1);
 220 }
 221
 222 // CHECK-LABEL: @test_svasrd_n_s64_m(
 223 // CHECK-NEXT:  entry:
 224 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 225 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], i32 1)
 226 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 227 //
 228 // CPP-CHECK-LABEL: @_Z19test_svasrd_n_s64_mu10__SVBool_tu11__SVInt64_t(
 229 // CPP-CHECK-NEXT:  entry:
 230 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 231 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], i32 1)
 232 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 233 //
 234 svint64_t test_svasrd_n_s64_m(svbool_t pg, svint64_t op1) MODE_ATTR
 235 {
 236   return SVE_ACLE_FUNC(svasrd,_n_s64,_m,)(pg, op1, 1);
 237 }
 238
 239 // CHECK-LABEL: @test_svasrd_n_s8_x(
 240 // CHECK-NEXT:  entry:
 241 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i32 8)
 242 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 243 //
 244 // CPP-CHECK-LABEL: @_Z18test_svasrd_n_s8_xu10__SVBool_tu10__SVInt8_t(
 245 // CPP-CHECK-NEXT:  entry:
 246 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.asrd.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i32 8)
 247 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 248 //
 249 svint8_t test_svasrd_n_s8_x(svbool_t pg, svint8_t op1) MODE_ATTR
 250 {
 251   return SVE_ACLE_FUNC(svasrd,_n_s8,_x,)(pg, op1, 8);
 252 }
 253
 254 // CHECK-LABEL: @test_svasrd_n_s16_x(
 255 // CHECK-NEXT:  entry:
 256 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
 257 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], i32 16)
 258 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 259 //
 260 // CPP-CHECK-LABEL: @_Z19test_svasrd_n_s16_xu10__SVBool_tu11__SVInt16_t(
 261 // CPP-CHECK-NEXT:  entry:
 262 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
 263 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.asrd.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], i32 16)
 264 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 265 //
 266 svint16_t test_svasrd_n_s16_x(svbool_t pg, svint16_t op1) MODE_ATTR
 267 {
 268   return SVE_ACLE_FUNC(svasrd,_n_s16,_x,)(pg, op1, 16);
 269 }
 270
 271 // CHECK-LABEL: @test_svasrd_n_s32_x(
 272 // CHECK-NEXT:  entry:
 273 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 274 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], i32 32)
 275 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 276 //
 277 // CPP-CHECK-LABEL: @_Z19test_svasrd_n_s32_xu10__SVBool_tu11__SVInt32_t(
 278 // CPP-CHECK-NEXT:  entry:
 279 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 280 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.asrd.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], i32 32)
 281 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 282 //
 283 svint32_t test_svasrd_n_s32_x(svbool_t pg, svint32_t op1) MODE_ATTR
 284 {
 285   return SVE_ACLE_FUNC(svasrd,_n_s32,_x,)(pg, op1, 32);
 286 }
 287
 288 // CHECK-LABEL: @test_svasrd_n_s64_x(
 289 // CHECK-NEXT:  entry:
 290 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 291 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], i32 64)
 292 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 293 //
 294 // CPP-CHECK-LABEL: @_Z19test_svasrd_n_s64_xu10__SVBool_tu11__SVInt64_t(
 295 // CPP-CHECK-NEXT:  entry:
 296 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 297 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.asrd.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], i32 64)
 298 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 299 //
 300 svint64_t test_svasrd_n_s64_x(svbool_t pg, svint64_t op1) MODE_ATTR
 301 {
 302   return SVE_ACLE_FUNC(svasrd,_n_s64,_x,)(pg, op1, 64);
 303 }