clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_cntw.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // REQUIRES: aarch64-registered-target
   3 // RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s
   4 // RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
   5 // RUN: %clang_cc1 -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
   6 // RUN: %clang_cc1 -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
   7
   8 #include <arm_sve.h>
   9
  10 #if defined __ARM_FEATURE_SME
  11 #define MODE_ATTR __arm_streaming
  12 #else
  13 #define MODE_ATTR
  14 #endif
  15
  16 // CHECK-LABEL: @test_svcntw(
  17 // CHECK-NEXT:  entry:
  18 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.vscale.i64()
  19 // CHECK-NEXT:    [[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 2
  20 // CHECK-NEXT:    ret i64 [[TMP1]]
  21 //
  22 // CPP-CHECK-LABEL: @_Z11test_svcntwv(
  23 // CPP-CHECK-NEXT:  entry:
  24 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.vscale.i64()
  25 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 2
  26 // CPP-CHECK-NEXT:    ret i64 [[TMP1]]
  27 //
  28 uint64_t test_svcntw(void) MODE_ATTR
  29 {
  30   return svcntw();
  31 }
  32
  33 // CHECK-LABEL: @test_svcntw_pat(
  34 // CHECK-NEXT:  entry:
  35 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 0)
  36 // CHECK-NEXT:    ret i64 [[TMP0]]
  37 //
  38 // CPP-CHECK-LABEL: @_Z15test_svcntw_patv(
  39 // CPP-CHECK-NEXT:  entry:
  40 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 0)
  41 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
  42 //
  43 uint64_t test_svcntw_pat(void) MODE_ATTR
  44 {
  45   return svcntw_pat(SV_POW2);
  46 }
  47
  48 // CHECK-LABEL: @test_svcntw_pat_1(
  49 // CHECK-NEXT:  entry:
  50 // CHECK-NEXT:    ret i64 1
  51 //
  52 // CPP-CHECK-LABEL: @_Z17test_svcntw_pat_1v(
  53 // CPP-CHECK-NEXT:  entry:
  54 // CPP-CHECK-NEXT:    ret i64 1
  55 //
  56 uint64_t test_svcntw_pat_1(void) MODE_ATTR
  57 {
  58   return svcntw_pat(SV_VL1);
  59 }
  60
  61 // CHECK-LABEL: @test_svcntw_pat_2(
  62 // CHECK-NEXT:  entry:
  63 // CHECK-NEXT:    ret i64 2
  64 //
  65 // CPP-CHECK-LABEL: @_Z17test_svcntw_pat_2v(
  66 // CPP-CHECK-NEXT:  entry:
  67 // CPP-CHECK-NEXT:    ret i64 2
  68 //
  69 uint64_t test_svcntw_pat_2(void) MODE_ATTR
  70 {
  71   return svcntw_pat(SV_VL2);
  72 }
  73
  74 // CHECK-LABEL: @test_svcntw_pat_3(
  75 // CHECK-NEXT:  entry:
  76 // CHECK-NEXT:    ret i64 3
  77 //
  78 // CPP-CHECK-LABEL: @_Z17test_svcntw_pat_3v(
  79 // CPP-CHECK-NEXT:  entry:
  80 // CPP-CHECK-NEXT:    ret i64 3
  81 //
  82 uint64_t test_svcntw_pat_3(void) MODE_ATTR
  83 {
  84   return svcntw_pat(SV_VL3);
  85 }
  86
  87 // CHECK-LABEL: @test_svcntw_pat_4(
  88 // CHECK-NEXT:  entry:
  89 // CHECK-NEXT:    ret i64 4
  90 //
  91 // CPP-CHECK-LABEL: @_Z17test_svcntw_pat_4v(
  92 // CPP-CHECK-NEXT:  entry:
  93 // CPP-CHECK-NEXT:    ret i64 4
  94 //
  95 uint64_t test_svcntw_pat_4(void) MODE_ATTR
  96 {
  97   return svcntw_pat(SV_VL4);
  98 }
  99
 100 // CHECK-LABEL: @test_svcntw_pat_5(
 101 // CHECK-NEXT:  entry:
 102 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 5)
 103 // CHECK-NEXT:    ret i64 [[TMP0]]
 104 //
 105 // CPP-CHECK-LABEL: @_Z17test_svcntw_pat_5v(
 106 // CPP-CHECK-NEXT:  entry:
 107 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 5)
 108 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 109 //
 110 uint64_t test_svcntw_pat_5(void) MODE_ATTR
 111 {
 112   return svcntw_pat(SV_VL5);
 113 }
 114
 115 // CHECK-LABEL: @test_svcntw_pat_6(
 116 // CHECK-NEXT:  entry:
 117 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 6)
 118 // CHECK-NEXT:    ret i64 [[TMP0]]
 119 //
 120 // CPP-CHECK-LABEL: @_Z17test_svcntw_pat_6v(
 121 // CPP-CHECK-NEXT:  entry:
 122 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 6)
 123 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 124 //
 125 uint64_t test_svcntw_pat_6(void) MODE_ATTR
 126 {
 127   return svcntw_pat(SV_VL6);
 128 }
 129
 130 // CHECK-LABEL: @test_svcntw_pat_7(
 131 // CHECK-NEXT:  entry:
 132 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 7)
 133 // CHECK-NEXT:    ret i64 [[TMP0]]
 134 //
 135 // CPP-CHECK-LABEL: @_Z17test_svcntw_pat_7v(
 136 // CPP-CHECK-NEXT:  entry:
 137 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 7)
 138 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 139 //
 140 uint64_t test_svcntw_pat_7(void) MODE_ATTR
 141 {
 142   return svcntw_pat(SV_VL7);
 143 }
 144
 145 // CHECK-LABEL: @test_svcntw_pat_8(
 146 // CHECK-NEXT:  entry:
 147 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 8)
 148 // CHECK-NEXT:    ret i64 [[TMP0]]
 149 //
 150 // CPP-CHECK-LABEL: @_Z17test_svcntw_pat_8v(
 151 // CPP-CHECK-NEXT:  entry:
 152 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 8)
 153 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 154 //
 155 uint64_t test_svcntw_pat_8(void) MODE_ATTR
 156 {
 157   return svcntw_pat(SV_VL8);
 158 }
 159
 160 // CHECK-LABEL: @test_svcntw_pat_9(
 161 // CHECK-NEXT:  entry:
 162 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 9)
 163 // CHECK-NEXT:    ret i64 [[TMP0]]
 164 //
 165 // CPP-CHECK-LABEL: @_Z17test_svcntw_pat_9v(
 166 // CPP-CHECK-NEXT:  entry:
 167 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 9)
 168 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 169 //
 170 uint64_t test_svcntw_pat_9(void) MODE_ATTR
 171 {
 172   return svcntw_pat(SV_VL16);
 173 }
 174
 175 // CHECK-LABEL: @test_svcntw_pat_10(
 176 // CHECK-NEXT:  entry:
 177 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 10)
 178 // CHECK-NEXT:    ret i64 [[TMP0]]
 179 //
 180 // CPP-CHECK-LABEL: @_Z18test_svcntw_pat_10v(
 181 // CPP-CHECK-NEXT:  entry:
 182 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 10)
 183 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 184 //
 185 uint64_t test_svcntw_pat_10(void) MODE_ATTR
 186 {
 187   return svcntw_pat(SV_VL32);
 188 }
 189
 190 // CHECK-LABEL: @test_svcntw_pat_11(
 191 // CHECK-NEXT:  entry:
 192 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 11)
 193 // CHECK-NEXT:    ret i64 [[TMP0]]
 194 //
 195 // CPP-CHECK-LABEL: @_Z18test_svcntw_pat_11v(
 196 // CPP-CHECK-NEXT:  entry:
 197 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 11)
 198 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 199 //
 200 uint64_t test_svcntw_pat_11(void) MODE_ATTR
 201 {
 202   return svcntw_pat(SV_VL64);
 203 }
 204
 205 // CHECK-LABEL: @test_svcntw_pat_12(
 206 // CHECK-NEXT:  entry:
 207 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 12)
 208 // CHECK-NEXT:    ret i64 [[TMP0]]
 209 //
 210 // CPP-CHECK-LABEL: @_Z18test_svcntw_pat_12v(
 211 // CPP-CHECK-NEXT:  entry:
 212 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 12)
 213 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 214 //
 215 uint64_t test_svcntw_pat_12(void) MODE_ATTR
 216 {
 217   return svcntw_pat(SV_VL128);
 218 }
 219
 220 // CHECK-LABEL: @test_svcntw_pat_13(
 221 // CHECK-NEXT:  entry:
 222 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 13)
 223 // CHECK-NEXT:    ret i64 [[TMP0]]
 224 //
 225 // CPP-CHECK-LABEL: @_Z18test_svcntw_pat_13v(
 226 // CPP-CHECK-NEXT:  entry:
 227 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 13)
 228 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 229 //
 230 uint64_t test_svcntw_pat_13(void) MODE_ATTR
 231 {
 232   return svcntw_pat(SV_VL256);
 233 }
 234
 235 // CHECK-LABEL: @test_svcntw_pat_14(
 236 // CHECK-NEXT:  entry:
 237 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 29)
 238 // CHECK-NEXT:    ret i64 [[TMP0]]
 239 //
 240 // CPP-CHECK-LABEL: @_Z18test_svcntw_pat_14v(
 241 // CPP-CHECK-NEXT:  entry:
 242 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 29)
 243 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 244 //
 245 uint64_t test_svcntw_pat_14(void) MODE_ATTR
 246 {
 247   return svcntw_pat(SV_MUL4);
 248 }
 249
 250 // CHECK-LABEL: @test_svcntw_pat_15(
 251 // CHECK-NEXT:  entry:
 252 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 30)
 253 // CHECK-NEXT:    ret i64 [[TMP0]]
 254 //
 255 // CPP-CHECK-LABEL: @_Z18test_svcntw_pat_15v(
 256 // CPP-CHECK-NEXT:  entry:
 257 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 30)
 258 // CPP-CHECK-NEXT:    ret i64 [[TMP0]]
 259 //
 260 uint64_t test_svcntw_pat_15(void) MODE_ATTR
 261 {
 262   return svcntw_pat(SV_MUL3);
 263 }
 264
 265 // CHECK-LABEL: @test_svcntw_pat_16(
 266 // CHECK-NEXT:  entry:
 267 // CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.vscale.i64()
 268 // CHECK-NEXT:    [[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 2
 269 // CHECK-NEXT:    ret i64 [[TMP1]]
 270 //
 271 // CPP-CHECK-LABEL: @_Z18test_svcntw_pat_16v(
 272 // CPP-CHECK-NEXT:  entry:
 273 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.vscale.i64()
 274 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 2
 275 // CPP-CHECK-NEXT:    ret i64 [[TMP1]]
 276 //
 277 uint64_t test_svcntw_pat_16(void) MODE_ATTR
 278 {
 279   return svcntw_pat(SV_ALL);
 280 }