clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_ext.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // REQUIRES: aarch64-registered-target
   3 // RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
   4 // RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
   5 // RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
   6 // RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
   7 // RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
   8 // RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
   9
  10 #include <arm_sve.h>
  11
  12 #if defined __ARM_FEATURE_SME
  13 #define MODE_ATTR __arm_streaming
  14 #else
  15 #define MODE_ATTR
  16 #endif
  17
  18 #ifdef SVE_OVERLOADED_FORMS
  19 // A simple used,unused... macro, long enough to represent any SVE builtin.
  20 #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
  21 #else
  22 #define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
  23 #endif
  24
  25 // CHECK-LABEL: @test_svext_s8(
  26 // CHECK-NEXT:  entry:
  27 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.ext.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i32 0)
  28 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  29 //
  30 // CPP-CHECK-LABEL: @_Z13test_svext_s8u10__SVInt8_tS_(
  31 // CPP-CHECK-NEXT:  entry:
  32 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.ext.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i32 0)
  33 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  34 //
  35 svint8_t test_svext_s8(svint8_t op1, svint8_t op2) MODE_ATTR
  36 {
  37   return SVE_ACLE_FUNC(svext,_s8,,)(op1, op2, 0);
  38 }
  39
  40 // CHECK-LABEL: @test_svext_s8_1(
  41 // CHECK-NEXT:  entry:
  42 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.ext.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i32 255)
  43 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  44 //
  45 // CPP-CHECK-LABEL: @_Z15test_svext_s8_1u10__SVInt8_tS_(
  46 // CPP-CHECK-NEXT:  entry:
  47 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.ext.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i32 255)
  48 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  49 //
  50 svint8_t test_svext_s8_1(svint8_t op1, svint8_t op2) MODE_ATTR
  51 {
  52   return SVE_ACLE_FUNC(svext,_s8,,)(op1, op2, 255);
  53 }
  54
  55 // CHECK-LABEL: @test_svext_s16(
  56 // CHECK-NEXT:  entry:
  57 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.ext.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i32 0)
  58 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  59 //
  60 // CPP-CHECK-LABEL: @_Z14test_svext_s16u11__SVInt16_tS_(
  61 // CPP-CHECK-NEXT:  entry:
  62 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.ext.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i32 0)
  63 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  64 //
  65 svint16_t test_svext_s16(svint16_t op1, svint16_t op2) MODE_ATTR
  66 {
  67   return SVE_ACLE_FUNC(svext,_s16,,)(op1, op2, 0);
  68 }
  69
  70 // CHECK-LABEL: @test_svext_s16_1(
  71 // CHECK-NEXT:  entry:
  72 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.ext.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i32 127)
  73 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  74 //
  75 // CPP-CHECK-LABEL: @_Z16test_svext_s16_1u11__SVInt16_tS_(
  76 // CPP-CHECK-NEXT:  entry:
  77 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.ext.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i32 127)
  78 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  79 //
  80 svint16_t test_svext_s16_1(svint16_t op1, svint16_t op2) MODE_ATTR
  81 {
  82   return SVE_ACLE_FUNC(svext,_s16,,)(op1, op2, 127);
  83 }
  84
  85 // CHECK-LABEL: @test_svext_s32(
  86 // CHECK-NEXT:  entry:
  87 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.ext.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i32 0)
  88 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  89 //
  90 // CPP-CHECK-LABEL: @_Z14test_svext_s32u11__SVInt32_tS_(
  91 // CPP-CHECK-NEXT:  entry:
  92 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.ext.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i32 0)
  93 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  94 //
  95 svint32_t test_svext_s32(svint32_t op1, svint32_t op2) MODE_ATTR
  96 {
  97   return SVE_ACLE_FUNC(svext,_s32,,)(op1, op2, 0);
  98 }
  99
 100 // CHECK-LABEL: @test_svext_s32_1(
 101 // CHECK-NEXT:  entry:
 102 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.ext.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i32 63)
 103 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 104 //
 105 // CPP-CHECK-LABEL: @_Z16test_svext_s32_1u11__SVInt32_tS_(
 106 // CPP-CHECK-NEXT:  entry:
 107 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.ext.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i32 63)
 108 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 109 //
 110 svint32_t test_svext_s32_1(svint32_t op1, svint32_t op2) MODE_ATTR
 111 {
 112   return SVE_ACLE_FUNC(svext,_s32,,)(op1, op2, 63);
 113 }
 114
 115 // CHECK-LABEL: @test_svext_s64(
 116 // CHECK-NEXT:  entry:
 117 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.ext.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i32 0)
 118 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 119 //
 120 // CPP-CHECK-LABEL: @_Z14test_svext_s64u11__SVInt64_tS_(
 121 // CPP-CHECK-NEXT:  entry:
 122 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.ext.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i32 0)
 123 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 124 //
 125 svint64_t test_svext_s64(svint64_t op1, svint64_t op2) MODE_ATTR
 126 {
 127   return SVE_ACLE_FUNC(svext,_s64,,)(op1, op2, 0);
 128 }
 129
 130 // CHECK-LABEL: @test_svext_s64_1(
 131 // CHECK-NEXT:  entry:
 132 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.ext.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i32 31)
 133 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 134 //
 135 // CPP-CHECK-LABEL: @_Z16test_svext_s64_1u11__SVInt64_tS_(
 136 // CPP-CHECK-NEXT:  entry:
 137 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.ext.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i32 31)
 138 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 139 //
 140 svint64_t test_svext_s64_1(svint64_t op1, svint64_t op2) MODE_ATTR
 141 {
 142   return SVE_ACLE_FUNC(svext,_s64,,)(op1, op2, 31);
 143 }
 144
 145 // CHECK-LABEL: @test_svext_u8(
 146 // CHECK-NEXT:  entry:
 147 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.ext.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i32 255)
 148 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 149 //
 150 // CPP-CHECK-LABEL: @_Z13test_svext_u8u11__SVUint8_tS_(
 151 // CPP-CHECK-NEXT:  entry:
 152 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.ext.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i32 255)
 153 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 154 //
 155 svuint8_t test_svext_u8(svuint8_t op1, svuint8_t op2) MODE_ATTR
 156 {
 157   return SVE_ACLE_FUNC(svext,_u8,,)(op1, op2, 255);
 158 }
 159
 160 // CHECK-LABEL: @test_svext_u16(
 161 // CHECK-NEXT:  entry:
 162 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.ext.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i32 127)
 163 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 164 //
 165 // CPP-CHECK-LABEL: @_Z14test_svext_u16u12__SVUint16_tS_(
 166 // CPP-CHECK-NEXT:  entry:
 167 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.ext.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i32 127)
 168 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 169 //
 170 svuint16_t test_svext_u16(svuint16_t op1, svuint16_t op2) MODE_ATTR
 171 {
 172   return SVE_ACLE_FUNC(svext,_u16,,)(op1, op2, 127);
 173 }
 174
 175 // CHECK-LABEL: @test_svext_u32(
 176 // CHECK-NEXT:  entry:
 177 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.ext.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i32 63)
 178 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 179 //
 180 // CPP-CHECK-LABEL: @_Z14test_svext_u32u12__SVUint32_tS_(
 181 // CPP-CHECK-NEXT:  entry:
 182 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.ext.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i32 63)
 183 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 184 //
 185 svuint32_t test_svext_u32(svuint32_t op1, svuint32_t op2) MODE_ATTR
 186 {
 187   return SVE_ACLE_FUNC(svext,_u32,,)(op1, op2, 63);
 188 }
 189
 190 // CHECK-LABEL: @test_svext_u64(
 191 // CHECK-NEXT:  entry:
 192 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.ext.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i32 31)
 193 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 194 //
 195 // CPP-CHECK-LABEL: @_Z14test_svext_u64u12__SVUint64_tS_(
 196 // CPP-CHECK-NEXT:  entry:
 197 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.ext.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]], i32 31)
 198 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 199 //
 200 svuint64_t test_svext_u64(svuint64_t op1, svuint64_t op2) MODE_ATTR
 201 {
 202   return SVE_ACLE_FUNC(svext,_u64,,)(op1, op2, 31);
 203 }
 204
 205 // CHECK-LABEL: @test_svext_f16(
 206 // CHECK-NEXT:  entry:
 207 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.ext.nxv8f16(<vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], i32 127)
 208 // CHECK-NEXT:    ret <vscale x 8 x half> [[TMP0]]
 209 //
 210 // CPP-CHECK-LABEL: @_Z14test_svext_f16u13__SVFloat16_tS_(
 211 // CPP-CHECK-NEXT:  entry:
 212 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.ext.nxv8f16(<vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], i32 127)
 213 // CPP-CHECK-NEXT:    ret <vscale x 8 x half> [[TMP0]]
 214 //
 215 svfloat16_t test_svext_f16(svfloat16_t op1, svfloat16_t op2) MODE_ATTR
 216 {
 217   return SVE_ACLE_FUNC(svext,_f16,,)(op1, op2, 127);
 218 }
 219
 220 // CHECK-LABEL: @test_svext_f32(
 221 // CHECK-NEXT:  entry:
 222 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.ext.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], i32 63)
 223 // CHECK-NEXT:    ret <vscale x 4 x float> [[TMP0]]
 224 //
 225 // CPP-CHECK-LABEL: @_Z14test_svext_f32u13__SVFloat32_tS_(
 226 // CPP-CHECK-NEXT:  entry:
 227 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.ext.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], i32 63)
 228 // CPP-CHECK-NEXT:    ret <vscale x 4 x float> [[TMP0]]
 229 //
 230 svfloat32_t test_svext_f32(svfloat32_t op1, svfloat32_t op2) MODE_ATTR
 231 {
 232   return SVE_ACLE_FUNC(svext,_f32,,)(op1, op2, 63);
 233 }
 234
 235 // CHECK-LABEL: @test_svext_f64(
 236 // CHECK-NEXT:  entry:
 237 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.ext.nxv2f64(<vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], i32 31)
 238 // CHECK-NEXT:    ret <vscale x 2 x double> [[TMP0]]
 239 //
 240 // CPP-CHECK-LABEL: @_Z14test_svext_f64u13__SVFloat64_tS_(
 241 // CPP-CHECK-NEXT:  entry:
 242 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.ext.nxv2f64(<vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], i32 31)
 243 // CPP-CHECK-NEXT:    ret <vscale x 2 x double> [[TMP0]]
 244 //
 245 svfloat64_t test_svext_f64(svfloat64_t op1, svfloat64_t op2) MODE_ATTR
 246 {
 247   return SVE_ACLE_FUNC(svext,_f64,,)(op1, op2, 31);
 248 }