clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_insr.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // REQUIRES: aarch64-registered-target
   3 // RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
   4 // RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
   5 // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
   6 // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
   7 // RUN: %clang_cc1 -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
   8 // RUN: %clang_cc1 -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
   9
  10 #include <arm_sve.h>
  11
  12 #if defined __ARM_FEATURE_SME
  13 #define MODE_ATTR __arm_streaming
  14 #else
  15 #define MODE_ATTR
  16 #endif
  17
  18 #ifdef SVE_OVERLOADED_FORMS
  19 // A simple used,unused... macro, long enough to represent any SVE builtin.
  20 #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
  21 #else
  22 #define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
  23 #endif
  24
  25 // CHECK-LABEL: @test_svinsr_n_s8(
  26 // CHECK-NEXT:  entry:
  27 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]])
  28 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  29 //
  30 // CPP-CHECK-LABEL: @_Z16test_svinsr_n_s8u10__SVInt8_ta(
  31 // CPP-CHECK-NEXT:  entry:
  32 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]])
  33 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  34 //
  35 svint8_t test_svinsr_n_s8(svint8_t op1, int8_t op2) MODE_ATTR
  36 {
  37   return SVE_ACLE_FUNC(svinsr,_n_s8,,)(op1, op2);
  38 }
  39
  40 // CHECK-LABEL: @test_svinsr_n_s16(
  41 // CHECK-NEXT:  entry:
  42 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]])
  43 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  44 //
  45 // CPP-CHECK-LABEL: @_Z17test_svinsr_n_s16u11__SVInt16_ts(
  46 // CPP-CHECK-NEXT:  entry:
  47 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]])
  48 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
  49 //
  50 svint16_t test_svinsr_n_s16(svint16_t op1, int16_t op2) MODE_ATTR
  51 {
  52   return SVE_ACLE_FUNC(svinsr,_n_s16,,)(op1, op2);
  53 }
  54
  55 // CHECK-LABEL: @test_svinsr_n_s32(
  56 // CHECK-NEXT:  entry:
  57 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.insr.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]])
  58 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  59 //
  60 // CPP-CHECK-LABEL: @_Z17test_svinsr_n_s32u11__SVInt32_ti(
  61 // CPP-CHECK-NEXT:  entry:
  62 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.insr.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]])
  63 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  64 //
  65 svint32_t test_svinsr_n_s32(svint32_t op1, int32_t op2) MODE_ATTR
  66 {
  67   return SVE_ACLE_FUNC(svinsr,_n_s32,,)(op1, op2);
  68 }
  69
  70 // CHECK-LABEL: @test_svinsr_n_s64(
  71 // CHECK-NEXT:  entry:
  72 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.insr.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], i64 [[OP2:%.*]])
  73 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
  74 //
  75 // CPP-CHECK-LABEL: @_Z17test_svinsr_n_s64u11__SVInt64_tl(
  76 // CPP-CHECK-NEXT:  entry:
  77 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.insr.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], i64 [[OP2:%.*]])
  78 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
  79 //
  80 svint64_t test_svinsr_n_s64(svint64_t op1, int64_t op2) MODE_ATTR
  81 {
  82   return SVE_ACLE_FUNC(svinsr,_n_s64,,)(op1, op2);
  83 }
  84
  85 // CHECK-LABEL: @test_svinsr_n_u8(
  86 // CHECK-NEXT:  entry:
  87 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]])
  88 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  89 //
  90 // CPP-CHECK-LABEL: @_Z16test_svinsr_n_u8u11__SVUint8_th(
  91 // CPP-CHECK-NEXT:  entry:
  92 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]])
  93 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
  94 //
  95 svuint8_t test_svinsr_n_u8(svuint8_t op1, uint8_t op2) MODE_ATTR
  96 {
  97   return SVE_ACLE_FUNC(svinsr,_n_u8,,)(op1, op2);
  98 }
  99
 100 // CHECK-LABEL: @test_svinsr_n_u16(
 101 // CHECK-NEXT:  entry:
 102 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]])
 103 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 104 //
 105 // CPP-CHECK-LABEL: @_Z17test_svinsr_n_u16u12__SVUint16_tt(
 106 // CPP-CHECK-NEXT:  entry:
 107 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]])
 108 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 109 //
 110 svuint16_t test_svinsr_n_u16(svuint16_t op1, uint16_t op2) MODE_ATTR
 111 {
 112   return SVE_ACLE_FUNC(svinsr,_n_u16,,)(op1, op2);
 113 }
 114
 115 // CHECK-LABEL: @test_svinsr_n_u32(
 116 // CHECK-NEXT:  entry:
 117 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.insr.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]])
 118 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 119 //
 120 // CPP-CHECK-LABEL: @_Z17test_svinsr_n_u32u12__SVUint32_tj(
 121 // CPP-CHECK-NEXT:  entry:
 122 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.insr.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]])
 123 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 124 //
 125 svuint32_t test_svinsr_n_u32(svuint32_t op1, uint32_t op2) MODE_ATTR
 126 {
 127   return SVE_ACLE_FUNC(svinsr,_n_u32,,)(op1, op2);
 128 }
 129
 130 // CHECK-LABEL: @test_svinsr_n_u64(
 131 // CHECK-NEXT:  entry:
 132 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.insr.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], i64 [[OP2:%.*]])
 133 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 134 //
 135 // CPP-CHECK-LABEL: @_Z17test_svinsr_n_u64u12__SVUint64_tm(
 136 // CPP-CHECK-NEXT:  entry:
 137 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.insr.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], i64 [[OP2:%.*]])
 138 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 139 //
 140 svuint64_t test_svinsr_n_u64(svuint64_t op1, uint64_t op2) MODE_ATTR
 141 {
 142   return SVE_ACLE_FUNC(svinsr,_n_u64,,)(op1, op2);
 143 }
 144
 145 // CHECK-LABEL: @test_svinsr_n_f16(
 146 // CHECK-NEXT:  entry:
 147 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.insr.nxv8f16(<vscale x 8 x half> [[OP1:%.*]], half [[OP2:%.*]])
 148 // CHECK-NEXT:    ret <vscale x 8 x half> [[TMP0]]
 149 //
 150 // CPP-CHECK-LABEL: @_Z17test_svinsr_n_f16u13__SVFloat16_tDh(
 151 // CPP-CHECK-NEXT:  entry:
 152 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.insr.nxv8f16(<vscale x 8 x half> [[OP1:%.*]], half [[OP2:%.*]])
 153 // CPP-CHECK-NEXT:    ret <vscale x 8 x half> [[TMP0]]
 154 //
 155 svfloat16_t test_svinsr_n_f16(svfloat16_t op1, float16_t op2) MODE_ATTR
 156 {
 157   return SVE_ACLE_FUNC(svinsr,_n_f16,,)(op1, op2);
 158 }
 159
 160 // CHECK-LABEL: @test_svinsr_n_f32(
 161 // CHECK-NEXT:  entry:
 162 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.insr.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], float [[OP2:%.*]])
 163 // CHECK-NEXT:    ret <vscale x 4 x float> [[TMP0]]
 164 //
 165 // CPP-CHECK-LABEL: @_Z17test_svinsr_n_f32u13__SVFloat32_tf(
 166 // CPP-CHECK-NEXT:  entry:
 167 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.insr.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], float [[OP2:%.*]])
 168 // CPP-CHECK-NEXT:    ret <vscale x 4 x float> [[TMP0]]
 169 //
 170 svfloat32_t test_svinsr_n_f32(svfloat32_t op1, float32_t op2) MODE_ATTR
 171 {
 172   return SVE_ACLE_FUNC(svinsr,_n_f32,,)(op1, op2);
 173 }
 174
 175 // CHECK-LABEL: @test_svinsr_n_f64(
 176 // CHECK-NEXT:  entry:
 177 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.insr.nxv2f64(<vscale x 2 x double> [[OP1:%.*]], double [[OP2:%.*]])
 178 // CHECK-NEXT:    ret <vscale x 2 x double> [[TMP0]]
 179 //
 180 // CPP-CHECK-LABEL: @_Z17test_svinsr_n_f64u13__SVFloat64_td(
 181 // CPP-CHECK-NEXT:  entry:
 182 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.insr.nxv2f64(<vscale x 2 x double> [[OP1:%.*]], double [[OP2:%.*]])
 183 // CPP-CHECK-NEXT:    ret <vscale x 2 x double> [[TMP0]]
 184 //
 185 svfloat64_t test_svinsr_n_f64(svfloat64_t op1, float64_t op2) MODE_ATTR
 186 {
 187   return SVE_ACLE_FUNC(svinsr,_n_f64,,)(op1, op2);
 188 }