clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_orr.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // REQUIRES: aarch64-registered-target
   3 // RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
   4 // RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
   5 // RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
   6 // RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
   7 // RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
   8 // RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
   9
  10 #include <arm_sve.h>
  11
  12 #if defined __ARM_FEATURE_SME
  13 #define MODE_ATTR __arm_streaming
  14 #else
  15 #define MODE_ATTR
  16 #endif
  17
  18 #ifdef SVE_OVERLOADED_FORMS
  19 // A simple used,unused... macro, long enough to represent any SVE builtin.
  20 #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
  21 #else
  22 #define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
  23 #endif
  24
  25 // CHECK-LABEL: @test_svorr_s8_z(
  26 // CHECK-NEXT:  entry:
  27 // CHECK-NEXT:    [[TMP0:%.*]] = select <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> zeroinitializer
  28 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> [[TMP0]], <vscale x 16 x i8> [[OP2:%.*]])
  29 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP1]]
  30 //
  31 // CPP-CHECK-LABEL: @_Z15test_svorr_s8_zu10__SVBool_tu10__SVInt8_tS0_(
  32 // CPP-CHECK-NEXT:  entry:
  33 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = select <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> zeroinitializer
  34 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> [[TMP0]], <vscale x 16 x i8> [[OP2:%.*]])
  35 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP1]]
  36 //
  37 svint8_t test_svorr_s8_z(svbool_t pg, svint8_t op1, svint8_t op2) MODE_ATTR
  38 {
  39   return SVE_ACLE_FUNC(svorr,_s8,_z,)(pg, op1, op2);
  40 }
  41
  42 // CHECK-LABEL: @test_svorr_s16_z(
  43 // CHECK-NEXT:  entry:
  44 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
  45 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> zeroinitializer
  46 // CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[TMP1]], <vscale x 8 x i16> [[OP2:%.*]])
  47 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP2]]
  48 //
  49 // CPP-CHECK-LABEL: @_Z16test_svorr_s16_zu10__SVBool_tu11__SVInt16_tS0_(
  50 // CPP-CHECK-NEXT:  entry:
  51 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
  52 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> zeroinitializer
  53 // CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[TMP1]], <vscale x 8 x i16> [[OP2:%.*]])
  54 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP2]]
  55 //
  56 svint16_t test_svorr_s16_z(svbool_t pg, svint16_t op1, svint16_t op2) MODE_ATTR
  57 {
  58   return SVE_ACLE_FUNC(svorr,_s16,_z,)(pg, op1, op2);
  59 }
  60
  61 // CHECK-LABEL: @test_svorr_s32_z(
  62 // CHECK-NEXT:  entry:
  63 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
  64 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> zeroinitializer
  65 // CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[TMP1]], <vscale x 4 x i32> [[OP2:%.*]])
  66 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP2]]
  67 //
  68 // CPP-CHECK-LABEL: @_Z16test_svorr_s32_zu10__SVBool_tu11__SVInt32_tS0_(
  69 // CPP-CHECK-NEXT:  entry:
  70 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
  71 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> zeroinitializer
  72 // CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[TMP1]], <vscale x 4 x i32> [[OP2:%.*]])
  73 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP2]]
  74 //
  75 svint32_t test_svorr_s32_z(svbool_t pg, svint32_t op1, svint32_t op2) MODE_ATTR
  76 {
  77   return SVE_ACLE_FUNC(svorr,_s32,_z,)(pg, op1, op2);
  78 }
  79
  80 // CHECK-LABEL: @test_svorr_s64_z(
  81 // CHECK-NEXT:  entry:
  82 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
  83 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> zeroinitializer
  84 // CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[TMP1]], <vscale x 2 x i64> [[OP2:%.*]])
  85 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP2]]
  86 //
  87 // CPP-CHECK-LABEL: @_Z16test_svorr_s64_zu10__SVBool_tu11__SVInt64_tS0_(
  88 // CPP-CHECK-NEXT:  entry:
  89 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
  90 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> zeroinitializer
  91 // CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[TMP1]], <vscale x 2 x i64> [[OP2:%.*]])
  92 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP2]]
  93 //
  94 svint64_t test_svorr_s64_z(svbool_t pg, svint64_t op1, svint64_t op2) MODE_ATTR
  95 {
  96   return SVE_ACLE_FUNC(svorr,_s64,_z,)(pg, op1, op2);
  97 }
  98
  99 // CHECK-LABEL: @test_svorr_u8_z(
 100 // CHECK-NEXT:  entry:
 101 // CHECK-NEXT:    [[TMP0:%.*]] = select <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> zeroinitializer
 102 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> [[TMP0]], <vscale x 16 x i8> [[OP2:%.*]])
 103 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP1]]
 104 //
 105 // CPP-CHECK-LABEL: @_Z15test_svorr_u8_zu10__SVBool_tu11__SVUint8_tS0_(
 106 // CPP-CHECK-NEXT:  entry:
 107 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = select <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> zeroinitializer
 108 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> [[TMP0]], <vscale x 16 x i8> [[OP2:%.*]])
 109 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP1]]
 110 //
 111 svuint8_t test_svorr_u8_z(svbool_t pg, svuint8_t op1, svuint8_t op2) MODE_ATTR
 112 {
 113   return SVE_ACLE_FUNC(svorr,_u8,_z,)(pg, op1, op2);
 114 }
 115
 116 // CHECK-LABEL: @test_svorr_u16_z(
 117 // CHECK-NEXT:  entry:
 118 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
 119 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> zeroinitializer
 120 // CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[TMP1]], <vscale x 8 x i16> [[OP2:%.*]])
 121 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP2]]
 122 //
 123 // CPP-CHECK-LABEL: @_Z16test_svorr_u16_zu10__SVBool_tu12__SVUint16_tS0_(
 124 // CPP-CHECK-NEXT:  entry:
 125 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
 126 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> zeroinitializer
 127 // CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[TMP1]], <vscale x 8 x i16> [[OP2:%.*]])
 128 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP2]]
 129 //
 130 svuint16_t test_svorr_u16_z(svbool_t pg, svuint16_t op1, svuint16_t op2) MODE_ATTR
 131 {
 132   return SVE_ACLE_FUNC(svorr,_u16,_z,)(pg, op1, op2);
 133 }
 134
 135 // CHECK-LABEL: @test_svorr_u32_z(
 136 // CHECK-NEXT:  entry:
 137 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 138 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> zeroinitializer
 139 // CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[TMP1]], <vscale x 4 x i32> [[OP2:%.*]])
 140 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP2]]
 141 //
 142 // CPP-CHECK-LABEL: @_Z16test_svorr_u32_zu10__SVBool_tu12__SVUint32_tS0_(
 143 // CPP-CHECK-NEXT:  entry:
 144 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 145 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> zeroinitializer
 146 // CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[TMP1]], <vscale x 4 x i32> [[OP2:%.*]])
 147 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP2]]
 148 //
 149 svuint32_t test_svorr_u32_z(svbool_t pg, svuint32_t op1, svuint32_t op2) MODE_ATTR
 150 {
 151   return SVE_ACLE_FUNC(svorr,_u32,_z,)(pg, op1, op2);
 152 }
 153
 154 // CHECK-LABEL: @test_svorr_u64_z(
 155 // CHECK-NEXT:  entry:
 156 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 157 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> zeroinitializer
 158 // CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[TMP1]], <vscale x 2 x i64> [[OP2:%.*]])
 159 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP2]]
 160 //
 161 // CPP-CHECK-LABEL: @_Z16test_svorr_u64_zu10__SVBool_tu12__SVUint64_tS0_(
 162 // CPP-CHECK-NEXT:  entry:
 163 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 164 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> zeroinitializer
 165 // CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[TMP1]], <vscale x 2 x i64> [[OP2:%.*]])
 166 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP2]]
 167 //
 168 svuint64_t test_svorr_u64_z(svbool_t pg, svuint64_t op1, svuint64_t op2) MODE_ATTR
 169 {
 170   return SVE_ACLE_FUNC(svorr,_u64,_z,)(pg, op1, op2);
 171 }
 172
 173 // CHECK-LABEL: @test_svorr_s8_m(
 174 // CHECK-NEXT:  entry:
 175 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]])
 176 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 177 //
 178 // CPP-CHECK-LABEL: @_Z15test_svorr_s8_mu10__SVBool_tu10__SVInt8_tS0_(
 179 // CPP-CHECK-NEXT:  entry:
 180 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]])
 181 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 182 //
 183 svint8_t test_svorr_s8_m(svbool_t pg, svint8_t op1, svint8_t op2) MODE_ATTR
 184 {
 185   return SVE_ACLE_FUNC(svorr,_s8,_m,)(pg, op1, op2);
 186 }
 187
 188 // CHECK-LABEL: @test_svorr_s16_m(
 189 // CHECK-NEXT:  entry:
 190 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
 191 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]])
 192 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 193 //
 194 // CPP-CHECK-LABEL: @_Z16test_svorr_s16_mu10__SVBool_tu11__SVInt16_tS0_(
 195 // CPP-CHECK-NEXT:  entry:
 196 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
 197 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]])
 198 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 199 //
 200 svint16_t test_svorr_s16_m(svbool_t pg, svint16_t op1, svint16_t op2) MODE_ATTR
 201 {
 202   return SVE_ACLE_FUNC(svorr,_s16,_m,)(pg, op1, op2);
 203 }
 204
 205 // CHECK-LABEL: @test_svorr_s32_m(
 206 // CHECK-NEXT:  entry:
 207 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 208 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]])
 209 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 210 //
 211 // CPP-CHECK-LABEL: @_Z16test_svorr_s32_mu10__SVBool_tu11__SVInt32_tS0_(
 212 // CPP-CHECK-NEXT:  entry:
 213 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 214 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]])
 215 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 216 //
 217 svint32_t test_svorr_s32_m(svbool_t pg, svint32_t op1, svint32_t op2) MODE_ATTR
 218 {
 219   return SVE_ACLE_FUNC(svorr,_s32,_m,)(pg, op1, op2);
 220 }
 221
 222 // CHECK-LABEL: @test_svorr_s64_m(
 223 // CHECK-NEXT:  entry:
 224 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 225 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]])
 226 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 227 //
 228 // CPP-CHECK-LABEL: @_Z16test_svorr_s64_mu10__SVBool_tu11__SVInt64_tS0_(
 229 // CPP-CHECK-NEXT:  entry:
 230 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 231 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]])
 232 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 233 //
 234 svint64_t test_svorr_s64_m(svbool_t pg, svint64_t op1, svint64_t op2) MODE_ATTR
 235 {
 236   return SVE_ACLE_FUNC(svorr,_s64,_m,)(pg, op1, op2);
 237 }
 238
 239 // CHECK-LABEL: @test_svorr_u8_m(
 240 // CHECK-NEXT:  entry:
 241 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]])
 242 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 243 //
 244 // CPP-CHECK-LABEL: @_Z15test_svorr_u8_mu10__SVBool_tu11__SVUint8_tS0_(
 245 // CPP-CHECK-NEXT:  entry:
 246 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]])
 247 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 248 //
 249 svuint8_t test_svorr_u8_m(svbool_t pg, svuint8_t op1, svuint8_t op2) MODE_ATTR
 250 {
 251   return SVE_ACLE_FUNC(svorr,_u8,_m,)(pg, op1, op2);
 252 }
 253
 254 // CHECK-LABEL: @test_svorr_u16_m(
 255 // CHECK-NEXT:  entry:
 256 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
 257 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]])
 258 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 259 //
 260 // CPP-CHECK-LABEL: @_Z16test_svorr_u16_mu10__SVBool_tu12__SVUint16_tS0_(
 261 // CPP-CHECK-NEXT:  entry:
 262 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
 263 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]])
 264 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 265 //
 266 svuint16_t test_svorr_u16_m(svbool_t pg, svuint16_t op1, svuint16_t op2) MODE_ATTR
 267 {
 268   return SVE_ACLE_FUNC(svorr,_u16,_m,)(pg, op1, op2);
 269 }
 270
 271 // CHECK-LABEL: @test_svorr_u32_m(
 272 // CHECK-NEXT:  entry:
 273 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 274 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]])
 275 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 276 //
 277 // CPP-CHECK-LABEL: @_Z16test_svorr_u32_mu10__SVBool_tu12__SVUint32_tS0_(
 278 // CPP-CHECK-NEXT:  entry:
 279 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 280 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]])
 281 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 282 //
 283 svuint32_t test_svorr_u32_m(svbool_t pg, svuint32_t op1, svuint32_t op2) MODE_ATTR
 284 {
 285   return SVE_ACLE_FUNC(svorr,_u32,_m,)(pg, op1, op2);
 286 }
 287
 288 // CHECK-LABEL: @test_svorr_u64_m(
 289 // CHECK-NEXT:  entry:
 290 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 291 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]])
 292 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 293 //
 294 // CPP-CHECK-LABEL: @_Z16test_svorr_u64_mu10__SVBool_tu12__SVUint64_tS0_(
 295 // CPP-CHECK-NEXT:  entry:
 296 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 297 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]])
 298 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 299 //
 300 svuint64_t test_svorr_u64_m(svbool_t pg, svuint64_t op1, svuint64_t op2) MODE_ATTR
 301 {
 302   return SVE_ACLE_FUNC(svorr,_u64,_m,)(pg, op1, op2);
 303 }
 304
 305 // CHECK-LABEL: @test_svorr_s8_x(
 306 // CHECK-NEXT:  entry:
 307 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.orr.u.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]])
 308 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 309 //
 310 // CPP-CHECK-LABEL: @_Z15test_svorr_s8_xu10__SVBool_tu10__SVInt8_tS0_(
 311 // CPP-CHECK-NEXT:  entry:
 312 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.orr.u.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]])
 313 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 314 //
 315 svint8_t test_svorr_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) MODE_ATTR
 316 {
 317   return SVE_ACLE_FUNC(svorr,_s8,_x,)(pg, op1, op2);
 318 }
 319
 320 // CHECK-LABEL: @test_svorr_s16_x(
 321 // CHECK-NEXT:  entry:
 322 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
 323 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.orr.u.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]])
 324 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 325 //
 326 // CPP-CHECK-LABEL: @_Z16test_svorr_s16_xu10__SVBool_tu11__SVInt16_tS0_(
 327 // CPP-CHECK-NEXT:  entry:
 328 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
 329 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.orr.u.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]])
 330 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 331 //
 332 svint16_t test_svorr_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) MODE_ATTR
 333 {
 334   return SVE_ACLE_FUNC(svorr,_s16,_x,)(pg, op1, op2);
 335 }
 336
 337 // CHECK-LABEL: @test_svorr_s32_x(
 338 // CHECK-NEXT:  entry:
 339 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 340 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.orr.u.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]])
 341 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 342 //
 343 // CPP-CHECK-LABEL: @_Z16test_svorr_s32_xu10__SVBool_tu11__SVInt32_tS0_(
 344 // CPP-CHECK-NEXT:  entry:
 345 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 346 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.orr.u.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]])
 347 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 348 //
 349 svint32_t test_svorr_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) MODE_ATTR
 350 {
 351   return SVE_ACLE_FUNC(svorr,_s32,_x,)(pg, op1, op2);
 352 }
 353
 354 // CHECK-LABEL: @test_svorr_s64_x(
 355 // CHECK-NEXT:  entry:
 356 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 357 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.orr.u.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]])
 358 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 359 //
 360 // CPP-CHECK-LABEL: @_Z16test_svorr_s64_xu10__SVBool_tu11__SVInt64_tS0_(
 361 // CPP-CHECK-NEXT:  entry:
 362 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 363 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.orr.u.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]])
 364 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 365 //
 366 svint64_t test_svorr_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) MODE_ATTR
 367 {
 368   return SVE_ACLE_FUNC(svorr,_s64,_x,)(pg, op1, op2);
 369 }
 370
 371 // CHECK-LABEL: @test_svorr_u8_x(
 372 // CHECK-NEXT:  entry:
 373 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.orr.u.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]])
 374 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 375 //
 376 // CPP-CHECK-LABEL: @_Z15test_svorr_u8_xu10__SVBool_tu11__SVUint8_tS0_(
 377 // CPP-CHECK-NEXT:  entry:
 378 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.orr.u.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]])
 379 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 380 //
 381 svuint8_t test_svorr_u8_x(svbool_t pg, svuint8_t op1, svuint8_t op2) MODE_ATTR
 382 {
 383   return SVE_ACLE_FUNC(svorr,_u8,_x,)(pg, op1, op2);
 384 }
 385
 386 // CHECK-LABEL: @test_svorr_u16_x(
 387 // CHECK-NEXT:  entry:
 388 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
 389 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.orr.u.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]])
 390 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 391 //
 392 // CPP-CHECK-LABEL: @_Z16test_svorr_u16_xu10__SVBool_tu12__SVUint16_tS0_(
 393 // CPP-CHECK-NEXT:  entry:
 394 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
 395 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.orr.u.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]])
 396 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 397 //
 398 svuint16_t test_svorr_u16_x(svbool_t pg, svuint16_t op1, svuint16_t op2) MODE_ATTR
 399 {
 400   return SVE_ACLE_FUNC(svorr,_u16,_x,)(pg, op1, op2);
 401 }
 402
 403 // CHECK-LABEL: @test_svorr_u32_x(
 404 // CHECK-NEXT:  entry:
 405 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 406 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.orr.u.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]])
 407 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 408 //
 409 // CPP-CHECK-LABEL: @_Z16test_svorr_u32_xu10__SVBool_tu12__SVUint32_tS0_(
 410 // CPP-CHECK-NEXT:  entry:
 411 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 412 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.orr.u.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]])
 413 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 414 //
 415 svuint32_t test_svorr_u32_x(svbool_t pg, svuint32_t op1, svuint32_t op2) MODE_ATTR
 416 {
 417   return SVE_ACLE_FUNC(svorr,_u32,_x,)(pg, op1, op2);
 418 }
 419
 420 // CHECK-LABEL: @test_svorr_u64_x(
 421 // CHECK-NEXT:  entry:
 422 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 423 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.orr.u.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]])
 424 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 425 //
 426 // CPP-CHECK-LABEL: @_Z16test_svorr_u64_xu10__SVBool_tu12__SVUint64_tS0_(
 427 // CPP-CHECK-NEXT:  entry:
 428 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 429 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.orr.u.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]])
 430 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 431 //
 432 svuint64_t test_svorr_u64_x(svbool_t pg, svuint64_t op1, svuint64_t op2) MODE_ATTR
 433 {
 434   return SVE_ACLE_FUNC(svorr,_u64,_x,)(pg, op1, op2);
 435 }
 436
 437 // CHECK-LABEL: @test_svorr_n_s8_z(
 438 // CHECK-NEXT:  entry:
 439 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[OP2:%.*]], i64 0
 440 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
 441 // CHECK-NEXT:    [[TMP0:%.*]] = select <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> zeroinitializer
 442 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> [[TMP0]], <vscale x 16 x i8> [[DOTSPLAT]])
 443 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP1]]
 444 //
 445 // CPP-CHECK-LABEL: @_Z17test_svorr_n_s8_zu10__SVBool_tu10__SVInt8_ta(
 446 // CPP-CHECK-NEXT:  entry:
 447 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[OP2:%.*]], i64 0
 448 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
 449 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = select <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> zeroinitializer
 450 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> [[TMP0]], <vscale x 16 x i8> [[DOTSPLAT]])
 451 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP1]]
 452 //
 453 svint8_t test_svorr_n_s8_z(svbool_t pg, svint8_t op1, int8_t op2) MODE_ATTR
 454 {
 455   return SVE_ACLE_FUNC(svorr,_n_s8,_z,)(pg, op1, op2);
 456 }
 457
 458 // CHECK-LABEL: @test_svorr_n_s16_z(
 459 // CHECK-NEXT:  entry:
 460 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
 461 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP2:%.*]], i64 0
 462 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
 463 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> zeroinitializer
 464 // CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[TMP1]], <vscale x 8 x i16> [[DOTSPLAT]])
 465 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP2]]
 466 //
 467 // CPP-CHECK-LABEL: @_Z18test_svorr_n_s16_zu10__SVBool_tu11__SVInt16_ts(
 468 // CPP-CHECK-NEXT:  entry:
 469 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
 470 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP2:%.*]], i64 0
 471 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
 472 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> zeroinitializer
 473 // CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[TMP1]], <vscale x 8 x i16> [[DOTSPLAT]])
 474 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP2]]
 475 //
 476 svint16_t test_svorr_n_s16_z(svbool_t pg, svint16_t op1, int16_t op2) MODE_ATTR
 477 {
 478   return SVE_ACLE_FUNC(svorr,_n_s16,_z,)(pg, op1, op2);
 479 }
 480
 481 // CHECK-LABEL: @test_svorr_n_s32_z(
 482 // CHECK-NEXT:  entry:
 483 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 484 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[OP2:%.*]], i64 0
 485 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[DOTSPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
 486 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> zeroinitializer
 487 // CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[TMP1]], <vscale x 4 x i32> [[DOTSPLAT]])
 488 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP2]]
 489 //
 490 // CPP-CHECK-LABEL: @_Z18test_svorr_n_s32_zu10__SVBool_tu11__SVInt32_ti(
 491 // CPP-CHECK-NEXT:  entry:
 492 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 493 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[OP2:%.*]], i64 0
 494 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[DOTSPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
 495 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> zeroinitializer
 496 // CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[TMP1]], <vscale x 4 x i32> [[DOTSPLAT]])
 497 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP2]]
 498 //
 499 svint32_t test_svorr_n_s32_z(svbool_t pg, svint32_t op1, int32_t op2) MODE_ATTR
 500 {
 501   return SVE_ACLE_FUNC(svorr,_n_s32,_z,)(pg, op1, op2);
 502 }
 503
 504 // CHECK-LABEL: @test_svorr_n_s64_z(
 505 // CHECK-NEXT:  entry:
 506 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 507 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[OP2:%.*]], i64 0
 508 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
 509 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> zeroinitializer
 510 // CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[TMP1]], <vscale x 2 x i64> [[DOTSPLAT]])
 511 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP2]]
 512 //
 513 // CPP-CHECK-LABEL: @_Z18test_svorr_n_s64_zu10__SVBool_tu11__SVInt64_tl(
 514 // CPP-CHECK-NEXT:  entry:
 515 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 516 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[OP2:%.*]], i64 0
 517 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
 518 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> zeroinitializer
 519 // CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[TMP1]], <vscale x 2 x i64> [[DOTSPLAT]])
 520 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP2]]
 521 //
 522 svint64_t test_svorr_n_s64_z(svbool_t pg, svint64_t op1, int64_t op2) MODE_ATTR
 523 {
 524   return SVE_ACLE_FUNC(svorr,_n_s64,_z,)(pg, op1, op2);
 525 }
 526
 527 // CHECK-LABEL: @test_svorr_n_u8_z(
 528 // CHECK-NEXT:  entry:
 529 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[OP2:%.*]], i64 0
 530 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
 531 // CHECK-NEXT:    [[TMP0:%.*]] = select <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> zeroinitializer
 532 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> [[TMP0]], <vscale x 16 x i8> [[DOTSPLAT]])
 533 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP1]]
 534 //
 535 // CPP-CHECK-LABEL: @_Z17test_svorr_n_u8_zu10__SVBool_tu11__SVUint8_th(
 536 // CPP-CHECK-NEXT:  entry:
 537 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[OP2:%.*]], i64 0
 538 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
 539 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = select <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> zeroinitializer
 540 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1> [[PG]], <vscale x 16 x i8> [[TMP0]], <vscale x 16 x i8> [[DOTSPLAT]])
 541 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP1]]
 542 //
 543 svuint8_t test_svorr_n_u8_z(svbool_t pg, svuint8_t op1, uint8_t op2) MODE_ATTR
 544 {
 545   return SVE_ACLE_FUNC(svorr,_n_u8,_z,)(pg, op1, op2);
 546 }
 547
 548 // CHECK-LABEL: @test_svorr_n_u16_z(
 549 // CHECK-NEXT:  entry:
 550 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
 551 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP2:%.*]], i64 0
 552 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
 553 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> zeroinitializer
 554 // CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[TMP1]], <vscale x 8 x i16> [[DOTSPLAT]])
 555 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP2]]
 556 //
 557 // CPP-CHECK-LABEL: @_Z18test_svorr_n_u16_zu10__SVBool_tu12__SVUint16_tt(
 558 // CPP-CHECK-NEXT:  entry:
 559 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
 560 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP2:%.*]], i64 0
 561 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
 562 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> zeroinitializer
 563 // CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[TMP1]], <vscale x 8 x i16> [[DOTSPLAT]])
 564 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP2]]
 565 //
 566 svuint16_t test_svorr_n_u16_z(svbool_t pg, svuint16_t op1, uint16_t op2) MODE_ATTR
 567 {
 568   return SVE_ACLE_FUNC(svorr,_n_u16,_z,)(pg, op1, op2);
 569 }
 570
 571 // CHECK-LABEL: @test_svorr_n_u32_z(
 572 // CHECK-NEXT:  entry:
 573 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 574 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[OP2:%.*]], i64 0
 575 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[DOTSPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
 576 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> zeroinitializer
 577 // CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[TMP1]], <vscale x 4 x i32> [[DOTSPLAT]])
 578 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP2]]
 579 //
 580 // CPP-CHECK-LABEL: @_Z18test_svorr_n_u32_zu10__SVBool_tu12__SVUint32_tj(
 581 // CPP-CHECK-NEXT:  entry:
 582 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 583 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[OP2:%.*]], i64 0
 584 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[DOTSPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
 585 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> zeroinitializer
 586 // CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[TMP1]], <vscale x 4 x i32> [[DOTSPLAT]])
 587 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP2]]
 588 //
 589 svuint32_t test_svorr_n_u32_z(svbool_t pg, svuint32_t op1, uint32_t op2) MODE_ATTR
 590 {
 591   return SVE_ACLE_FUNC(svorr,_n_u32,_z,)(pg, op1, op2);
 592 }
 593
 594 // CHECK-LABEL: @test_svorr_n_u64_z(
 595 // CHECK-NEXT:  entry:
 596 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 597 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[OP2:%.*]], i64 0
 598 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
 599 // CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> zeroinitializer
 600 // CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[TMP1]], <vscale x 2 x i64> [[DOTSPLAT]])
 601 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP2]]
 602 //
 603 // CPP-CHECK-LABEL: @_Z18test_svorr_n_u64_zu10__SVBool_tu12__SVUint64_tm(
 604 // CPP-CHECK-NEXT:  entry:
 605 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 606 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[OP2:%.*]], i64 0
 607 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
 608 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> zeroinitializer
 609 // CPP-CHECK-NEXT:    [[TMP2:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[TMP1]], <vscale x 2 x i64> [[DOTSPLAT]])
 610 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP2]]
 611 //
 612 svuint64_t test_svorr_n_u64_z(svbool_t pg, svuint64_t op1, uint64_t op2) MODE_ATTR
 613 {
 614   return SVE_ACLE_FUNC(svorr,_n_u64,_z,)(pg, op1, op2);
 615 }
 616
 617 // CHECK-LABEL: @test_svorr_n_s8_m(
 618 // CHECK-NEXT:  entry:
 619 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[OP2:%.*]], i64 0
 620 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
 621 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[DOTSPLAT]])
 622 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 623 //
 624 // CPP-CHECK-LABEL: @_Z17test_svorr_n_s8_mu10__SVBool_tu10__SVInt8_ta(
 625 // CPP-CHECK-NEXT:  entry:
 626 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[OP2:%.*]], i64 0
 627 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
 628 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[DOTSPLAT]])
 629 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 630 //
 631 svint8_t test_svorr_n_s8_m(svbool_t pg, svint8_t op1, int8_t op2) MODE_ATTR
 632 {
 633   return SVE_ACLE_FUNC(svorr,_n_s8,_m,)(pg, op1, op2);
 634 }
 635
 636 // CHECK-LABEL: @test_svorr_n_s16_m(
 637 // CHECK-NEXT:  entry:
 638 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
 639 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP2:%.*]], i64 0
 640 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
 641 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[DOTSPLAT]])
 642 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 643 //
 644 // CPP-CHECK-LABEL: @_Z18test_svorr_n_s16_mu10__SVBool_tu11__SVInt16_ts(
 645 // CPP-CHECK-NEXT:  entry:
 646 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
 647 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP2:%.*]], i64 0
 648 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
 649 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[DOTSPLAT]])
 650 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 651 //
 652 svint16_t test_svorr_n_s16_m(svbool_t pg, svint16_t op1, int16_t op2) MODE_ATTR
 653 {
 654   return SVE_ACLE_FUNC(svorr,_n_s16,_m,)(pg, op1, op2);
 655 }
 656
 657 // CHECK-LABEL: @test_svorr_n_s32_m(
 658 // CHECK-NEXT:  entry:
 659 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 660 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[OP2:%.*]], i64 0
 661 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[DOTSPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
 662 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[DOTSPLAT]])
 663 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 664 //
 665 // CPP-CHECK-LABEL: @_Z18test_svorr_n_s32_mu10__SVBool_tu11__SVInt32_ti(
 666 // CPP-CHECK-NEXT:  entry:
 667 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 668 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[OP2:%.*]], i64 0
 669 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[DOTSPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
 670 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[DOTSPLAT]])
 671 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 672 //
 673 svint32_t test_svorr_n_s32_m(svbool_t pg, svint32_t op1, int32_t op2) MODE_ATTR
 674 {
 675   return SVE_ACLE_FUNC(svorr,_n_s32,_m,)(pg, op1, op2);
 676 }
 677
 678 // CHECK-LABEL: @test_svorr_n_s64_m(
 679 // CHECK-NEXT:  entry:
 680 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 681 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[OP2:%.*]], i64 0
 682 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
 683 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[DOTSPLAT]])
 684 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 685 //
 686 // CPP-CHECK-LABEL: @_Z18test_svorr_n_s64_mu10__SVBool_tu11__SVInt64_tl(
 687 // CPP-CHECK-NEXT:  entry:
 688 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 689 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[OP2:%.*]], i64 0
 690 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
 691 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[DOTSPLAT]])
 692 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 693 //
 694 svint64_t test_svorr_n_s64_m(svbool_t pg, svint64_t op1, int64_t op2) MODE_ATTR
 695 {
 696   return SVE_ACLE_FUNC(svorr,_n_s64,_m,)(pg, op1, op2);
 697 }
 698
 699 // CHECK-LABEL: @test_svorr_n_u8_m(
 700 // CHECK-NEXT:  entry:
 701 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[OP2:%.*]], i64 0
 702 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
 703 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[DOTSPLAT]])
 704 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 705 //
 706 // CPP-CHECK-LABEL: @_Z17test_svorr_n_u8_mu10__SVBool_tu11__SVUint8_th(
 707 // CPP-CHECK-NEXT:  entry:
 708 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[OP2:%.*]], i64 0
 709 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
 710 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.orr.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[DOTSPLAT]])
 711 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 712 //
 713 svuint8_t test_svorr_n_u8_m(svbool_t pg, svuint8_t op1, uint8_t op2) MODE_ATTR
 714 {
 715   return SVE_ACLE_FUNC(svorr,_n_u8,_m,)(pg, op1, op2);
 716 }
 717
 718 // CHECK-LABEL: @test_svorr_n_u16_m(
 719 // CHECK-NEXT:  entry:
 720 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
 721 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP2:%.*]], i64 0
 722 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
 723 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[DOTSPLAT]])
 724 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 725 //
 726 // CPP-CHECK-LABEL: @_Z18test_svorr_n_u16_mu10__SVBool_tu12__SVUint16_tt(
 727 // CPP-CHECK-NEXT:  entry:
 728 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
 729 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP2:%.*]], i64 0
 730 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
 731 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.orr.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[DOTSPLAT]])
 732 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 733 //
 734 svuint16_t test_svorr_n_u16_m(svbool_t pg, svuint16_t op1, uint16_t op2) MODE_ATTR
 735 {
 736   return SVE_ACLE_FUNC(svorr,_n_u16,_m,)(pg, op1, op2);
 737 }
 738
 739 // CHECK-LABEL: @test_svorr_n_u32_m(
 740 // CHECK-NEXT:  entry:
 741 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 742 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[OP2:%.*]], i64 0
 743 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[DOTSPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
 744 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[DOTSPLAT]])
 745 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 746 //
 747 // CPP-CHECK-LABEL: @_Z18test_svorr_n_u32_mu10__SVBool_tu12__SVUint32_tj(
 748 // CPP-CHECK-NEXT:  entry:
 749 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 750 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[OP2:%.*]], i64 0
 751 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[DOTSPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
 752 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[DOTSPLAT]])
 753 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 754 //
 755 svuint32_t test_svorr_n_u32_m(svbool_t pg, svuint32_t op1, uint32_t op2) MODE_ATTR
 756 {
 757   return SVE_ACLE_FUNC(svorr,_n_u32,_m,)(pg, op1, op2);
 758 }
 759
 760 // CHECK-LABEL: @test_svorr_n_u64_m(
 761 // CHECK-NEXT:  entry:
 762 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 763 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[OP2:%.*]], i64 0
 764 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
 765 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[DOTSPLAT]])
 766 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 767 //
 768 // CPP-CHECK-LABEL: @_Z18test_svorr_n_u64_mu10__SVBool_tu12__SVUint64_tm(
 769 // CPP-CHECK-NEXT:  entry:
 770 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 771 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[OP2:%.*]], i64 0
 772 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
 773 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.orr.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[DOTSPLAT]])
 774 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 775 //
 776 svuint64_t test_svorr_n_u64_m(svbool_t pg, svuint64_t op1, uint64_t op2) MODE_ATTR
 777 {
 778   return SVE_ACLE_FUNC(svorr,_n_u64,_m,)(pg, op1, op2);
 779 }
 780
 781 // CHECK-LABEL: @test_svorr_n_s8_x(
 782 // CHECK-NEXT:  entry:
 783 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[OP2:%.*]], i64 0
 784 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
 785 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.orr.u.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[DOTSPLAT]])
 786 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 787 //
 788 // CPP-CHECK-LABEL: @_Z17test_svorr_n_s8_xu10__SVBool_tu10__SVInt8_ta(
 789 // CPP-CHECK-NEXT:  entry:
 790 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[OP2:%.*]], i64 0
 791 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
 792 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.orr.u.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[DOTSPLAT]])
 793 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 794 //
 795 svint8_t test_svorr_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2) MODE_ATTR
 796 {
 797   return SVE_ACLE_FUNC(svorr,_n_s8,_x,)(pg, op1, op2);
 798 }
 799
 800 // CHECK-LABEL: @test_svorr_n_s16_x(
 801 // CHECK-NEXT:  entry:
 802 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
 803 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP2:%.*]], i64 0
 804 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
 805 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.orr.u.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[DOTSPLAT]])
 806 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 807 //
 808 // CPP-CHECK-LABEL: @_Z18test_svorr_n_s16_xu10__SVBool_tu11__SVInt16_ts(
 809 // CPP-CHECK-NEXT:  entry:
 810 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
 811 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP2:%.*]], i64 0
 812 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
 813 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.orr.u.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[DOTSPLAT]])
 814 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 815 //
 816 svint16_t test_svorr_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2) MODE_ATTR
 817 {
 818   return SVE_ACLE_FUNC(svorr,_n_s16,_x,)(pg, op1, op2);
 819 }
 820
 821 // CHECK-LABEL: @test_svorr_n_s32_x(
 822 // CHECK-NEXT:  entry:
 823 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 824 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[OP2:%.*]], i64 0
 825 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[DOTSPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
 826 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.orr.u.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[DOTSPLAT]])
 827 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 828 //
 829 // CPP-CHECK-LABEL: @_Z18test_svorr_n_s32_xu10__SVBool_tu11__SVInt32_ti(
 830 // CPP-CHECK-NEXT:  entry:
 831 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 832 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[OP2:%.*]], i64 0
 833 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[DOTSPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
 834 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.orr.u.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[DOTSPLAT]])
 835 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 836 //
 837 svint32_t test_svorr_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2) MODE_ATTR
 838 {
 839   return SVE_ACLE_FUNC(svorr,_n_s32,_x,)(pg, op1, op2);
 840 }
 841
 842 // CHECK-LABEL: @test_svorr_n_s64_x(
 843 // CHECK-NEXT:  entry:
 844 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 845 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[OP2:%.*]], i64 0
 846 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
 847 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.orr.u.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[DOTSPLAT]])
 848 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 849 //
 850 // CPP-CHECK-LABEL: @_Z18test_svorr_n_s64_xu10__SVBool_tu11__SVInt64_tl(
 851 // CPP-CHECK-NEXT:  entry:
 852 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 853 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[OP2:%.*]], i64 0
 854 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
 855 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.orr.u.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[DOTSPLAT]])
 856 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 857 //
 858 svint64_t test_svorr_n_s64_x(svbool_t pg, svint64_t op1, int64_t op2) MODE_ATTR
 859 {
 860   return SVE_ACLE_FUNC(svorr,_n_s64,_x,)(pg, op1, op2);
 861 }
 862
 863 // CHECK-LABEL: @test_svorr_n_u8_x(
 864 // CHECK-NEXT:  entry:
 865 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[OP2:%.*]], i64 0
 866 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
 867 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.orr.u.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[DOTSPLAT]])
 868 // CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 869 //
 870 // CPP-CHECK-LABEL: @_Z17test_svorr_n_u8_xu10__SVBool_tu11__SVUint8_th(
 871 // CPP-CHECK-NEXT:  entry:
 872 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[OP2:%.*]], i64 0
 873 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
 874 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.orr.u.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[DOTSPLAT]])
 875 // CPP-CHECK-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 876 //
 877 svuint8_t test_svorr_n_u8_x(svbool_t pg, svuint8_t op1, uint8_t op2) MODE_ATTR
 878 {
 879   return SVE_ACLE_FUNC(svorr,_n_u8,_x,)(pg, op1, op2);
 880 }
 881
 882 // CHECK-LABEL: @test_svorr_n_u16_x(
 883 // CHECK-NEXT:  entry:
 884 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
 885 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP2:%.*]], i64 0
 886 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
 887 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.orr.u.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[DOTSPLAT]])
 888 // CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 889 //
 890 // CPP-CHECK-LABEL: @_Z18test_svorr_n_u16_xu10__SVBool_tu12__SVUint16_tt(
 891 // CPP-CHECK-NEXT:  entry:
 892 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
 893 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP2:%.*]], i64 0
 894 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
 895 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.orr.u.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[DOTSPLAT]])
 896 // CPP-CHECK-NEXT:    ret <vscale x 8 x i16> [[TMP1]]
 897 //
 898 svuint16_t test_svorr_n_u16_x(svbool_t pg, svuint16_t op1, uint16_t op2) MODE_ATTR
 899 {
 900   return SVE_ACLE_FUNC(svorr,_n_u16,_x,)(pg, op1, op2);
 901 }
 902
 903 // CHECK-LABEL: @test_svorr_n_u32_x(
 904 // CHECK-NEXT:  entry:
 905 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 906 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[OP2:%.*]], i64 0
 907 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[DOTSPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
 908 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.orr.u.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[DOTSPLAT]])
 909 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 910 //
 911 // CPP-CHECK-LABEL: @_Z18test_svorr_n_u32_xu10__SVBool_tu12__SVUint32_tj(
 912 // CPP-CHECK-NEXT:  entry:
 913 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
 914 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[OP2:%.*]], i64 0
 915 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[DOTSPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
 916 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.orr.u.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[DOTSPLAT]])
 917 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
 918 //
 919 svuint32_t test_svorr_n_u32_x(svbool_t pg, svuint32_t op1, uint32_t op2) MODE_ATTR
 920 {
 921   return SVE_ACLE_FUNC(svorr,_n_u32,_x,)(pg, op1, op2);
 922 }
 923
 924 // CHECK-LABEL: @test_svorr_n_u64_x(
 925 // CHECK-NEXT:  entry:
 926 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 927 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[OP2:%.*]], i64 0
 928 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
 929 // CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.orr.u.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[DOTSPLAT]])
 930 // CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 931 //
 932 // CPP-CHECK-LABEL: @_Z18test_svorr_n_u64_xu10__SVBool_tu12__SVUint64_tm(
 933 // CPP-CHECK-NEXT:  entry:
 934 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
 935 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[OP2:%.*]], i64 0
 936 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
 937 // CPP-CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.orr.u.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[DOTSPLAT]])
 938 // CPP-CHECK-NEXT:    ret <vscale x 2 x i64> [[TMP1]]
 939 //
 940 svuint64_t test_svorr_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2) MODE_ATTR
 941 {
 942   return SVE_ACLE_FUNC(svorr,_n_u64,_x,)(pg, op1, op2);
 943 }
 944
 945 // CHECK-LABEL: @test_svorr_b_z(
 946 // CHECK-NEXT:  entry:
 947 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.orr.z.nxv16i1(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP2:%.*]])
 948 // CHECK-NEXT:    ret <vscale x 16 x i1> [[TMP0]]
 949 //
 950 // CPP-CHECK-LABEL: @_Z14test_svorr_b_zu10__SVBool_tS_S_(
 951 // CPP-CHECK-NEXT:  entry:
 952 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.orr.z.nxv16i1(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP2:%.*]])
 953 // CPP-CHECK-NEXT:    ret <vscale x 16 x i1> [[TMP0]]
 954 //
 955 svbool_t test_svorr_b_z(svbool_t pg, svbool_t op1, svbool_t op2) MODE_ATTR
 956 {
 957   return SVE_ACLE_FUNC(svorr,_b,_z,)(pg, op1, op2);
 958 }