clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_usdot.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // REQUIRES: aarch64-registered-target
   3 // RUN: %clang_cc1 -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
   4 // RUN: %clang_cc1 -target-feature +i8mm -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
   5 // RUN: %clang_cc1 -target-feature +i8mm -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
   6 // RUN: %clang_cc1 -target-feature +i8mm -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
   7 // RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +i8mm -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
   8 // RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +i8mm -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
   9
  10 #include <arm_sve.h>
  11
  12 #if defined __ARM_FEATURE_SME
  13 #define MODE_ATTR __arm_streaming
  14 #else
  15 #define MODE_ATTR
  16 #endif
  17
  18 #ifdef SVE_OVERLOADED_FORMS
  19 // A simple used,unused... macro, long enough to represent any SVE builtin.
  20 #define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3
  21 #else
  22 #define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4
  23 #endif
  24
  25 // CHECK-LABEL: @test_svusdot_s32(
  26 // CHECK-NEXT:  entry:
  27 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32> [[X:%.*]], <vscale x 16 x i8> [[Y:%.*]], <vscale x 16 x i8> [[Z:%.*]])
  28 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  29 //
  30 // CPP-CHECK-LABEL: @_Z16test_svusdot_s32u11__SVInt32_tu11__SVUint8_tu10__SVInt8_t(
  31 // CPP-CHECK-NEXT:  entry:
  32 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32> [[X:%.*]], <vscale x 16 x i8> [[Y:%.*]], <vscale x 16 x i8> [[Z:%.*]])
  33 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  34 //
  35 svint32_t test_svusdot_s32(svint32_t x, svuint8_t y, svint8_t z) MODE_ATTR {
  36   return SVE_ACLE_FUNC(svusdot, _s32, , )(x, y, z);
  37 }
  38
  39 // CHECK-LABEL: @test_svusdot_n_s32(
  40 // CHECK-NEXT:  entry:
  41 // CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[Z:%.*]], i64 0
  42 // CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
  43 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32> [[X:%.*]], <vscale x 16 x i8> [[Y:%.*]], <vscale x 16 x i8> [[DOTSPLAT]])
  44 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  45 //
  46 // CPP-CHECK-LABEL: @_Z18test_svusdot_n_s32u11__SVInt32_tu11__SVUint8_ta(
  47 // CPP-CHECK-NEXT:  entry:
  48 // CPP-CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[Z:%.*]], i64 0
  49 // CPP-CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
  50 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32> [[X:%.*]], <vscale x 16 x i8> [[Y:%.*]], <vscale x 16 x i8> [[DOTSPLAT]])
  51 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  52 //
  53 svint32_t test_svusdot_n_s32(svint32_t x, svuint8_t y, int8_t z) MODE_ATTR {
  54   return SVE_ACLE_FUNC(svusdot, _n_s32, , )(x, y, z);
  55 }
  56
  57 // CHECK-LABEL: @test_svusdot_lane_s32_0(
  58 // CHECK-NEXT:  entry:
  59 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> [[X:%.*]], <vscale x 16 x i8> [[Y:%.*]], <vscale x 16 x i8> [[Z:%.*]], i32 0)
  60 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  61 //
  62 // CPP-CHECK-LABEL: @_Z23test_svusdot_lane_s32_0u11__SVInt32_tu11__SVUint8_tu10__SVInt8_t(
  63 // CPP-CHECK-NEXT:  entry:
  64 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> [[X:%.*]], <vscale x 16 x i8> [[Y:%.*]], <vscale x 16 x i8> [[Z:%.*]], i32 0)
  65 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  66 //
  67 svint32_t test_svusdot_lane_s32_0(svint32_t x, svuint8_t y, svint8_t z) MODE_ATTR {
  68   return SVE_ACLE_FUNC(svusdot_lane, _s32, , )(x, y, z, 0);
  69 }
  70
  71 // CHECK-LABEL: @test_svusdot_lane_s32_1(
  72 // CHECK-NEXT:  entry:
  73 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> [[X:%.*]], <vscale x 16 x i8> [[Y:%.*]], <vscale x 16 x i8> [[Z:%.*]], i32 1)
  74 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  75 //
  76 // CPP-CHECK-LABEL: @_Z23test_svusdot_lane_s32_1u11__SVInt32_tu11__SVUint8_tu10__SVInt8_t(
  77 // CPP-CHECK-NEXT:  entry:
  78 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> [[X:%.*]], <vscale x 16 x i8> [[Y:%.*]], <vscale x 16 x i8> [[Z:%.*]], i32 1)
  79 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  80 //
  81 svint32_t test_svusdot_lane_s32_1(svint32_t x, svuint8_t y, svint8_t z) MODE_ATTR {
  82   return SVE_ACLE_FUNC(svusdot_lane, _s32, , )(x, y, z, 1);
  83 }
  84
  85 // CHECK-LABEL: @test_svusdot_lane_s32_2(
  86 // CHECK-NEXT:  entry:
  87 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> [[X:%.*]], <vscale x 16 x i8> [[Y:%.*]], <vscale x 16 x i8> [[Z:%.*]], i32 2)
  88 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  89 //
  90 // CPP-CHECK-LABEL: @_Z23test_svusdot_lane_s32_2u11__SVInt32_tu11__SVUint8_tu10__SVInt8_t(
  91 // CPP-CHECK-NEXT:  entry:
  92 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> [[X:%.*]], <vscale x 16 x i8> [[Y:%.*]], <vscale x 16 x i8> [[Z:%.*]], i32 2)
  93 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
  94 //
  95 svint32_t test_svusdot_lane_s32_2(svint32_t x, svuint8_t y, svint8_t z) MODE_ATTR {
  96   return SVE_ACLE_FUNC(svusdot_lane, _s32, , )(x, y, z, 2);
  97 }
  98
  99 // CHECK-LABEL: @test_svusdot_lane_s32_3(
 100 // CHECK-NEXT:  entry:
 101 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> [[X:%.*]], <vscale x 16 x i8> [[Y:%.*]], <vscale x 16 x i8> [[Z:%.*]], i32 3)
 102 // CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 103 //
 104 // CPP-CHECK-LABEL: @_Z23test_svusdot_lane_s32_3u11__SVInt32_tu11__SVUint8_tu10__SVInt8_t(
 105 // CPP-CHECK-NEXT:  entry:
 106 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> [[X:%.*]], <vscale x 16 x i8> [[Y:%.*]], <vscale x 16 x i8> [[Z:%.*]], i32 3)
 107 // CPP-CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 108 //
 109 svint32_t test_svusdot_lane_s32_3(svint32_t x, svuint8_t y, svint8_t z) MODE_ATTR {
 110   return SVE_ACLE_FUNC(svusdot_lane, _s32, , )(x, y, z, 3);
 111 }