clang/test/CodeGen/AArch64/sve-vector-compare-ops.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve \
   3 // RUN: -disable-O0-optnone \
   4 // RUN:  -emit-llvm -o - %s | opt -S -passes=sroa | FileCheck %s
   5
   6 // REQUIRES: aarch64-registered-target
   7
   8 #include <arm_sve.h>
   9
  10 // EQ
  11
  12 // CHECK-LABEL: @eq_bool(
  13 // CHECK-NEXT:  entry:
  14 // CHECK-NEXT:    [[CMP:%.*]] = icmp eq <vscale x 16 x i1> [[A:%.*]], [[B:%.*]]
  15 // CHECK-NEXT:    ret <vscale x 16 x i1> [[CMP]]
  16 //
  17 svbool_t eq_bool(svbool_t a, svbool_t b) {
  18   return a == b;
  19 }
  20
  21 // CHECK-LABEL: @eq_i8(
  22 // CHECK-NEXT:  entry:
  23 // CHECK-NEXT:    [[CMP:%.*]] = icmp eq <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]
  24 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 16 x i1> [[CMP]] to <vscale x 16 x i8>
  25 // CHECK-NEXT:    ret <vscale x 16 x i8> [[CONV]]
  26 //
  27 svint8_t eq_i8(svint8_t a, svint8_t b) {
  28   return a == b;
  29 }
  30
  31 // CHECK-LABEL: @eq_i16(
  32 // CHECK-NEXT:  entry:
  33 // CHECK-NEXT:    [[CMP:%.*]] = icmp eq <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]
  34 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 8 x i1> [[CMP]] to <vscale x 8 x i16>
  35 // CHECK-NEXT:    ret <vscale x 8 x i16> [[CONV]]
  36 //
  37 svint16_t eq_i16(svint16_t a, svint16_t b) {
  38   return a == b;
  39 }
  40
  41 // CHECK-LABEL: @eq_i32(
  42 // CHECK-NEXT:  entry:
  43 // CHECK-NEXT:    [[CMP:%.*]] = icmp eq <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]
  44 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
  45 // CHECK-NEXT:    ret <vscale x 4 x i32> [[CONV]]
  46 //
  47 svint32_t eq_i32(svint32_t a, svint32_t b) {
  48   return a == b;
  49 }
  50
  51 // CHECK-LABEL: @eq_i64(
  52 // CHECK-NEXT:  entry:
  53 // CHECK-NEXT:    [[CMP:%.*]] = icmp eq <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]
  54 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
  55 // CHECK-NEXT:    ret <vscale x 2 x i64> [[CONV]]
  56 //
  57 svint64_t eq_i64(svint64_t a, svint64_t b) {
  58   return a == b;
  59 }
  60
  61 // CHECK-LABEL: @eq_u8(
  62 // CHECK-NEXT:  entry:
  63 // CHECK-NEXT:    [[CMP:%.*]] = icmp eq <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]
  64 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 16 x i1> [[CMP]] to <vscale x 16 x i8>
  65 // CHECK-NEXT:    ret <vscale x 16 x i8> [[CONV]]
  66 //
  67 svint8_t eq_u8(svuint8_t a, svuint8_t b) {
  68   return a == b;
  69 }
  70
  71 // CHECK-LABEL: @eq_u16(
  72 // CHECK-NEXT:  entry:
  73 // CHECK-NEXT:    [[CMP:%.*]] = icmp eq <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]
  74 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 8 x i1> [[CMP]] to <vscale x 8 x i16>
  75 // CHECK-NEXT:    ret <vscale x 8 x i16> [[CONV]]
  76 //
  77 svint16_t eq_u16(svuint16_t a, svuint16_t b) {
  78   return a == b;
  79 }
  80
  81 // CHECK-LABEL: @eq_u32(
  82 // CHECK-NEXT:  entry:
  83 // CHECK-NEXT:    [[CMP:%.*]] = icmp eq <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]
  84 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
  85 // CHECK-NEXT:    ret <vscale x 4 x i32> [[CONV]]
  86 //
  87 svint32_t eq_u32(svuint32_t a, svuint32_t b) {
  88   return a == b;
  89 }
  90
  91 // CHECK-LABEL: @eq_u64(
  92 // CHECK-NEXT:  entry:
  93 // CHECK-NEXT:    [[CMP:%.*]] = icmp eq <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]
  94 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
  95 // CHECK-NEXT:    ret <vscale x 2 x i64> [[CONV]]
  96 //
  97 svint64_t eq_u64(svuint64_t a, svuint64_t b) {
  98   return a == b;
  99 }
 100
 101 // CHECK-LABEL: @eq_f16(
 102 // CHECK-NEXT:  entry:
 103 // CHECK-NEXT:    [[CMP:%.*]] = fcmp oeq <vscale x 8 x half> [[A:%.*]], [[B:%.*]]
 104 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 8 x i1> [[CMP]] to <vscale x 8 x i16>
 105 // CHECK-NEXT:    ret <vscale x 8 x i16> [[CONV]]
 106 //
 107 svint16_t eq_f16(svfloat16_t a, svfloat16_t b) {
 108   return a == b;
 109 }
 110
 111 // CHECK-LABEL: @eq_f32(
 112 // CHECK-NEXT:  entry:
 113 // CHECK-NEXT:    [[CMP:%.*]] = fcmp oeq <vscale x 4 x float> [[A:%.*]], [[B:%.*]]
 114 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
 115 // CHECK-NEXT:    ret <vscale x 4 x i32> [[CONV]]
 116 //
 117 svint32_t eq_f32(svfloat32_t a, svfloat32_t b) {
 118   return a == b;
 119 }
 120
 121 // CHECK-LABEL: @eq_f64(
 122 // CHECK-NEXT:  entry:
 123 // CHECK-NEXT:    [[CMP:%.*]] = fcmp oeq <vscale x 2 x double> [[A:%.*]], [[B:%.*]]
 124 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
 125 // CHECK-NEXT:    ret <vscale x 2 x i64> [[CONV]]
 126 //
 127 svint64_t eq_f64(svfloat64_t a, svfloat64_t b) {
 128   return a == b;
 129 }
 130
 131 // NEQ
 132
 133 // CHECK-LABEL: @neq_bool(
 134 // CHECK-NEXT:  entry:
 135 // CHECK-NEXT:    [[CMP:%.*]] = icmp ne <vscale x 16 x i1> [[A:%.*]], [[B:%.*]]
 136 // CHECK-NEXT:    ret <vscale x 16 x i1> [[CMP]]
 137 //
 138 svbool_t neq_bool(svbool_t a, svbool_t b) {
 139   return a != b;
 140 }
 141
 142 // CHECK-LABEL: @neq_i8(
 143 // CHECK-NEXT:  entry:
 144 // CHECK-NEXT:    [[CMP:%.*]] = icmp ne <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]
 145 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 16 x i1> [[CMP]] to <vscale x 16 x i8>
 146 // CHECK-NEXT:    ret <vscale x 16 x i8> [[CONV]]
 147 //
 148 svint8_t neq_i8(svint8_t a, svint8_t b) {
 149   return a != b;
 150 }
 151
 152 // CHECK-LABEL: @neq_i16(
 153 // CHECK-NEXT:  entry:
 154 // CHECK-NEXT:    [[CMP:%.*]] = icmp ne <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]
 155 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 8 x i1> [[CMP]] to <vscale x 8 x i16>
 156 // CHECK-NEXT:    ret <vscale x 8 x i16> [[CONV]]
 157 //
 158 svint16_t neq_i16(svint16_t a, svint16_t b) {
 159   return a != b;
 160 }
 161
 162 // CHECK-LABEL: @neq_i32(
 163 // CHECK-NEXT:  entry:
 164 // CHECK-NEXT:    [[CMP:%.*]] = icmp ne <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]
 165 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
 166 // CHECK-NEXT:    ret <vscale x 4 x i32> [[CONV]]
 167 //
 168 svint32_t neq_i32(svint32_t a, svint32_t b) {
 169   return a != b;
 170 }
 171
 172 // CHECK-LABEL: @neq_i64(
 173 // CHECK-NEXT:  entry:
 174 // CHECK-NEXT:    [[CMP:%.*]] = icmp ne <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]
 175 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
 176 // CHECK-NEXT:    ret <vscale x 2 x i64> [[CONV]]
 177 //
 178 svint64_t neq_i64(svint64_t a, svint64_t b) {
 179   return a != b;
 180 }
 181
 182 // CHECK-LABEL: @neq_u8(
 183 // CHECK-NEXT:  entry:
 184 // CHECK-NEXT:    [[CMP:%.*]] = icmp ne <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]
 185 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 16 x i1> [[CMP]] to <vscale x 16 x i8>
 186 // CHECK-NEXT:    ret <vscale x 16 x i8> [[CONV]]
 187 //
 188 svint8_t neq_u8(svuint8_t a, svuint8_t b) {
 189   return a != b;
 190 }
 191
 192 // CHECK-LABEL: @neq_u16(
 193 // CHECK-NEXT:  entry:
 194 // CHECK-NEXT:    [[CMP:%.*]] = icmp ne <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]
 195 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 8 x i1> [[CMP]] to <vscale x 8 x i16>
 196 // CHECK-NEXT:    ret <vscale x 8 x i16> [[CONV]]
 197 //
 198 svint16_t neq_u16(svuint16_t a, svuint16_t b) {
 199   return a != b;
 200 }
 201
 202 // CHECK-LABEL: @neq_u32(
 203 // CHECK-NEXT:  entry:
 204 // CHECK-NEXT:    [[CMP:%.*]] = icmp ne <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]
 205 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
 206 // CHECK-NEXT:    ret <vscale x 4 x i32> [[CONV]]
 207 //
 208 svint32_t neq_u32(svuint32_t a, svuint32_t b) {
 209   return a != b;
 210 }
 211
 212 // CHECK-LABEL: @neq_u64(
 213 // CHECK-NEXT:  entry:
 214 // CHECK-NEXT:    [[CMP:%.*]] = icmp ne <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]
 215 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
 216 // CHECK-NEXT:    ret <vscale x 2 x i64> [[CONV]]
 217 //
 218 svint64_t neq_u64(svuint64_t a, svuint64_t b) {
 219   return a != b;
 220 }
 221
 222 // CHECK-LABEL: @neq_f16(
 223 // CHECK-NEXT:  entry:
 224 // CHECK-NEXT:    [[CMP:%.*]] = fcmp une <vscale x 8 x half> [[A:%.*]], [[B:%.*]]
 225 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 8 x i1> [[CMP]] to <vscale x 8 x i16>
 226 // CHECK-NEXT:    ret <vscale x 8 x i16> [[CONV]]
 227 //
 228 svint16_t neq_f16(svfloat16_t a, svfloat16_t b) {
 229   return a != b;
 230 }
 231
 232 // CHECK-LABEL: @neq_f32(
 233 // CHECK-NEXT:  entry:
 234 // CHECK-NEXT:    [[CMP:%.*]] = fcmp une <vscale x 4 x float> [[A:%.*]], [[B:%.*]]
 235 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
 236 // CHECK-NEXT:    ret <vscale x 4 x i32> [[CONV]]
 237 //
 238 svint32_t neq_f32(svfloat32_t a, svfloat32_t b) {
 239   return a != b;
 240 }
 241
 242 // CHECK-LABEL: @neq_f64(
 243 // CHECK-NEXT:  entry:
 244 // CHECK-NEXT:    [[CMP:%.*]] = fcmp une <vscale x 2 x double> [[A:%.*]], [[B:%.*]]
 245 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
 246 // CHECK-NEXT:    ret <vscale x 2 x i64> [[CONV]]
 247 //
 248 svint64_t neq_f64(svfloat64_t a, svfloat64_t b) {
 249   return a != b;
 250 }
 251
 252 // LT
 253
 254 // CHECK-LABEL: @lt_bool(
 255 // CHECK-NEXT:  entry:
 256 // CHECK-NEXT:    [[CMP:%.*]] = icmp ult <vscale x 16 x i1> [[A:%.*]], [[B:%.*]]
 257 // CHECK-NEXT:    ret <vscale x 16 x i1> [[CMP]]
 258 //
 259 svbool_t lt_bool(svbool_t a, svbool_t b) {
 260   return a < b;
 261 }
 262
 263 // CHECK-LABEL: @lt_i8(
 264 // CHECK-NEXT:  entry:
 265 // CHECK-NEXT:    [[CMP:%.*]] = icmp ult <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]
 266 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 16 x i1> [[CMP]] to <vscale x 16 x i8>
 267 // CHECK-NEXT:    ret <vscale x 16 x i8> [[CONV]]
 268 //
 269 svint8_t lt_i8(svint8_t a, svint8_t b) {
 270   return a < b;
 271 }
 272
 273 // CHECK-LABEL: @lt_i16(
 274 // CHECK-NEXT:  entry:
 275 // CHECK-NEXT:    [[CMP:%.*]] = icmp ult <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]
 276 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 8 x i1> [[CMP]] to <vscale x 8 x i16>
 277 // CHECK-NEXT:    ret <vscale x 8 x i16> [[CONV]]
 278 //
 279 svint16_t lt_i16(svint16_t a, svint16_t b) {
 280   return a < b;
 281 }
 282
 283 // CHECK-LABEL: @lt_i32(
 284 // CHECK-NEXT:  entry:
 285 // CHECK-NEXT:    [[CMP:%.*]] = icmp ult <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]
 286 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
 287 // CHECK-NEXT:    ret <vscale x 4 x i32> [[CONV]]
 288 //
 289 svint32_t lt_i32(svint32_t a, svint32_t b) {
 290   return a < b;
 291 }
 292
 293 // CHECK-LABEL: @lt_i64(
 294 // CHECK-NEXT:  entry:
 295 // CHECK-NEXT:    [[CMP:%.*]] = icmp ult <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]
 296 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
 297 // CHECK-NEXT:    ret <vscale x 2 x i64> [[CONV]]
 298 //
 299 svint64_t lt_i64(svint64_t a, svint64_t b) {
 300   return a < b;
 301 }
 302
 303 // CHECK-LABEL: @lt_u8(
 304 // CHECK-NEXT:  entry:
 305 // CHECK-NEXT:    [[CMP:%.*]] = icmp ult <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]
 306 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 16 x i1> [[CMP]] to <vscale x 16 x i8>
 307 // CHECK-NEXT:    ret <vscale x 16 x i8> [[CONV]]
 308 //
 309 svint8_t lt_u8(svuint8_t a, svuint8_t b) {
 310   return a < b;
 311 }
 312
 313 // CHECK-LABEL: @lt_u16(
 314 // CHECK-NEXT:  entry:
 315 // CHECK-NEXT:    [[CMP:%.*]] = icmp ult <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]
 316 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 8 x i1> [[CMP]] to <vscale x 8 x i16>
 317 // CHECK-NEXT:    ret <vscale x 8 x i16> [[CONV]]
 318 //
 319 svint16_t lt_u16(svuint16_t a, svuint16_t b) {
 320   return a < b;
 321 }
 322
 323 // CHECK-LABEL: @lt_u32(
 324 // CHECK-NEXT:  entry:
 325 // CHECK-NEXT:    [[CMP:%.*]] = icmp ult <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]
 326 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
 327 // CHECK-NEXT:    ret <vscale x 4 x i32> [[CONV]]
 328 //
 329 svint32_t lt_u32(svuint32_t a, svuint32_t b) {
 330   return a < b;
 331 }
 332
 333 // CHECK-LABEL: @lt_u64(
 334 // CHECK-NEXT:  entry:
 335 // CHECK-NEXT:    [[CMP:%.*]] = icmp ult <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]
 336 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
 337 // CHECK-NEXT:    ret <vscale x 2 x i64> [[CONV]]
 338 //
 339 svint64_t lt_u64(svuint64_t a, svuint64_t b) {
 340   return a < b;
 341 }
 342
 343 // CHECK-LABEL: @lt_f16(
 344 // CHECK-NEXT:  entry:
 345 // CHECK-NEXT:    [[CMP:%.*]] = fcmp olt <vscale x 8 x half> [[A:%.*]], [[B:%.*]]
 346 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 8 x i1> [[CMP]] to <vscale x 8 x i16>
 347 // CHECK-NEXT:    ret <vscale x 8 x i16> [[CONV]]
 348 //
 349 svint16_t lt_f16(svfloat16_t a, svfloat16_t b) {
 350   return a < b;
 351 }
 352
 353 // CHECK-LABEL: @lt_f32(
 354 // CHECK-NEXT:  entry:
 355 // CHECK-NEXT:    [[CMP:%.*]] = fcmp olt <vscale x 4 x float> [[A:%.*]], [[B:%.*]]
 356 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
 357 // CHECK-NEXT:    ret <vscale x 4 x i32> [[CONV]]
 358 //
 359 svint32_t lt_f32(svfloat32_t a, svfloat32_t b) {
 360   return a < b;
 361 }
 362
 363 // CHECK-LABEL: @lt_f64(
 364 // CHECK-NEXT:  entry:
 365 // CHECK-NEXT:    [[CMP:%.*]] = fcmp olt <vscale x 2 x double> [[A:%.*]], [[B:%.*]]
 366 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
 367 // CHECK-NEXT:    ret <vscale x 2 x i64> [[CONV]]
 368 //
 369 svint64_t lt_f64(svfloat64_t a, svfloat64_t b) {
 370   return a < b;
 371 }
 372
 373 // LEQ
 374
 375 // CHECK-LABEL: @leq_bool(
 376 // CHECK-NEXT:  entry:
 377 // CHECK-NEXT:    [[CMP:%.*]] = icmp ule <vscale x 16 x i1> [[A:%.*]], [[B:%.*]]
 378 // CHECK-NEXT:    ret <vscale x 16 x i1> [[CMP]]
 379 //
 380 svbool_t leq_bool(svbool_t a, svbool_t b) {
 381   return a <= b;
 382 }
 383
 384 // CHECK-LABEL: @leq_i8(
 385 // CHECK-NEXT:  entry:
 386 // CHECK-NEXT:    [[CMP:%.*]] = icmp ule <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]
 387 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 16 x i1> [[CMP]] to <vscale x 16 x i8>
 388 // CHECK-NEXT:    ret <vscale x 16 x i8> [[CONV]]
 389 //
 390 svint8_t leq_i8(svint8_t a, svint8_t b) {
 391   return a <= b;
 392 }
 393
 394 // CHECK-LABEL: @leq_i16(
 395 // CHECK-NEXT:  entry:
 396 // CHECK-NEXT:    [[CMP:%.*]] = icmp ule <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]
 397 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 8 x i1> [[CMP]] to <vscale x 8 x i16>
 398 // CHECK-NEXT:    ret <vscale x 8 x i16> [[CONV]]
 399 //
 400 svint16_t leq_i16(svint16_t a, svint16_t b) {
 401   return a <= b;
 402 }
 403
 404 // CHECK-LABEL: @leq_i32(
 405 // CHECK-NEXT:  entry:
 406 // CHECK-NEXT:    [[CMP:%.*]] = icmp ule <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]
 407 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
 408 // CHECK-NEXT:    ret <vscale x 4 x i32> [[CONV]]
 409 //
 410 svint32_t leq_i32(svint32_t a, svint32_t b) {
 411   return a <= b;
 412 }
 413
 414 // CHECK-LABEL: @leq_i64(
 415 // CHECK-NEXT:  entry:
 416 // CHECK-NEXT:    [[CMP:%.*]] = icmp ule <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]
 417 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
 418 // CHECK-NEXT:    ret <vscale x 2 x i64> [[CONV]]
 419 //
 420 svint64_t leq_i64(svint64_t a, svint64_t b) {
 421   return a <= b;
 422 }
 423
 424 // CHECK-LABEL: @leq_u8(
 425 // CHECK-NEXT:  entry:
 426 // CHECK-NEXT:    [[CMP:%.*]] = icmp ule <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]
 427 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 16 x i1> [[CMP]] to <vscale x 16 x i8>
 428 // CHECK-NEXT:    ret <vscale x 16 x i8> [[CONV]]
 429 //
 430 svint8_t leq_u8(svuint8_t a, svuint8_t b) {
 431   return a <= b;
 432 }
 433
 434 // CHECK-LABEL: @leq_u16(
 435 // CHECK-NEXT:  entry:
 436 // CHECK-NEXT:    [[CMP:%.*]] = icmp ule <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]
 437 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 8 x i1> [[CMP]] to <vscale x 8 x i16>
 438 // CHECK-NEXT:    ret <vscale x 8 x i16> [[CONV]]
 439 //
 440 svint16_t leq_u16(svuint16_t a, svuint16_t b) {
 441   return a <= b;
 442 }
 443
 444 // CHECK-LABEL: @leq_u32(
 445 // CHECK-NEXT:  entry:
 446 // CHECK-NEXT:    [[CMP:%.*]] = icmp ule <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]
 447 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
 448 // CHECK-NEXT:    ret <vscale x 4 x i32> [[CONV]]
 449 //
 450 svint32_t leq_u32(svuint32_t a, svuint32_t b) {
 451   return a <= b;
 452 }
 453
 454 // CHECK-LABEL: @leq_u64(
 455 // CHECK-NEXT:  entry:
 456 // CHECK-NEXT:    [[CMP:%.*]] = icmp ule <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]
 457 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
 458 // CHECK-NEXT:    ret <vscale x 2 x i64> [[CONV]]
 459 //
 460 svint64_t leq_u64(svuint64_t a, svuint64_t b) {
 461   return a <= b;
 462 }
 463
 464 // CHECK-LABEL: @leq_f16(
 465 // CHECK-NEXT:  entry:
 466 // CHECK-NEXT:    [[CMP:%.*]] = fcmp ole <vscale x 8 x half> [[A:%.*]], [[B:%.*]]
 467 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 8 x i1> [[CMP]] to <vscale x 8 x i16>
 468 // CHECK-NEXT:    ret <vscale x 8 x i16> [[CONV]]
 469 //
 470 svint16_t leq_f16(svfloat16_t a, svfloat16_t b) {
 471   return a <= b;
 472 }
 473
 474 // CHECK-LABEL: @leq_f32(
 475 // CHECK-NEXT:  entry:
 476 // CHECK-NEXT:    [[CMP:%.*]] = fcmp ole <vscale x 4 x float> [[A:%.*]], [[B:%.*]]
 477 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
 478 // CHECK-NEXT:    ret <vscale x 4 x i32> [[CONV]]
 479 //
 480 svint32_t leq_f32(svfloat32_t a, svfloat32_t b) {
 481   return a <= b;
 482 }
 483
 484 // CHECK-LABEL: @leq_f64(
 485 // CHECK-NEXT:  entry:
 486 // CHECK-NEXT:    [[CMP:%.*]] = fcmp ole <vscale x 2 x double> [[A:%.*]], [[B:%.*]]
 487 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
 488 // CHECK-NEXT:    ret <vscale x 2 x i64> [[CONV]]
 489 //
 490 svint64_t leq_f64(svfloat64_t a, svfloat64_t b) {
 491   return a <= b;
 492 }
 493
 494 // GT
 495
 496 // CHECK-LABEL: @gt_bool(
 497 // CHECK-NEXT:  entry:
 498 // CHECK-NEXT:    [[CMP:%.*]] = icmp ugt <vscale x 16 x i1> [[A:%.*]], [[B:%.*]]
 499 // CHECK-NEXT:    ret <vscale x 16 x i1> [[CMP]]
 500 //
 501 svbool_t gt_bool(svbool_t a, svbool_t b) {
 502   return a > b;
 503 }
 504
 505 // CHECK-LABEL: @gt_i8(
 506 // CHECK-NEXT:  entry:
 507 // CHECK-NEXT:    [[CMP:%.*]] = icmp ugt <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]
 508 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 16 x i1> [[CMP]] to <vscale x 16 x i8>
 509 // CHECK-NEXT:    ret <vscale x 16 x i8> [[CONV]]
 510 //
 511 svint8_t gt_i8(svint8_t a, svint8_t b) {
 512   return a > b;
 513 }
 514
 515 // CHECK-LABEL: @gt_i16(
 516 // CHECK-NEXT:  entry:
 517 // CHECK-NEXT:    [[CMP:%.*]] = icmp ugt <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]
 518 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 8 x i1> [[CMP]] to <vscale x 8 x i16>
 519 // CHECK-NEXT:    ret <vscale x 8 x i16> [[CONV]]
 520 //
 521 svint16_t gt_i16(svint16_t a, svint16_t b) {
 522   return a > b;
 523 }
 524
 525 // CHECK-LABEL: @gt_i32(
 526 // CHECK-NEXT:  entry:
 527 // CHECK-NEXT:    [[CMP:%.*]] = icmp ugt <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]
 528 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
 529 // CHECK-NEXT:    ret <vscale x 4 x i32> [[CONV]]
 530 //
 531 svint32_t gt_i32(svint32_t a, svint32_t b) {
 532   return a > b;
 533 }
 534
 535 // CHECK-LABEL: @gt_i64(
 536 // CHECK-NEXT:  entry:
 537 // CHECK-NEXT:    [[CMP:%.*]] = icmp ugt <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]
 538 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
 539 // CHECK-NEXT:    ret <vscale x 2 x i64> [[CONV]]
 540 //
 541 svint64_t gt_i64(svint64_t a, svint64_t b) {
 542   return a > b;
 543 }
 544
 545 // CHECK-LABEL: @gt_u8(
 546 // CHECK-NEXT:  entry:
 547 // CHECK-NEXT:    [[CMP:%.*]] = icmp ugt <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]
 548 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 16 x i1> [[CMP]] to <vscale x 16 x i8>
 549 // CHECK-NEXT:    ret <vscale x 16 x i8> [[CONV]]
 550 //
 551 svint8_t gt_u8(svuint8_t a, svuint8_t b) {
 552   return a > b;
 553 }
 554
 555 // CHECK-LABEL: @gt_u16(
 556 // CHECK-NEXT:  entry:
 557 // CHECK-NEXT:    [[CMP:%.*]] = icmp ugt <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]
 558 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 8 x i1> [[CMP]] to <vscale x 8 x i16>
 559 // CHECK-NEXT:    ret <vscale x 8 x i16> [[CONV]]
 560 //
 561 svint16_t gt_u16(svuint16_t a, svuint16_t b) {
 562   return a > b;
 563 }
 564
 565 // CHECK-LABEL: @gt_u32(
 566 // CHECK-NEXT:  entry:
 567 // CHECK-NEXT:    [[CMP:%.*]] = icmp ugt <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]
 568 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
 569 // CHECK-NEXT:    ret <vscale x 4 x i32> [[CONV]]
 570 //
 571 svint32_t gt_u32(svuint32_t a, svuint32_t b) {
 572   return a > b;
 573 }
 574
 575 // CHECK-LABEL: @gt_u64(
 576 // CHECK-NEXT:  entry:
 577 // CHECK-NEXT:    [[CMP:%.*]] = icmp ugt <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]
 578 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
 579 // CHECK-NEXT:    ret <vscale x 2 x i64> [[CONV]]
 580 //
 581 svint64_t gt_u64(svuint64_t a, svuint64_t b) {
 582   return a > b;
 583 }
 584
 585 // CHECK-LABEL: @gt_f16(
 586 // CHECK-NEXT:  entry:
 587 // CHECK-NEXT:    [[CMP:%.*]] = fcmp ogt <vscale x 8 x half> [[A:%.*]], [[B:%.*]]
 588 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 8 x i1> [[CMP]] to <vscale x 8 x i16>
 589 // CHECK-NEXT:    ret <vscale x 8 x i16> [[CONV]]
 590 //
 591 svint16_t gt_f16(svfloat16_t a, svfloat16_t b) {
 592   return a > b;
 593 }
 594
 595 // CHECK-LABEL: @gt_f32(
 596 // CHECK-NEXT:  entry:
 597 // CHECK-NEXT:    [[CMP:%.*]] = fcmp ogt <vscale x 4 x float> [[A:%.*]], [[B:%.*]]
 598 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
 599 // CHECK-NEXT:    ret <vscale x 4 x i32> [[CONV]]
 600 //
 601 svint32_t gt_f32(svfloat32_t a, svfloat32_t b) {
 602   return a > b;
 603 }
 604
 605 // CHECK-LABEL: @gt_f64(
 606 // CHECK-NEXT:  entry:
 607 // CHECK-NEXT:    [[CMP:%.*]] = fcmp ogt <vscale x 2 x double> [[A:%.*]], [[B:%.*]]
 608 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
 609 // CHECK-NEXT:    ret <vscale x 2 x i64> [[CONV]]
 610 //
 611 svint64_t gt_f64(svfloat64_t a, svfloat64_t b) {
 612   return a > b;
 613 }
 614
 615 // GEQ
 616
 617 // CHECK-LABEL: @geq_bool(
 618 // CHECK-NEXT:  entry:
 619 // CHECK-NEXT:    [[CMP:%.*]] = icmp uge <vscale x 16 x i1> [[A:%.*]], [[B:%.*]]
 620 // CHECK-NEXT:    ret <vscale x 16 x i1> [[CMP]]
 621 //
 622 svbool_t geq_bool(svbool_t a, svbool_t b) {
 623   return a >= b;
 624 }
 625
 626 // CHECK-LABEL: @geq_i8(
 627 // CHECK-NEXT:  entry:
 628 // CHECK-NEXT:    [[CMP:%.*]] = icmp uge <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]
 629 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 16 x i1> [[CMP]] to <vscale x 16 x i8>
 630 // CHECK-NEXT:    ret <vscale x 16 x i8> [[CONV]]
 631 //
 632 svint8_t geq_i8(svint8_t a, svint8_t b) {
 633   return a >= b;
 634 }
 635
 636 // CHECK-LABEL: @geq_i16(
 637 // CHECK-NEXT:  entry:
 638 // CHECK-NEXT:    [[CMP:%.*]] = icmp uge <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]
 639 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 8 x i1> [[CMP]] to <vscale x 8 x i16>
 640 // CHECK-NEXT:    ret <vscale x 8 x i16> [[CONV]]
 641 //
 642 svint16_t geq_i16(svint16_t a, svint16_t b) {
 643   return a >= b;
 644 }
 645
 646 // CHECK-LABEL: @geq_i32(
 647 // CHECK-NEXT:  entry:
 648 // CHECK-NEXT:    [[CMP:%.*]] = icmp uge <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]
 649 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
 650 // CHECK-NEXT:    ret <vscale x 4 x i32> [[CONV]]
 651 //
 652 svint32_t geq_i32(svint32_t a, svint32_t b) {
 653   return a >= b;
 654 }
 655
 656 // CHECK-LABEL: @geq_i64(
 657 // CHECK-NEXT:  entry:
 658 // CHECK-NEXT:    [[CMP:%.*]] = icmp uge <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]
 659 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
 660 // CHECK-NEXT:    ret <vscale x 2 x i64> [[CONV]]
 661 //
 662 svint64_t geq_i64(svint64_t a, svint64_t b) {
 663   return a >= b;
 664 }
 665
 666 // CHECK-LABEL: @geq_u8(
 667 // CHECK-NEXT:  entry:
 668 // CHECK-NEXT:    [[CMP:%.*]] = icmp uge <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]
 669 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 16 x i1> [[CMP]] to <vscale x 16 x i8>
 670 // CHECK-NEXT:    ret <vscale x 16 x i8> [[CONV]]
 671 //
 672 svint8_t geq_u8(svuint8_t a, svuint8_t b) {
 673   return a >= b;
 674 }
 675
 676 // CHECK-LABEL: @geq_u16(
 677 // CHECK-NEXT:  entry:
 678 // CHECK-NEXT:    [[CMP:%.*]] = icmp uge <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]
 679 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 8 x i1> [[CMP]] to <vscale x 8 x i16>
 680 // CHECK-NEXT:    ret <vscale x 8 x i16> [[CONV]]
 681 //
 682 svint16_t geq_u16(svuint16_t a, svuint16_t b) {
 683   return a >= b;
 684 }
 685
 686 // CHECK-LABEL: @geq_u32(
 687 // CHECK-NEXT:  entry:
 688 // CHECK-NEXT:    [[CMP:%.*]] = icmp uge <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]
 689 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
 690 // CHECK-NEXT:    ret <vscale x 4 x i32> [[CONV]]
 691 //
 692 svint32_t geq_u32(svuint32_t a, svuint32_t b) {
 693   return a >= b;
 694 }
 695
 696 // CHECK-LABEL: @geq_u64(
 697 // CHECK-NEXT:  entry:
 698 // CHECK-NEXT:    [[CMP:%.*]] = icmp uge <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]
 699 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
 700 // CHECK-NEXT:    ret <vscale x 2 x i64> [[CONV]]
 701 //
 702 svint64_t geq_u64(svuint64_t a, svuint64_t b) {
 703   return a >= b;
 704 }
 705
 706 // CHECK-LABEL: @geq_f16(
 707 // CHECK-NEXT:  entry:
 708 // CHECK-NEXT:    [[CMP:%.*]] = fcmp oge <vscale x 8 x half> [[A:%.*]], [[B:%.*]]
 709 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 8 x i1> [[CMP]] to <vscale x 8 x i16>
 710 // CHECK-NEXT:    ret <vscale x 8 x i16> [[CONV]]
 711 //
 712 svint16_t geq_f16(svfloat16_t a, svfloat16_t b) {
 713   return a >= b;
 714 }
 715
 716 // CHECK-LABEL: @geq_f32(
 717 // CHECK-NEXT:  entry:
 718 // CHECK-NEXT:    [[CMP:%.*]] = fcmp oge <vscale x 4 x float> [[A:%.*]], [[B:%.*]]
 719 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
 720 // CHECK-NEXT:    ret <vscale x 4 x i32> [[CONV]]
 721 //
 722 svint32_t geq_f32(svfloat32_t a, svfloat32_t b) {
 723   return a >= b;
 724 }
 725
 726 // CHECK-LABEL: @geq_f64(
 727 // CHECK-NEXT:  entry:
 728 // CHECK-NEXT:    [[CMP:%.*]] = fcmp oge <vscale x 2 x double> [[A:%.*]], [[B:%.*]]
 729 // CHECK-NEXT:    [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
 730 // CHECK-NEXT:    ret <vscale x 2 x i64> [[CONV]]
 731 //
 732 svint64_t geq_f64(svfloat64_t a, svfloat64_t b) {
 733   return a >= b;
 734 }