clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // REQUIRES: aarch64-registered-target
   3
   4 // RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
   5 // RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +bf16 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
   6 // RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
   7 // RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +bf16 -target-feature +sme -target-feature +sme2 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
   8 // RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
   9 // RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
  10 // RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve2p1 -disable-O0-optnone -Werror -Wall -o /dev/null %s
  11 // RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +bf16 -target-feature +sme -target-feature +sme2 -disable-O0-optnone -Werror -Wall -o /dev/null %s
  12
  13 #include <arm_sve.h>
  14
  15 #ifdef __ARM_FEATURE_SME
  16 #define ATTR __arm_streaming
  17 #else
  18 #define ATTR
  19 #endif
  20
  21 #ifdef SVE_OVERLOADED_FORMS
  22 // A simple used,unused... macro, long enough to represent any SVE builtin.
  23 #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
  24 #else
  25 #define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
  26 #endif
  27
  28 // BFMLSLB
  29
  30
  31 // CHECK-LABEL: @test_bfmlslb(
  32 // CHECK-NEXT:  entry:
  33 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb(<vscale x 4 x float> [[ZDA:%.*]], <vscale x 8 x bfloat> [[ZN:%.*]], <vscale x 8 x bfloat> [[ZM:%.*]])
  34 // CHECK-NEXT:    ret <vscale x 4 x float> [[TMP0]]
  35 //
  36 // CPP-CHECK-LABEL: @_Z12test_bfmlslbu13__SVFloat32_tu14__SVBfloat16_tS0_(
  37 // CPP-CHECK-NEXT:  entry:
  38 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb(<vscale x 4 x float> [[ZDA:%.*]], <vscale x 8 x bfloat> [[ZN:%.*]], <vscale x 8 x bfloat> [[ZM:%.*]])
  39 // CPP-CHECK-NEXT:    ret <vscale x 4 x float> [[TMP0]]
  40 //
  41 svfloat32_t test_bfmlslb(svfloat32_t zda, svbfloat16_t zn, svbfloat16_t zm) ATTR
  42 {
  43   return SVE_ACLE_FUNC(svbfmlslb,_f32,,)(zda, zn, zm);
  44 }
  45
  46
  47 // CHECK-LABEL: @test_bfmlslb_lane(
  48 // CHECK-NEXT:  entry:
  49 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb.lane(<vscale x 4 x float> [[ZDA:%.*]], <vscale x 8 x bfloat> [[ZN:%.*]], <vscale x 8 x bfloat> [[ZM:%.*]], i32 7)
  50 // CHECK-NEXT:    ret <vscale x 4 x float> [[TMP0]]
  51 //
  52 // CPP-CHECK-LABEL: @_Z17test_bfmlslb_laneu13__SVFloat32_tu14__SVBfloat16_tS0_(
  53 // CPP-CHECK-NEXT:  entry:
  54 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb.lane(<vscale x 4 x float> [[ZDA:%.*]], <vscale x 8 x bfloat> [[ZN:%.*]], <vscale x 8 x bfloat> [[ZM:%.*]], i32 7)
  55 // CPP-CHECK-NEXT:    ret <vscale x 4 x float> [[TMP0]]
  56 //
  57 svfloat32_t test_bfmlslb_lane(svfloat32_t zda, svbfloat16_t zn, svbfloat16_t zm) ATTR
  58 {
  59   return SVE_ACLE_FUNC(svbfmlslb_lane,_f32,,)(zda, zn, zm, 7);
  60 }
  61
  62 // BFMLSLT
  63
  64
  65 // CHECK-LABEL: @test_bfmlslt(
  66 // CHECK-NEXT:  entry:
  67 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt(<vscale x 4 x float> [[ZDA:%.*]], <vscale x 8 x bfloat> [[ZN:%.*]], <vscale x 8 x bfloat> [[ZM:%.*]])
  68 // CHECK-NEXT:    ret <vscale x 4 x float> [[TMP0]]
  69 //
  70 // CPP-CHECK-LABEL: @_Z12test_bfmlsltu13__SVFloat32_tu14__SVBfloat16_tS0_(
  71 // CPP-CHECK-NEXT:  entry:
  72 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt(<vscale x 4 x float> [[ZDA:%.*]], <vscale x 8 x bfloat> [[ZN:%.*]], <vscale x 8 x bfloat> [[ZM:%.*]])
  73 // CPP-CHECK-NEXT:    ret <vscale x 4 x float> [[TMP0]]
  74 //
  75 svfloat32_t test_bfmlslt(svfloat32_t zda, svbfloat16_t zn, svbfloat16_t zm) ATTR
  76 {
  77   return SVE_ACLE_FUNC(svbfmlslt,_f32,,)(zda, zn, zm);
  78 }
  79
  80
  81 // CHECK-LABEL: @test_bfmlslt_lane(
  82 // CHECK-NEXT:  entry:
  83 // CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt.lane(<vscale x 4 x float> [[ZDA:%.*]], <vscale x 8 x bfloat> [[ZN:%.*]], <vscale x 8 x bfloat> [[ZM:%.*]], i32 7)
  84 // CHECK-NEXT:    ret <vscale x 4 x float> [[TMP0]]
  85 //
  86 // CPP-CHECK-LABEL: @_Z17test_bfmlslt_laneu13__SVFloat32_tu14__SVBfloat16_tS0_(
  87 // CPP-CHECK-NEXT:  entry:
  88 // CPP-CHECK-NEXT:    [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt.lane(<vscale x 4 x float> [[ZDA:%.*]], <vscale x 8 x bfloat> [[ZN:%.*]], <vscale x 8 x bfloat> [[ZM:%.*]], i32 7)
  89 // CPP-CHECK-NEXT:    ret <vscale x 4 x float> [[TMP0]]
  90 //
  91 svfloat32_t test_bfmlslt_lane(svfloat32_t zda, svbfloat16_t zn, svbfloat16_t zm) ATTR
  92 {
  93   return SVE_ACLE_FUNC(svbfmlslt_lane,_f32,,)(zda, zn, zm, 7);
  94 }