clang/test/CodeGen/X86/keylocker.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
   2 // RUN: %clang_cc1 %s -O0 -ffreestanding -triple=x86_64-unknown-unknown -target-feature +kl -target-feature +widekl -emit-llvm -o - -Wall -Werror | FileCheck %s -check-prefix=CHECK64
   3 // RUN: %clang_cc1 %s -O0 -ffreestanding -triple=i386-unknown-unknown -target-feature +kl -target-feature +widekl -emit-llvm -o - -Wall -Werror | FileCheck %s -check-prefix=CHECK32
   4
   5 #include <x86intrin.h>
   6
   7 // CHECK64-LABEL: @test_loadiwkey(
   8 // CHECK64-NEXT:  entry:
   9 // CHECK64-NEXT:    [[__CTL_ADDR_I:%.*]] = alloca i32, align 4
  10 // CHECK64-NEXT:    [[__INTKEY_ADDR_I:%.*]] = alloca <2 x i64>, align 16
  11 // CHECK64-NEXT:    [[__ENKEY_LO_ADDR_I:%.*]] = alloca <2 x i64>, align 16
  12 // CHECK64-NEXT:    [[__ENKEY_HI_ADDR_I:%.*]] = alloca <2 x i64>, align 16
  13 // CHECK64-NEXT:    [[CTL_ADDR:%.*]] = alloca i32, align 4
  14 // CHECK64-NEXT:    [[INTKEY_ADDR:%.*]] = alloca <2 x i64>, align 16
  15 // CHECK64-NEXT:    [[ENKEY_LO_ADDR:%.*]] = alloca <2 x i64>, align 16
  16 // CHECK64-NEXT:    [[ENKEY_HI_ADDR:%.*]] = alloca <2 x i64>, align 16
  17 // CHECK64-NEXT:    store i32 [[CTL:%.*]], ptr [[CTL_ADDR]], align 4
  18 // CHECK64-NEXT:    store <2 x i64> [[INTKEY:%.*]], ptr [[INTKEY_ADDR]], align 16
  19 // CHECK64-NEXT:    store <2 x i64> [[ENKEY_LO:%.*]], ptr [[ENKEY_LO_ADDR]], align 16
  20 // CHECK64-NEXT:    store <2 x i64> [[ENKEY_HI:%.*]], ptr [[ENKEY_HI_ADDR]], align 16
  21 // CHECK64-NEXT:    [[TMP0:%.*]] = load i32, ptr [[CTL_ADDR]], align 4
  22 // CHECK64-NEXT:    [[TMP1:%.*]] = load <2 x i64>, ptr [[INTKEY_ADDR]], align 16
  23 // CHECK64-NEXT:    [[TMP2:%.*]] = load <2 x i64>, ptr [[ENKEY_LO_ADDR]], align 16
  24 // CHECK64-NEXT:    [[TMP3:%.*]] = load <2 x i64>, ptr [[ENKEY_HI_ADDR]], align 16
  25 // CHECK64-NEXT:    store i32 [[TMP0]], ptr [[__CTL_ADDR_I]], align 4
  26 // CHECK64-NEXT:    store <2 x i64> [[TMP1]], ptr [[__INTKEY_ADDR_I]], align 16
  27 // CHECK64-NEXT:    store <2 x i64> [[TMP2]], ptr [[__ENKEY_LO_ADDR_I]], align 16
  28 // CHECK64-NEXT:    store <2 x i64> [[TMP3]], ptr [[__ENKEY_HI_ADDR_I]], align 16
  29 // CHECK64-NEXT:    [[TMP4:%.*]] = load <2 x i64>, ptr [[__INTKEY_ADDR_I]], align 16
  30 // CHECK64-NEXT:    [[TMP5:%.*]] = load <2 x i64>, ptr [[__ENKEY_LO_ADDR_I]], align 16
  31 // CHECK64-NEXT:    [[TMP6:%.*]] = load <2 x i64>, ptr [[__ENKEY_HI_ADDR_I]], align 16
  32 // CHECK64-NEXT:    [[TMP7:%.*]] = load i32, ptr [[__CTL_ADDR_I]], align 4
  33 // CHECK64-NEXT:    call void @llvm.x86.loadiwkey(<2 x i64> [[TMP4]], <2 x i64> [[TMP5]], <2 x i64> [[TMP6]], i32 [[TMP7]])
  34 // CHECK64-NEXT:    ret void
  35 //
  36 // CHECK32-LABEL: @test_loadiwkey(
  37 // CHECK32-NEXT:  entry:
  38 // CHECK32-NEXT:    [[__CTL_ADDR_I:%.*]] = alloca i32, align 4
  39 // CHECK32-NEXT:    [[__INTKEY_ADDR_I:%.*]] = alloca <2 x i64>, align 16
  40 // CHECK32-NEXT:    [[__ENKEY_LO_ADDR_I:%.*]] = alloca <2 x i64>, align 16
  41 // CHECK32-NEXT:    [[__ENKEY_HI_ADDR_I:%.*]] = alloca <2 x i64>, align 16
  42 // CHECK32-NEXT:    [[CTL_ADDR:%.*]] = alloca i32, align 4
  43 // CHECK32-NEXT:    [[INTKEY_ADDR:%.*]] = alloca <2 x i64>, align 16
  44 // CHECK32-NEXT:    [[ENKEY_LO_ADDR:%.*]] = alloca <2 x i64>, align 16
  45 // CHECK32-NEXT:    [[ENKEY_HI_ADDR:%.*]] = alloca <2 x i64>, align 16
  46 // CHECK32-NEXT:    store i32 [[CTL:%.*]], ptr [[CTL_ADDR]], align 4
  47 // CHECK32-NEXT:    store <2 x i64> [[INTKEY:%.*]], ptr [[INTKEY_ADDR]], align 16
  48 // CHECK32-NEXT:    store <2 x i64> [[ENKEY_LO:%.*]], ptr [[ENKEY_LO_ADDR]], align 16
  49 // CHECK32-NEXT:    store <2 x i64> [[ENKEY_HI:%.*]], ptr [[ENKEY_HI_ADDR]], align 16
  50 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, ptr [[CTL_ADDR]], align 4
  51 // CHECK32-NEXT:    [[TMP1:%.*]] = load <2 x i64>, ptr [[INTKEY_ADDR]], align 16
  52 // CHECK32-NEXT:    [[TMP2:%.*]] = load <2 x i64>, ptr [[ENKEY_LO_ADDR]], align 16
  53 // CHECK32-NEXT:    [[TMP3:%.*]] = load <2 x i64>, ptr [[ENKEY_HI_ADDR]], align 16
  54 // CHECK32-NEXT:    store i32 [[TMP0]], ptr [[__CTL_ADDR_I]], align 4
  55 // CHECK32-NEXT:    store <2 x i64> [[TMP1]], ptr [[__INTKEY_ADDR_I]], align 16
  56 // CHECK32-NEXT:    store <2 x i64> [[TMP2]], ptr [[__ENKEY_LO_ADDR_I]], align 16
  57 // CHECK32-NEXT:    store <2 x i64> [[TMP3]], ptr [[__ENKEY_HI_ADDR_I]], align 16
  58 // CHECK32-NEXT:    [[TMP4:%.*]] = load <2 x i64>, ptr [[__INTKEY_ADDR_I]], align 16
  59 // CHECK32-NEXT:    [[TMP5:%.*]] = load <2 x i64>, ptr [[__ENKEY_LO_ADDR_I]], align 16
  60 // CHECK32-NEXT:    [[TMP6:%.*]] = load <2 x i64>, ptr [[__ENKEY_HI_ADDR_I]], align 16
  61 // CHECK32-NEXT:    [[TMP7:%.*]] = load i32, ptr [[__CTL_ADDR_I]], align 4
  62 // CHECK32-NEXT:    call void @llvm.x86.loadiwkey(<2 x i64> [[TMP4]], <2 x i64> [[TMP5]], <2 x i64> [[TMP6]], i32 [[TMP7]])
  63 // CHECK32-NEXT:    ret void
  64 //
  65 void test_loadiwkey(unsigned int ctl, __m128i intkey, __m128i enkey_lo, __m128i enkey_hi) {
  66   _mm_loadiwkey(ctl, intkey, enkey_lo, enkey_hi);
  67 }
  68
  69 // CHECK64-LABEL: @test_encodekey128_u32(
  70 // CHECK64-NEXT:  entry:
  71 // CHECK64-NEXT:    [[__HTYPE_ADDR_I:%.*]] = alloca i32, align 4
  72 // CHECK64-NEXT:    [[__KEY_ADDR_I:%.*]] = alloca <2 x i64>, align 16
  73 // CHECK64-NEXT:    [[__H_ADDR_I:%.*]] = alloca ptr, align 8
  74 // CHECK64-NEXT:    [[HTYPE_ADDR:%.*]] = alloca i32, align 4
  75 // CHECK64-NEXT:    [[KEY_ADDR:%.*]] = alloca <2 x i64>, align 16
  76 // CHECK64-NEXT:    [[H_ADDR:%.*]] = alloca ptr, align 8
  77 // CHECK64-NEXT:    store i32 [[HTYPE:%.*]], ptr [[HTYPE_ADDR]], align 4
  78 // CHECK64-NEXT:    store <2 x i64> [[KEY:%.*]], ptr [[KEY_ADDR]], align 16
  79 // CHECK64-NEXT:    store ptr [[H:%.*]], ptr [[H_ADDR]], align 8
  80 // CHECK64-NEXT:    [[TMP0:%.*]] = load i32, ptr [[HTYPE_ADDR]], align 4
  81 // CHECK64-NEXT:    [[TMP1:%.*]] = load <2 x i64>, ptr [[KEY_ADDR]], align 16
  82 // CHECK64-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[H_ADDR]], align 8
  83 // CHECK64-NEXT:    store i32 [[TMP0]], ptr [[__HTYPE_ADDR_I]], align 4
  84 // CHECK64-NEXT:    store <2 x i64> [[TMP1]], ptr [[__KEY_ADDR_I]], align 16
  85 // CHECK64-NEXT:    store ptr [[TMP2]], ptr [[__H_ADDR_I]], align 8
  86 // CHECK64-NEXT:    [[TMP3:%.*]] = load i32, ptr [[__HTYPE_ADDR_I]], align 4
  87 // CHECK64-NEXT:    [[TMP4:%.*]] = load <2 x i64>, ptr [[__KEY_ADDR_I]], align 16
  88 // CHECK64-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[__H_ADDR_I]], align 8
  89 // CHECK64-NEXT:    [[TMP6:%.*]] = call { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.encodekey128(i32 [[TMP3]], <2 x i64> [[TMP4]])
  90 // CHECK64-NEXT:    [[TMP7:%.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP6]], 1
  91 // CHECK64-NEXT:    store <2 x i64> [[TMP7]], ptr [[TMP5]], align 1
  92 // CHECK64-NEXT:    [[TMP9:%.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP6]], 2
  93 // CHECK64-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr [[TMP5]], i32 16
  94 // CHECK64-NEXT:    store <2 x i64> [[TMP9]], ptr [[TMP10]], align 1
  95 // CHECK64-NEXT:    [[TMP12:%.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP6]], 3
  96 // CHECK64-NEXT:    [[TMP13:%.*]] = getelementptr i8, ptr [[TMP5]], i32 32
  97 // CHECK64-NEXT:    store <2 x i64> [[TMP12]], ptr [[TMP13]], align 1
  98 // CHECK64-NEXT:    [[TMP15:%.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP6]], 0
  99 // CHECK64-NEXT:    ret i32 [[TMP15]]
 100 //
 101 // CHECK32-LABEL: @test_encodekey128_u32(
 102 // CHECK32-NEXT:  entry:
 103 // CHECK32-NEXT:    [[__HTYPE_ADDR_I:%.*]] = alloca i32, align 4
 104 // CHECK32-NEXT:    [[__KEY_ADDR_I:%.*]] = alloca <2 x i64>, align 16
 105 // CHECK32-NEXT:    [[__H_ADDR_I:%.*]] = alloca ptr, align 4
 106 // CHECK32-NEXT:    [[HTYPE_ADDR:%.*]] = alloca i32, align 4
 107 // CHECK32-NEXT:    [[KEY_ADDR:%.*]] = alloca <2 x i64>, align 16
 108 // CHECK32-NEXT:    [[H_ADDR:%.*]] = alloca ptr, align 4
 109 // CHECK32-NEXT:    store i32 [[HTYPE:%.*]], ptr [[HTYPE_ADDR]], align 4
 110 // CHECK32-NEXT:    store <2 x i64> [[KEY:%.*]], ptr [[KEY_ADDR]], align 16
 111 // CHECK32-NEXT:    store ptr [[H:%.*]], ptr [[H_ADDR]], align 4
 112 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, ptr [[HTYPE_ADDR]], align 4
 113 // CHECK32-NEXT:    [[TMP1:%.*]] = load <2 x i64>, ptr [[KEY_ADDR]], align 16
 114 // CHECK32-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[H_ADDR]], align 4
 115 // CHECK32-NEXT:    store i32 [[TMP0]], ptr [[__HTYPE_ADDR_I]], align 4
 116 // CHECK32-NEXT:    store <2 x i64> [[TMP1]], ptr [[__KEY_ADDR_I]], align 16
 117 // CHECK32-NEXT:    store ptr [[TMP2]], ptr [[__H_ADDR_I]], align 4
 118 // CHECK32-NEXT:    [[TMP3:%.*]] = load i32, ptr [[__HTYPE_ADDR_I]], align 4
 119 // CHECK32-NEXT:    [[TMP4:%.*]] = load <2 x i64>, ptr [[__KEY_ADDR_I]], align 16
 120 // CHECK32-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[__H_ADDR_I]], align 4
 121 // CHECK32-NEXT:    [[TMP6:%.*]] = call { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.encodekey128(i32 [[TMP3]], <2 x i64> [[TMP4]])
 122 // CHECK32-NEXT:    [[TMP7:%.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP6]], 1
 123 // CHECK32-NEXT:    store <2 x i64> [[TMP7]], ptr [[TMP5]], align 1
 124 // CHECK32-NEXT:    [[TMP9:%.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP6]], 2
 125 // CHECK32-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr [[TMP5]], i32 16
 126 // CHECK32-NEXT:    store <2 x i64> [[TMP9]], ptr [[TMP10]], align 1
 127 // CHECK32-NEXT:    [[TMP12:%.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP6]], 3
 128 // CHECK32-NEXT:    [[TMP13:%.*]] = getelementptr i8, ptr [[TMP5]], i32 32
 129 // CHECK32-NEXT:    store <2 x i64> [[TMP12]], ptr [[TMP13]], align 1
 130 // CHECK32-NEXT:    [[TMP15:%.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP6]], 0
 131 // CHECK32-NEXT:    ret i32 [[TMP15]]
 132 //
 133 unsigned int test_encodekey128_u32(unsigned int htype, __m128i key, void *h) {
 134   return _mm_encodekey128_u32(htype, key, h);
 135 }
 136
 137 // CHECK64-LABEL: @test_encodekey256_u32(
 138 // CHECK64-NEXT:  entry:
 139 // CHECK64-NEXT:    [[__HTYPE_ADDR_I:%.*]] = alloca i32, align 4
 140 // CHECK64-NEXT:    [[__KEY_LO_ADDR_I:%.*]] = alloca <2 x i64>, align 16
 141 // CHECK64-NEXT:    [[__KEY_HI_ADDR_I:%.*]] = alloca <2 x i64>, align 16
 142 // CHECK64-NEXT:    [[__H_ADDR_I:%.*]] = alloca ptr, align 8
 143 // CHECK64-NEXT:    [[HTYPE_ADDR:%.*]] = alloca i32, align 4
 144 // CHECK64-NEXT:    [[KEY_LO_ADDR:%.*]] = alloca <2 x i64>, align 16
 145 // CHECK64-NEXT:    [[KEY_HI_ADDR:%.*]] = alloca <2 x i64>, align 16
 146 // CHECK64-NEXT:    [[H_ADDR:%.*]] = alloca ptr, align 8
 147 // CHECK64-NEXT:    store i32 [[HTYPE:%.*]], ptr [[HTYPE_ADDR]], align 4
 148 // CHECK64-NEXT:    store <2 x i64> [[KEY_LO:%.*]], ptr [[KEY_LO_ADDR]], align 16
 149 // CHECK64-NEXT:    store <2 x i64> [[KEY_HI:%.*]], ptr [[KEY_HI_ADDR]], align 16
 150 // CHECK64-NEXT:    store ptr [[H:%.*]], ptr [[H_ADDR]], align 8
 151 // CHECK64-NEXT:    [[TMP0:%.*]] = load i32, ptr [[HTYPE_ADDR]], align 4
 152 // CHECK64-NEXT:    [[TMP1:%.*]] = load <2 x i64>, ptr [[KEY_LO_ADDR]], align 16
 153 // CHECK64-NEXT:    [[TMP2:%.*]] = load <2 x i64>, ptr [[KEY_HI_ADDR]], align 16
 154 // CHECK64-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[H_ADDR]], align 8
 155 // CHECK64-NEXT:    store i32 [[TMP0]], ptr [[__HTYPE_ADDR_I]], align 4
 156 // CHECK64-NEXT:    store <2 x i64> [[TMP1]], ptr [[__KEY_LO_ADDR_I]], align 16
 157 // CHECK64-NEXT:    store <2 x i64> [[TMP2]], ptr [[__KEY_HI_ADDR_I]], align 16
 158 // CHECK64-NEXT:    store ptr [[TMP3]], ptr [[__H_ADDR_I]], align 8
 159 // CHECK64-NEXT:    [[TMP4:%.*]] = load i32, ptr [[__HTYPE_ADDR_I]], align 4
 160 // CHECK64-NEXT:    [[TMP5:%.*]] = load <2 x i64>, ptr [[__KEY_LO_ADDR_I]], align 16
 161 // CHECK64-NEXT:    [[TMP6:%.*]] = load <2 x i64>, ptr [[__KEY_HI_ADDR_I]], align 16
 162 // CHECK64-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[__H_ADDR_I]], align 8
 163 // CHECK64-NEXT:    [[TMP8:%.*]] = call { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.encodekey256(i32 [[TMP4]], <2 x i64> [[TMP5]], <2 x i64> [[TMP6]])
 164 // CHECK64-NEXT:    [[TMP9:%.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP8]], 1
 165 // CHECK64-NEXT:    store <2 x i64> [[TMP9]], ptr [[TMP7]], align 1
 166 // CHECK64-NEXT:    [[TMP11:%.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP8]], 2
 167 // CHECK64-NEXT:    [[TMP12:%.*]] = getelementptr i8, ptr [[TMP7]], i32 16
 168 // CHECK64-NEXT:    store <2 x i64> [[TMP11]], ptr [[TMP12]], align 1
 169 // CHECK64-NEXT:    [[TMP14:%.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP8]], 3
 170 // CHECK64-NEXT:    [[TMP15:%.*]] = getelementptr i8, ptr [[TMP7]], i32 32
 171 // CHECK64-NEXT:    store <2 x i64> [[TMP14]], ptr [[TMP15]], align 1
 172 // CHECK64-NEXT:    [[TMP17:%.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP8]], 4
 173 // CHECK64-NEXT:    [[TMP18:%.*]] = getelementptr i8, ptr [[TMP7]], i32 48
 174 // CHECK64-NEXT:    store <2 x i64> [[TMP17]], ptr [[TMP18]], align 1
 175 // CHECK64-NEXT:    [[TMP20:%.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP8]], 0
 176 // CHECK64-NEXT:    ret i32 [[TMP20]]
 177 //
 178 // CHECK32-LABEL: @test_encodekey256_u32(
 179 // CHECK32-NEXT:  entry:
 180 // CHECK32-NEXT:    [[__HTYPE_ADDR_I:%.*]] = alloca i32, align 4
 181 // CHECK32-NEXT:    [[__KEY_LO_ADDR_I:%.*]] = alloca <2 x i64>, align 16
 182 // CHECK32-NEXT:    [[__KEY_HI_ADDR_I:%.*]] = alloca <2 x i64>, align 16
 183 // CHECK32-NEXT:    [[__H_ADDR_I:%.*]] = alloca ptr, align 4
 184 // CHECK32-NEXT:    [[HTYPE_ADDR:%.*]] = alloca i32, align 4
 185 // CHECK32-NEXT:    [[KEY_LO_ADDR:%.*]] = alloca <2 x i64>, align 16
 186 // CHECK32-NEXT:    [[KEY_HI_ADDR:%.*]] = alloca <2 x i64>, align 16
 187 // CHECK32-NEXT:    [[H_ADDR:%.*]] = alloca ptr, align 4
 188 // CHECK32-NEXT:    store i32 [[HTYPE:%.*]], ptr [[HTYPE_ADDR]], align 4
 189 // CHECK32-NEXT:    store <2 x i64> [[KEY_LO:%.*]], ptr [[KEY_LO_ADDR]], align 16
 190 // CHECK32-NEXT:    store <2 x i64> [[KEY_HI:%.*]], ptr [[KEY_HI_ADDR]], align 16
 191 // CHECK32-NEXT:    store ptr [[H:%.*]], ptr [[H_ADDR]], align 4
 192 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, ptr [[HTYPE_ADDR]], align 4
 193 // CHECK32-NEXT:    [[TMP1:%.*]] = load <2 x i64>, ptr [[KEY_LO_ADDR]], align 16
 194 // CHECK32-NEXT:    [[TMP2:%.*]] = load <2 x i64>, ptr [[KEY_HI_ADDR]], align 16
 195 // CHECK32-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[H_ADDR]], align 4
 196 // CHECK32-NEXT:    store i32 [[TMP0]], ptr [[__HTYPE_ADDR_I]], align 4
 197 // CHECK32-NEXT:    store <2 x i64> [[TMP1]], ptr [[__KEY_LO_ADDR_I]], align 16
 198 // CHECK32-NEXT:    store <2 x i64> [[TMP2]], ptr [[__KEY_HI_ADDR_I]], align 16
 199 // CHECK32-NEXT:    store ptr [[TMP3]], ptr [[__H_ADDR_I]], align 4
 200 // CHECK32-NEXT:    [[TMP4:%.*]] = load i32, ptr [[__HTYPE_ADDR_I]], align 4
 201 // CHECK32-NEXT:    [[TMP5:%.*]] = load <2 x i64>, ptr [[__KEY_LO_ADDR_I]], align 16
 202 // CHECK32-NEXT:    [[TMP6:%.*]] = load <2 x i64>, ptr [[__KEY_HI_ADDR_I]], align 16
 203 // CHECK32-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[__H_ADDR_I]], align 4
 204 // CHECK32-NEXT:    [[TMP8:%.*]] = call { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.encodekey256(i32 [[TMP4]], <2 x i64> [[TMP5]], <2 x i64> [[TMP6]])
 205 // CHECK32-NEXT:    [[TMP9:%.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP8]], 1
 206 // CHECK32-NEXT:    store <2 x i64> [[TMP9]], ptr [[TMP7]], align 1
 207 // CHECK32-NEXT:    [[TMP11:%.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP8]], 2
 208 // CHECK32-NEXT:    [[TMP12:%.*]] = getelementptr i8, ptr [[TMP7]], i32 16
 209 // CHECK32-NEXT:    store <2 x i64> [[TMP11]], ptr [[TMP12]], align 1
 210 // CHECK32-NEXT:    [[TMP14:%.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP8]], 3
 211 // CHECK32-NEXT:    [[TMP15:%.*]] = getelementptr i8, ptr [[TMP7]], i32 32
 212 // CHECK32-NEXT:    store <2 x i64> [[TMP14]], ptr [[TMP15]], align 1
 213 // CHECK32-NEXT:    [[TMP17:%.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP8]], 4
 214 // CHECK32-NEXT:    [[TMP18:%.*]] = getelementptr i8, ptr [[TMP7]], i32 48
 215 // CHECK32-NEXT:    store <2 x i64> [[TMP17]], ptr [[TMP18]], align 1
 216 // CHECK32-NEXT:    [[TMP20:%.*]] = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP8]], 0
 217 // CHECK32-NEXT:    ret i32 [[TMP20]]
 218 //
 219 unsigned int test_encodekey256_u32(unsigned int htype, __m128i key_lo, __m128i key_hi, void *h) {
 220   return _mm_encodekey256_u32(htype, key_lo, key_hi, h);
 221 }
 222
 223 // CHECK64-LABEL: @test_mm_aesenc256kl_u8(
 224 // CHECK64-NEXT:  entry:
 225 // CHECK64-NEXT:    [[__ODATA_ADDR_I:%.*]] = alloca ptr, align 8
 226 // CHECK64-NEXT:    [[__IDATA_ADDR_I:%.*]] = alloca <2 x i64>, align 16
 227 // CHECK64-NEXT:    [[__H_ADDR_I:%.*]] = alloca ptr, align 8
 228 // CHECK64-NEXT:    [[ODATA_ADDR:%.*]] = alloca ptr, align 8
 229 // CHECK64-NEXT:    [[IDATA_ADDR:%.*]] = alloca <2 x i64>, align 16
 230 // CHECK64-NEXT:    [[H_ADDR:%.*]] = alloca ptr, align 8
 231 // CHECK64-NEXT:    store ptr [[ODATA:%.*]], ptr [[ODATA_ADDR]], align 8
 232 // CHECK64-NEXT:    store <2 x i64> [[IDATA:%.*]], ptr [[IDATA_ADDR]], align 16
 233 // CHECK64-NEXT:    store ptr [[H:%.*]], ptr [[H_ADDR]], align 8
 234 // CHECK64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[ODATA_ADDR]], align 8
 235 // CHECK64-NEXT:    [[TMP1:%.*]] = load <2 x i64>, ptr [[IDATA_ADDR]], align 16
 236 // CHECK64-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[H_ADDR]], align 8
 237 // CHECK64-NEXT:    store ptr [[TMP0]], ptr [[__ODATA_ADDR_I]], align 8
 238 // CHECK64-NEXT:    store <2 x i64> [[TMP1]], ptr [[__IDATA_ADDR_I]], align 16
 239 // CHECK64-NEXT:    store ptr [[TMP2]], ptr [[__H_ADDR_I]], align 8
 240 // CHECK64-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[__ODATA_ADDR_I]], align 8
 241 // CHECK64-NEXT:    [[TMP4:%.*]] = load <2 x i64>, ptr [[__IDATA_ADDR_I]], align 16
 242 // CHECK64-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[__H_ADDR_I]], align 8
 243 // CHECK64-NEXT:    [[TMP6:%.*]] = call { i8, <2 x i64> } @llvm.x86.aesenc256kl(<2 x i64> [[TMP4]], ptr [[TMP5]])
 244 // CHECK64-NEXT:    [[TMP7:%.*]] = extractvalue { i8, <2 x i64> } [[TMP6]], 0
 245 // CHECK64-NEXT:    [[TMP8:%.*]] = trunc i8 [[TMP7]] to i1
 246 // CHECK64-NEXT:    [[TMP9:%.*]] = extractvalue { i8, <2 x i64> } [[TMP6]], 1
 247 // CHECK64-NEXT:    br i1 [[TMP8]], label [[AESENC256KL_NO_ERROR_I:%.*]], label [[AESENC256KL_ERROR_I:%.*]]
 248 // CHECK64:       aesenc256kl_no_error.i:
 249 // CHECK64-NEXT:    store <2 x i64> [[TMP9]], ptr [[TMP3]], align 16
 250 // CHECK64-NEXT:    br label [[_MM_AESENC256KL_U8_EXIT:%.*]]
 251 // CHECK64:       aesenc256kl_error.i:
 252 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP3]], align 16
 253 // CHECK64-NEXT:    br label [[_MM_AESENC256KL_U8_EXIT]]
 254 // CHECK64:       _mm_aesenc256kl_u8.exit:
 255 // CHECK64-NEXT:    [[TMP10:%.*]] = extractvalue { i8, <2 x i64> } [[TMP6]], 0
 256 // CHECK64-NEXT:    ret i8 [[TMP10]]
 257 //
 258 // CHECK32-LABEL: @test_mm_aesenc256kl_u8(
 259 // CHECK32-NEXT:  entry:
 260 // CHECK32-NEXT:    [[__ODATA_ADDR_I:%.*]] = alloca ptr, align 4
 261 // CHECK32-NEXT:    [[__IDATA_ADDR_I:%.*]] = alloca <2 x i64>, align 16
 262 // CHECK32-NEXT:    [[__H_ADDR_I:%.*]] = alloca ptr, align 4
 263 // CHECK32-NEXT:    [[ODATA_ADDR:%.*]] = alloca ptr, align 4
 264 // CHECK32-NEXT:    [[IDATA_ADDR:%.*]] = alloca <2 x i64>, align 16
 265 // CHECK32-NEXT:    [[H_ADDR:%.*]] = alloca ptr, align 4
 266 // CHECK32-NEXT:    store ptr [[ODATA:%.*]], ptr [[ODATA_ADDR]], align 4
 267 // CHECK32-NEXT:    store <2 x i64> [[IDATA:%.*]], ptr [[IDATA_ADDR]], align 16
 268 // CHECK32-NEXT:    store ptr [[H:%.*]], ptr [[H_ADDR]], align 4
 269 // CHECK32-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[ODATA_ADDR]], align 4
 270 // CHECK32-NEXT:    [[TMP1:%.*]] = load <2 x i64>, ptr [[IDATA_ADDR]], align 16
 271 // CHECK32-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[H_ADDR]], align 4
 272 // CHECK32-NEXT:    store ptr [[TMP0]], ptr [[__ODATA_ADDR_I]], align 4
 273 // CHECK32-NEXT:    store <2 x i64> [[TMP1]], ptr [[__IDATA_ADDR_I]], align 16
 274 // CHECK32-NEXT:    store ptr [[TMP2]], ptr [[__H_ADDR_I]], align 4
 275 // CHECK32-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[__ODATA_ADDR_I]], align 4
 276 // CHECK32-NEXT:    [[TMP4:%.*]] = load <2 x i64>, ptr [[__IDATA_ADDR_I]], align 16
 277 // CHECK32-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[__H_ADDR_I]], align 4
 278 // CHECK32-NEXT:    [[TMP6:%.*]] = call { i8, <2 x i64> } @llvm.x86.aesenc256kl(<2 x i64> [[TMP4]], ptr [[TMP5]])
 279 // CHECK32-NEXT:    [[TMP7:%.*]] = extractvalue { i8, <2 x i64> } [[TMP6]], 0
 280 // CHECK32-NEXT:    [[TMP8:%.*]] = trunc i8 [[TMP7]] to i1
 281 // CHECK32-NEXT:    [[TMP9:%.*]] = extractvalue { i8, <2 x i64> } [[TMP6]], 1
 282 // CHECK32-NEXT:    br i1 [[TMP8]], label [[AESENC256KL_NO_ERROR_I:%.*]], label [[AESENC256KL_ERROR_I:%.*]]
 283 // CHECK32:       aesenc256kl_no_error.i:
 284 // CHECK32-NEXT:    store <2 x i64> [[TMP9]], ptr [[TMP3]], align 16
 285 // CHECK32-NEXT:    br label [[_MM_AESENC256KL_U8_EXIT:%.*]]
 286 // CHECK32:       aesenc256kl_error.i:
 287 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP3]], align 16
 288 // CHECK32-NEXT:    br label [[_MM_AESENC256KL_U8_EXIT]]
 289 // CHECK32:       _mm_aesenc256kl_u8.exit:
 290 // CHECK32-NEXT:    [[TMP10:%.*]] = extractvalue { i8, <2 x i64> } [[TMP6]], 0
 291 // CHECK32-NEXT:    ret i8 [[TMP10]]
 292 //
 293 unsigned char test_mm_aesenc256kl_u8(__m128i *odata, __m128i idata, const void *h) {
 294   return _mm_aesenc256kl_u8(odata, idata, h);
 295 }
 296
 297 // CHECK64-LABEL: @test_mm_aesdec256kl_u8(
 298 // CHECK64-NEXT:  entry:
 299 // CHECK64-NEXT:    [[__ODATA_ADDR_I:%.*]] = alloca ptr, align 8
 300 // CHECK64-NEXT:    [[__IDATA_ADDR_I:%.*]] = alloca <2 x i64>, align 16
 301 // CHECK64-NEXT:    [[__H_ADDR_I:%.*]] = alloca ptr, align 8
 302 // CHECK64-NEXT:    [[ODATA_ADDR:%.*]] = alloca ptr, align 8
 303 // CHECK64-NEXT:    [[IDATA_ADDR:%.*]] = alloca <2 x i64>, align 16
 304 // CHECK64-NEXT:    [[H_ADDR:%.*]] = alloca ptr, align 8
 305 // CHECK64-NEXT:    store ptr [[ODATA:%.*]], ptr [[ODATA_ADDR]], align 8
 306 // CHECK64-NEXT:    store <2 x i64> [[IDATA:%.*]], ptr [[IDATA_ADDR]], align 16
 307 // CHECK64-NEXT:    store ptr [[H:%.*]], ptr [[H_ADDR]], align 8
 308 // CHECK64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[ODATA_ADDR]], align 8
 309 // CHECK64-NEXT:    [[TMP1:%.*]] = load <2 x i64>, ptr [[IDATA_ADDR]], align 16
 310 // CHECK64-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[H_ADDR]], align 8
 311 // CHECK64-NEXT:    store ptr [[TMP0]], ptr [[__ODATA_ADDR_I]], align 8
 312 // CHECK64-NEXT:    store <2 x i64> [[TMP1]], ptr [[__IDATA_ADDR_I]], align 16
 313 // CHECK64-NEXT:    store ptr [[TMP2]], ptr [[__H_ADDR_I]], align 8
 314 // CHECK64-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[__ODATA_ADDR_I]], align 8
 315 // CHECK64-NEXT:    [[TMP4:%.*]] = load <2 x i64>, ptr [[__IDATA_ADDR_I]], align 16
 316 // CHECK64-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[__H_ADDR_I]], align 8
 317 // CHECK64-NEXT:    [[TMP6:%.*]] = call { i8, <2 x i64> } @llvm.x86.aesdec256kl(<2 x i64> [[TMP4]], ptr [[TMP5]])
 318 // CHECK64-NEXT:    [[TMP7:%.*]] = extractvalue { i8, <2 x i64> } [[TMP6]], 0
 319 // CHECK64-NEXT:    [[TMP8:%.*]] = trunc i8 [[TMP7]] to i1
 320 // CHECK64-NEXT:    [[TMP9:%.*]] = extractvalue { i8, <2 x i64> } [[TMP6]], 1
 321 // CHECK64-NEXT:    br i1 [[TMP8]], label [[AESDEC256KL_NO_ERROR_I:%.*]], label [[AESDEC256KL_ERROR_I:%.*]]
 322 // CHECK64:       aesdec256kl_no_error.i:
 323 // CHECK64-NEXT:    store <2 x i64> [[TMP9]], ptr [[TMP3]], align 16
 324 // CHECK64-NEXT:    br label [[_MM_AESDEC256KL_U8_EXIT:%.*]]
 325 // CHECK64:       aesdec256kl_error.i:
 326 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP3]], align 16
 327 // CHECK64-NEXT:    br label [[_MM_AESDEC256KL_U8_EXIT]]
 328 // CHECK64:       _mm_aesdec256kl_u8.exit:
 329 // CHECK64-NEXT:    [[TMP10:%.*]] = extractvalue { i8, <2 x i64> } [[TMP6]], 0
 330 // CHECK64-NEXT:    ret i8 [[TMP10]]
 331 //
 332 // CHECK32-LABEL: @test_mm_aesdec256kl_u8(
 333 // CHECK32-NEXT:  entry:
 334 // CHECK32-NEXT:    [[__ODATA_ADDR_I:%.*]] = alloca ptr, align 4
 335 // CHECK32-NEXT:    [[__IDATA_ADDR_I:%.*]] = alloca <2 x i64>, align 16
 336 // CHECK32-NEXT:    [[__H_ADDR_I:%.*]] = alloca ptr, align 4
 337 // CHECK32-NEXT:    [[ODATA_ADDR:%.*]] = alloca ptr, align 4
 338 // CHECK32-NEXT:    [[IDATA_ADDR:%.*]] = alloca <2 x i64>, align 16
 339 // CHECK32-NEXT:    [[H_ADDR:%.*]] = alloca ptr, align 4
 340 // CHECK32-NEXT:    store ptr [[ODATA:%.*]], ptr [[ODATA_ADDR]], align 4
 341 // CHECK32-NEXT:    store <2 x i64> [[IDATA:%.*]], ptr [[IDATA_ADDR]], align 16
 342 // CHECK32-NEXT:    store ptr [[H:%.*]], ptr [[H_ADDR]], align 4
 343 // CHECK32-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[ODATA_ADDR]], align 4
 344 // CHECK32-NEXT:    [[TMP1:%.*]] = load <2 x i64>, ptr [[IDATA_ADDR]], align 16
 345 // CHECK32-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[H_ADDR]], align 4
 346 // CHECK32-NEXT:    store ptr [[TMP0]], ptr [[__ODATA_ADDR_I]], align 4
 347 // CHECK32-NEXT:    store <2 x i64> [[TMP1]], ptr [[__IDATA_ADDR_I]], align 16
 348 // CHECK32-NEXT:    store ptr [[TMP2]], ptr [[__H_ADDR_I]], align 4
 349 // CHECK32-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[__ODATA_ADDR_I]], align 4
 350 // CHECK32-NEXT:    [[TMP4:%.*]] = load <2 x i64>, ptr [[__IDATA_ADDR_I]], align 16
 351 // CHECK32-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[__H_ADDR_I]], align 4
 352 // CHECK32-NEXT:    [[TMP6:%.*]] = call { i8, <2 x i64> } @llvm.x86.aesdec256kl(<2 x i64> [[TMP4]], ptr [[TMP5]])
 353 // CHECK32-NEXT:    [[TMP7:%.*]] = extractvalue { i8, <2 x i64> } [[TMP6]], 0
 354 // CHECK32-NEXT:    [[TMP8:%.*]] = trunc i8 [[TMP7]] to i1
 355 // CHECK32-NEXT:    [[TMP9:%.*]] = extractvalue { i8, <2 x i64> } [[TMP6]], 1
 356 // CHECK32-NEXT:    br i1 [[TMP8]], label [[AESDEC256KL_NO_ERROR_I:%.*]], label [[AESDEC256KL_ERROR_I:%.*]]
 357 // CHECK32:       aesdec256kl_no_error.i:
 358 // CHECK32-NEXT:    store <2 x i64> [[TMP9]], ptr [[TMP3]], align 16
 359 // CHECK32-NEXT:    br label [[_MM_AESDEC256KL_U8_EXIT:%.*]]
 360 // CHECK32:       aesdec256kl_error.i:
 361 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP3]], align 16
 362 // CHECK32-NEXT:    br label [[_MM_AESDEC256KL_U8_EXIT]]
 363 // CHECK32:       _mm_aesdec256kl_u8.exit:
 364 // CHECK32-NEXT:    [[TMP10:%.*]] = extractvalue { i8, <2 x i64> } [[TMP6]], 0
 365 // CHECK32-NEXT:    ret i8 [[TMP10]]
 366 //
 367 unsigned char test_mm_aesdec256kl_u8(__m128i *odata, __m128i idata, const void *h) {
 368   return _mm_aesdec256kl_u8(odata, idata, h);
 369 }
 370
 371 // CHECK64-LABEL: @test_mm_aesenc128kl_u8(
 372 // CHECK64-NEXT:  entry:
 373 // CHECK64-NEXT:    [[__ODATA_ADDR_I:%.*]] = alloca ptr, align 8
 374 // CHECK64-NEXT:    [[__IDATA_ADDR_I:%.*]] = alloca <2 x i64>, align 16
 375 // CHECK64-NEXT:    [[__H_ADDR_I:%.*]] = alloca ptr, align 8
 376 // CHECK64-NEXT:    [[ODATA_ADDR:%.*]] = alloca ptr, align 8
 377 // CHECK64-NEXT:    [[IDATA_ADDR:%.*]] = alloca <2 x i64>, align 16
 378 // CHECK64-NEXT:    [[H_ADDR:%.*]] = alloca ptr, align 8
 379 // CHECK64-NEXT:    store ptr [[ODATA:%.*]], ptr [[ODATA_ADDR]], align 8
 380 // CHECK64-NEXT:    store <2 x i64> [[IDATA:%.*]], ptr [[IDATA_ADDR]], align 16
 381 // CHECK64-NEXT:    store ptr [[H:%.*]], ptr [[H_ADDR]], align 8
 382 // CHECK64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[ODATA_ADDR]], align 8
 383 // CHECK64-NEXT:    [[TMP1:%.*]] = load <2 x i64>, ptr [[IDATA_ADDR]], align 16
 384 // CHECK64-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[H_ADDR]], align 8
 385 // CHECK64-NEXT:    store ptr [[TMP0]], ptr [[__ODATA_ADDR_I]], align 8
 386 // CHECK64-NEXT:    store <2 x i64> [[TMP1]], ptr [[__IDATA_ADDR_I]], align 16
 387 // CHECK64-NEXT:    store ptr [[TMP2]], ptr [[__H_ADDR_I]], align 8
 388 // CHECK64-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[__ODATA_ADDR_I]], align 8
 389 // CHECK64-NEXT:    [[TMP4:%.*]] = load <2 x i64>, ptr [[__IDATA_ADDR_I]], align 16
 390 // CHECK64-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[__H_ADDR_I]], align 8
 391 // CHECK64-NEXT:    [[TMP6:%.*]] = call { i8, <2 x i64> } @llvm.x86.aesenc128kl(<2 x i64> [[TMP4]], ptr [[TMP5]])
 392 // CHECK64-NEXT:    [[TMP7:%.*]] = extractvalue { i8, <2 x i64> } [[TMP6]], 0
 393 // CHECK64-NEXT:    [[TMP8:%.*]] = trunc i8 [[TMP7]] to i1
 394 // CHECK64-NEXT:    [[TMP9:%.*]] = extractvalue { i8, <2 x i64> } [[TMP6]], 1
 395 // CHECK64-NEXT:    br i1 [[TMP8]], label [[AESENC128KL_NO_ERROR_I:%.*]], label [[AESENC128KL_ERROR_I:%.*]]
 396 // CHECK64:       aesenc128kl_no_error.i:
 397 // CHECK64-NEXT:    store <2 x i64> [[TMP9]], ptr [[TMP3]], align 16
 398 // CHECK64-NEXT:    br label [[_MM_AESENC128KL_U8_EXIT:%.*]]
 399 // CHECK64:       aesenc128kl_error.i:
 400 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP3]], align 16
 401 // CHECK64-NEXT:    br label [[_MM_AESENC128KL_U8_EXIT]]
 402 // CHECK64:       _mm_aesenc128kl_u8.exit:
 403 // CHECK64-NEXT:    [[TMP10:%.*]] = extractvalue { i8, <2 x i64> } [[TMP6]], 0
 404 // CHECK64-NEXT:    ret i8 [[TMP10]]
 405 //
 406 // CHECK32-LABEL: @test_mm_aesenc128kl_u8(
 407 // CHECK32-NEXT:  entry:
 408 // CHECK32-NEXT:    [[__ODATA_ADDR_I:%.*]] = alloca ptr, align 4
 409 // CHECK32-NEXT:    [[__IDATA_ADDR_I:%.*]] = alloca <2 x i64>, align 16
 410 // CHECK32-NEXT:    [[__H_ADDR_I:%.*]] = alloca ptr, align 4
 411 // CHECK32-NEXT:    [[ODATA_ADDR:%.*]] = alloca ptr, align 4
 412 // CHECK32-NEXT:    [[IDATA_ADDR:%.*]] = alloca <2 x i64>, align 16
 413 // CHECK32-NEXT:    [[H_ADDR:%.*]] = alloca ptr, align 4
 414 // CHECK32-NEXT:    store ptr [[ODATA:%.*]], ptr [[ODATA_ADDR]], align 4
 415 // CHECK32-NEXT:    store <2 x i64> [[IDATA:%.*]], ptr [[IDATA_ADDR]], align 16
 416 // CHECK32-NEXT:    store ptr [[H:%.*]], ptr [[H_ADDR]], align 4
 417 // CHECK32-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[ODATA_ADDR]], align 4
 418 // CHECK32-NEXT:    [[TMP1:%.*]] = load <2 x i64>, ptr [[IDATA_ADDR]], align 16
 419 // CHECK32-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[H_ADDR]], align 4
 420 // CHECK32-NEXT:    store ptr [[TMP0]], ptr [[__ODATA_ADDR_I]], align 4
 421 // CHECK32-NEXT:    store <2 x i64> [[TMP1]], ptr [[__IDATA_ADDR_I]], align 16
 422 // CHECK32-NEXT:    store ptr [[TMP2]], ptr [[__H_ADDR_I]], align 4
 423 // CHECK32-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[__ODATA_ADDR_I]], align 4
 424 // CHECK32-NEXT:    [[TMP4:%.*]] = load <2 x i64>, ptr [[__IDATA_ADDR_I]], align 16
 425 // CHECK32-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[__H_ADDR_I]], align 4
 426 // CHECK32-NEXT:    [[TMP6:%.*]] = call { i8, <2 x i64> } @llvm.x86.aesenc128kl(<2 x i64> [[TMP4]], ptr [[TMP5]])
 427 // CHECK32-NEXT:    [[TMP7:%.*]] = extractvalue { i8, <2 x i64> } [[TMP6]], 0
 428 // CHECK32-NEXT:    [[TMP8:%.*]] = trunc i8 [[TMP7]] to i1
 429 // CHECK32-NEXT:    [[TMP9:%.*]] = extractvalue { i8, <2 x i64> } [[TMP6]], 1
 430 // CHECK32-NEXT:    br i1 [[TMP8]], label [[AESENC128KL_NO_ERROR_I:%.*]], label [[AESENC128KL_ERROR_I:%.*]]
 431 // CHECK32:       aesenc128kl_no_error.i:
 432 // CHECK32-NEXT:    store <2 x i64> [[TMP9]], ptr [[TMP3]], align 16
 433 // CHECK32-NEXT:    br label [[_MM_AESENC128KL_U8_EXIT:%.*]]
 434 // CHECK32:       aesenc128kl_error.i:
 435 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP3]], align 16
 436 // CHECK32-NEXT:    br label [[_MM_AESENC128KL_U8_EXIT]]
 437 // CHECK32:       _mm_aesenc128kl_u8.exit:
 438 // CHECK32-NEXT:    [[TMP10:%.*]] = extractvalue { i8, <2 x i64> } [[TMP6]], 0
 439 // CHECK32-NEXT:    ret i8 [[TMP10]]
 440 //
 441 unsigned char test_mm_aesenc128kl_u8(__m128i *odata, __m128i idata, const void *h) {
 442   return _mm_aesenc128kl_u8(odata, idata, h);
 443 }
 444
 445 // CHECK64-LABEL: @test_mm_aesdec128kl_u8(
 446 // CHECK64-NEXT:  entry:
 447 // CHECK64-NEXT:    [[__ODATA_ADDR_I:%.*]] = alloca ptr, align 8
 448 // CHECK64-NEXT:    [[__IDATA_ADDR_I:%.*]] = alloca <2 x i64>, align 16
 449 // CHECK64-NEXT:    [[__H_ADDR_I:%.*]] = alloca ptr, align 8
 450 // CHECK64-NEXT:    [[ODATA_ADDR:%.*]] = alloca ptr, align 8
 451 // CHECK64-NEXT:    [[IDATA_ADDR:%.*]] = alloca <2 x i64>, align 16
 452 // CHECK64-NEXT:    [[H_ADDR:%.*]] = alloca ptr, align 8
 453 // CHECK64-NEXT:    store ptr [[ODATA:%.*]], ptr [[ODATA_ADDR]], align 8
 454 // CHECK64-NEXT:    store <2 x i64> [[IDATA:%.*]], ptr [[IDATA_ADDR]], align 16
 455 // CHECK64-NEXT:    store ptr [[H:%.*]], ptr [[H_ADDR]], align 8
 456 // CHECK64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[ODATA_ADDR]], align 8
 457 // CHECK64-NEXT:    [[TMP1:%.*]] = load <2 x i64>, ptr [[IDATA_ADDR]], align 16
 458 // CHECK64-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[H_ADDR]], align 8
 459 // CHECK64-NEXT:    store ptr [[TMP0]], ptr [[__ODATA_ADDR_I]], align 8
 460 // CHECK64-NEXT:    store <2 x i64> [[TMP1]], ptr [[__IDATA_ADDR_I]], align 16
 461 // CHECK64-NEXT:    store ptr [[TMP2]], ptr [[__H_ADDR_I]], align 8
 462 // CHECK64-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[__ODATA_ADDR_I]], align 8
 463 // CHECK64-NEXT:    [[TMP4:%.*]] = load <2 x i64>, ptr [[__IDATA_ADDR_I]], align 16
 464 // CHECK64-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[__H_ADDR_I]], align 8
 465 // CHECK64-NEXT:    [[TMP6:%.*]] = call { i8, <2 x i64> } @llvm.x86.aesdec128kl(<2 x i64> [[TMP4]], ptr [[TMP5]])
 466 // CHECK64-NEXT:    [[TMP7:%.*]] = extractvalue { i8, <2 x i64> } [[TMP6]], 0
 467 // CHECK64-NEXT:    [[TMP8:%.*]] = trunc i8 [[TMP7]] to i1
 468 // CHECK64-NEXT:    [[TMP9:%.*]] = extractvalue { i8, <2 x i64> } [[TMP6]], 1
 469 // CHECK64-NEXT:    br i1 [[TMP8]], label [[AESDEC128KL_NO_ERROR_I:%.*]], label [[AESDEC128KL_ERROR_I:%.*]]
 470 // CHECK64:       aesdec128kl_no_error.i:
 471 // CHECK64-NEXT:    store <2 x i64> [[TMP9]], ptr [[TMP3]], align 16
 472 // CHECK64-NEXT:    br label [[_MM_AESDEC128KL_U8_EXIT:%.*]]
 473 // CHECK64:       aesdec128kl_error.i:
 474 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP3]], align 16
 475 // CHECK64-NEXT:    br label [[_MM_AESDEC128KL_U8_EXIT]]
 476 // CHECK64:       _mm_aesdec128kl_u8.exit:
 477 // CHECK64-NEXT:    [[TMP10:%.*]] = extractvalue { i8, <2 x i64> } [[TMP6]], 0
 478 // CHECK64-NEXT:    ret i8 [[TMP10]]
 479 //
 480 // CHECK32-LABEL: @test_mm_aesdec128kl_u8(
 481 // CHECK32-NEXT:  entry:
 482 // CHECK32-NEXT:    [[__ODATA_ADDR_I:%.*]] = alloca ptr, align 4
 483 // CHECK32-NEXT:    [[__IDATA_ADDR_I:%.*]] = alloca <2 x i64>, align 16
 484 // CHECK32-NEXT:    [[__H_ADDR_I:%.*]] = alloca ptr, align 4
 485 // CHECK32-NEXT:    [[ODATA_ADDR:%.*]] = alloca ptr, align 4
 486 // CHECK32-NEXT:    [[IDATA_ADDR:%.*]] = alloca <2 x i64>, align 16
 487 // CHECK32-NEXT:    [[H_ADDR:%.*]] = alloca ptr, align 4
 488 // CHECK32-NEXT:    store ptr [[ODATA:%.*]], ptr [[ODATA_ADDR]], align 4
 489 // CHECK32-NEXT:    store <2 x i64> [[IDATA:%.*]], ptr [[IDATA_ADDR]], align 16
 490 // CHECK32-NEXT:    store ptr [[H:%.*]], ptr [[H_ADDR]], align 4
 491 // CHECK32-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[ODATA_ADDR]], align 4
 492 // CHECK32-NEXT:    [[TMP1:%.*]] = load <2 x i64>, ptr [[IDATA_ADDR]], align 16
 493 // CHECK32-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[H_ADDR]], align 4
 494 // CHECK32-NEXT:    store ptr [[TMP0]], ptr [[__ODATA_ADDR_I]], align 4
 495 // CHECK32-NEXT:    store <2 x i64> [[TMP1]], ptr [[__IDATA_ADDR_I]], align 16
 496 // CHECK32-NEXT:    store ptr [[TMP2]], ptr [[__H_ADDR_I]], align 4
 497 // CHECK32-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[__ODATA_ADDR_I]], align 4
 498 // CHECK32-NEXT:    [[TMP4:%.*]] = load <2 x i64>, ptr [[__IDATA_ADDR_I]], align 16
 499 // CHECK32-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[__H_ADDR_I]], align 4
 500 // CHECK32-NEXT:    [[TMP6:%.*]] = call { i8, <2 x i64> } @llvm.x86.aesdec128kl(<2 x i64> [[TMP4]], ptr [[TMP5]])
 501 // CHECK32-NEXT:    [[TMP7:%.*]] = extractvalue { i8, <2 x i64> } [[TMP6]], 0
 502 // CHECK32-NEXT:    [[TMP8:%.*]] = trunc i8 [[TMP7]] to i1
 503 // CHECK32-NEXT:    [[TMP9:%.*]] = extractvalue { i8, <2 x i64> } [[TMP6]], 1
 504 // CHECK32-NEXT:    br i1 [[TMP8]], label [[AESDEC128KL_NO_ERROR_I:%.*]], label [[AESDEC128KL_ERROR_I:%.*]]
 505 // CHECK32:       aesdec128kl_no_error.i:
 506 // CHECK32-NEXT:    store <2 x i64> [[TMP9]], ptr [[TMP3]], align 16
 507 // CHECK32-NEXT:    br label [[_MM_AESDEC128KL_U8_EXIT:%.*]]
 508 // CHECK32:       aesdec128kl_error.i:
 509 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP3]], align 16
 510 // CHECK32-NEXT:    br label [[_MM_AESDEC128KL_U8_EXIT]]
 511 // CHECK32:       _mm_aesdec128kl_u8.exit:
 512 // CHECK32-NEXT:    [[TMP10:%.*]] = extractvalue { i8, <2 x i64> } [[TMP6]], 0
 513 // CHECK32-NEXT:    ret i8 [[TMP10]]
 514 //
 515 unsigned char test_mm_aesdec128kl_u8(__m128i *odata, __m128i idata, const void *h) {
 516   return _mm_aesdec128kl_u8(odata, idata, h);
 517 }
 518
 519 // CHECK64-LABEL: @test__mm_aesencwide128kl_u8(
 520 // CHECK64-NEXT:  entry:
 521 // CHECK64-NEXT:    [[__ODATA_ADDR_I:%.*]] = alloca ptr, align 8
 522 // CHECK64-NEXT:    [[__IDATA_ADDR_I:%.*]] = alloca ptr, align 8
 523 // CHECK64-NEXT:    [[__H_ADDR_I:%.*]] = alloca ptr, align 8
 524 // CHECK64-NEXT:    [[ODATA_ADDR:%.*]] = alloca ptr, align 8
 525 // CHECK64-NEXT:    [[IDATA_ADDR:%.*]] = alloca ptr, align 8
 526 // CHECK64-NEXT:    [[H_ADDR:%.*]] = alloca ptr, align 8
 527 // CHECK64-NEXT:    store ptr [[ODATA:%.*]], ptr [[ODATA_ADDR]], align 8
 528 // CHECK64-NEXT:    store ptr [[IDATA:%.*]], ptr [[IDATA_ADDR]], align 8
 529 // CHECK64-NEXT:    store ptr [[H:%.*]], ptr [[H_ADDR]], align 8
 530 // CHECK64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[ODATA_ADDR]], align 8
 531 // CHECK64-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[IDATA_ADDR]], align 8
 532 // CHECK64-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[H_ADDR]], align 8
 533 // CHECK64-NEXT:    store ptr [[TMP0]], ptr [[__ODATA_ADDR_I]], align 8
 534 // CHECK64-NEXT:    store ptr [[TMP1]], ptr [[__IDATA_ADDR_I]], align 8
 535 // CHECK64-NEXT:    store ptr [[TMP2]], ptr [[__H_ADDR_I]], align 8
 536 // CHECK64-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[__ODATA_ADDR_I]], align 8
 537 // CHECK64-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[__IDATA_ADDR_I]], align 8
 538 // CHECK64-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[__H_ADDR_I]], align 8
 539 // CHECK64-NEXT:    [[TMP6:%.*]] = load <2 x i64>, ptr [[TMP4]], align 16
 540 // CHECK64-NEXT:    [[TMP7:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 1
 541 // CHECK64-NEXT:    [[TMP8:%.*]] = load <2 x i64>, ptr [[TMP7]], align 16
 542 // CHECK64-NEXT:    [[TMP9:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 2
 543 // CHECK64-NEXT:    [[TMP10:%.*]] = load <2 x i64>, ptr [[TMP9]], align 16
 544 // CHECK64-NEXT:    [[TMP11:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 3
 545 // CHECK64-NEXT:    [[TMP12:%.*]] = load <2 x i64>, ptr [[TMP11]], align 16
 546 // CHECK64-NEXT:    [[TMP13:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 4
 547 // CHECK64-NEXT:    [[TMP14:%.*]] = load <2 x i64>, ptr [[TMP13]], align 16
 548 // CHECK64-NEXT:    [[TMP15:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 5
 549 // CHECK64-NEXT:    [[TMP16:%.*]] = load <2 x i64>, ptr [[TMP15]], align 16
 550 // CHECK64-NEXT:    [[TMP17:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 6
 551 // CHECK64-NEXT:    [[TMP18:%.*]] = load <2 x i64>, ptr [[TMP17]], align 16
 552 // CHECK64-NEXT:    [[TMP19:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 7
 553 // CHECK64-NEXT:    [[TMP20:%.*]] = load <2 x i64>, ptr [[TMP19]], align 16
 554 // CHECK64-NEXT:    [[TMP21:%.*]] = call { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.aesencwide128kl(ptr [[TMP5]], <2 x i64> [[TMP6]], <2 x i64> [[TMP8]], <2 x i64> [[TMP10]], <2 x i64> [[TMP12]], <2 x i64> [[TMP14]], <2 x i64> [[TMP16]], <2 x i64> [[TMP18]], <2 x i64> [[TMP20]])
 555 // CHECK64-NEXT:    [[TMP22:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 0
 556 // CHECK64-NEXT:    [[TMP23:%.*]] = trunc i8 [[TMP22]] to i1
 557 // CHECK64-NEXT:    br i1 [[TMP23]], label [[AESENCWIDE128KL_NO_ERROR_I:%.*]], label [[AESENCWIDE128KL_ERROR_I:%.*]]
 558 // CHECK64:       aesencwide128kl_no_error.i:
 559 // CHECK64-NEXT:    [[TMP24:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 1
 560 // CHECK64-NEXT:    store <2 x i64> [[TMP24]], ptr [[TMP3]], align 16
 561 // CHECK64-NEXT:    [[TMP25:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 2
 562 // CHECK64-NEXT:    [[TMP26:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 1
 563 // CHECK64-NEXT:    store <2 x i64> [[TMP25]], ptr [[TMP26]], align 16
 564 // CHECK64-NEXT:    [[TMP27:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 3
 565 // CHECK64-NEXT:    [[TMP28:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 2
 566 // CHECK64-NEXT:    store <2 x i64> [[TMP27]], ptr [[TMP28]], align 16
 567 // CHECK64-NEXT:    [[TMP29:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 4
 568 // CHECK64-NEXT:    [[TMP30:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 3
 569 // CHECK64-NEXT:    store <2 x i64> [[TMP29]], ptr [[TMP30]], align 16
 570 // CHECK64-NEXT:    [[TMP31:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 5
 571 // CHECK64-NEXT:    [[TMP32:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 4
 572 // CHECK64-NEXT:    store <2 x i64> [[TMP31]], ptr [[TMP32]], align 16
 573 // CHECK64-NEXT:    [[TMP33:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 6
 574 // CHECK64-NEXT:    [[TMP34:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 5
 575 // CHECK64-NEXT:    store <2 x i64> [[TMP33]], ptr [[TMP34]], align 16
 576 // CHECK64-NEXT:    [[TMP35:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 7
 577 // CHECK64-NEXT:    [[TMP36:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 6
 578 // CHECK64-NEXT:    store <2 x i64> [[TMP35]], ptr [[TMP36]], align 16
 579 // CHECK64-NEXT:    [[TMP37:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 8
 580 // CHECK64-NEXT:    [[TMP38:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 7
 581 // CHECK64-NEXT:    store <2 x i64> [[TMP37]], ptr [[TMP38]], align 16
 582 // CHECK64-NEXT:    br label [[_MM_AESENCWIDE128KL_U8_EXIT:%.*]]
 583 // CHECK64:       aesencwide128kl_error.i:
 584 // CHECK64-NEXT:    [[TMP39:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 1
 585 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP3]], align 16
 586 // CHECK64-NEXT:    [[TMP40:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 2
 587 // CHECK64-NEXT:    [[TMP41:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 1
 588 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP41]], align 16
 589 // CHECK64-NEXT:    [[TMP42:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 3
 590 // CHECK64-NEXT:    [[TMP43:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 2
 591 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP43]], align 16
 592 // CHECK64-NEXT:    [[TMP44:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 4
 593 // CHECK64-NEXT:    [[TMP45:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 3
 594 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP45]], align 16
 595 // CHECK64-NEXT:    [[TMP46:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 5
 596 // CHECK64-NEXT:    [[TMP47:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 4
 597 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP47]], align 16
 598 // CHECK64-NEXT:    [[TMP48:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 6
 599 // CHECK64-NEXT:    [[TMP49:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 5
 600 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP49]], align 16
 601 // CHECK64-NEXT:    [[TMP50:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 7
 602 // CHECK64-NEXT:    [[TMP51:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 6
 603 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP51]], align 16
 604 // CHECK64-NEXT:    [[TMP52:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 8
 605 // CHECK64-NEXT:    [[TMP53:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 7
 606 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP53]], align 16
 607 // CHECK64-NEXT:    br label [[_MM_AESENCWIDE128KL_U8_EXIT]]
 608 // CHECK64:       _mm_aesencwide128kl_u8.exit:
 609 // CHECK64-NEXT:    [[TMP54:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 0
 610 // CHECK64-NEXT:    ret i8 [[TMP54]]
 611 //
 612 // CHECK32-LABEL: @test__mm_aesencwide128kl_u8(
 613 // CHECK32-NEXT:  entry:
 614 // CHECK32-NEXT:    [[__ODATA_ADDR_I:%.*]] = alloca ptr, align 4
 615 // CHECK32-NEXT:    [[__IDATA_ADDR_I:%.*]] = alloca ptr, align 4
 616 // CHECK32-NEXT:    [[__H_ADDR_I:%.*]] = alloca ptr, align 4
 617 // CHECK32-NEXT:    [[ODATA_ADDR:%.*]] = alloca ptr, align 4
 618 // CHECK32-NEXT:    [[IDATA_ADDR:%.*]] = alloca ptr, align 4
 619 // CHECK32-NEXT:    [[H_ADDR:%.*]] = alloca ptr, align 4
 620 // CHECK32-NEXT:    store ptr [[ODATA:%.*]], ptr [[ODATA_ADDR]], align 4
 621 // CHECK32-NEXT:    store ptr [[IDATA:%.*]], ptr [[IDATA_ADDR]], align 4
 622 // CHECK32-NEXT:    store ptr [[H:%.*]], ptr [[H_ADDR]], align 4
 623 // CHECK32-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[ODATA_ADDR]], align 4
 624 // CHECK32-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[IDATA_ADDR]], align 4
 625 // CHECK32-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[H_ADDR]], align 4
 626 // CHECK32-NEXT:    store ptr [[TMP0]], ptr [[__ODATA_ADDR_I]], align 4
 627 // CHECK32-NEXT:    store ptr [[TMP1]], ptr [[__IDATA_ADDR_I]], align 4
 628 // CHECK32-NEXT:    store ptr [[TMP2]], ptr [[__H_ADDR_I]], align 4
 629 // CHECK32-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[__ODATA_ADDR_I]], align 4
 630 // CHECK32-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[__IDATA_ADDR_I]], align 4
 631 // CHECK32-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[__H_ADDR_I]], align 4
 632 // CHECK32-NEXT:    [[TMP6:%.*]] = load <2 x i64>, ptr [[TMP4]], align 16
 633 // CHECK32-NEXT:    [[TMP7:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 1
 634 // CHECK32-NEXT:    [[TMP8:%.*]] = load <2 x i64>, ptr [[TMP7]], align 16
 635 // CHECK32-NEXT:    [[TMP9:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 2
 636 // CHECK32-NEXT:    [[TMP10:%.*]] = load <2 x i64>, ptr [[TMP9]], align 16
 637 // CHECK32-NEXT:    [[TMP11:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 3
 638 // CHECK32-NEXT:    [[TMP12:%.*]] = load <2 x i64>, ptr [[TMP11]], align 16
 639 // CHECK32-NEXT:    [[TMP13:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 4
 640 // CHECK32-NEXT:    [[TMP14:%.*]] = load <2 x i64>, ptr [[TMP13]], align 16
 641 // CHECK32-NEXT:    [[TMP15:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 5
 642 // CHECK32-NEXT:    [[TMP16:%.*]] = load <2 x i64>, ptr [[TMP15]], align 16
 643 // CHECK32-NEXT:    [[TMP17:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 6
 644 // CHECK32-NEXT:    [[TMP18:%.*]] = load <2 x i64>, ptr [[TMP17]], align 16
 645 // CHECK32-NEXT:    [[TMP19:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 7
 646 // CHECK32-NEXT:    [[TMP20:%.*]] = load <2 x i64>, ptr [[TMP19]], align 16
 647 // CHECK32-NEXT:    [[TMP21:%.*]] = call { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.aesencwide128kl(ptr [[TMP5]], <2 x i64> [[TMP6]], <2 x i64> [[TMP8]], <2 x i64> [[TMP10]], <2 x i64> [[TMP12]], <2 x i64> [[TMP14]], <2 x i64> [[TMP16]], <2 x i64> [[TMP18]], <2 x i64> [[TMP20]])
 648 // CHECK32-NEXT:    [[TMP22:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 0
 649 // CHECK32-NEXT:    [[TMP23:%.*]] = trunc i8 [[TMP22]] to i1
 650 // CHECK32-NEXT:    br i1 [[TMP23]], label [[AESENCWIDE128KL_NO_ERROR_I:%.*]], label [[AESENCWIDE128KL_ERROR_I:%.*]]
 651 // CHECK32:       aesencwide128kl_no_error.i:
 652 // CHECK32-NEXT:    [[TMP24:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 1
 653 // CHECK32-NEXT:    store <2 x i64> [[TMP24]], ptr [[TMP3]], align 16
 654 // CHECK32-NEXT:    [[TMP25:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 2
 655 // CHECK32-NEXT:    [[TMP26:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 1
 656 // CHECK32-NEXT:    store <2 x i64> [[TMP25]], ptr [[TMP26]], align 16
 657 // CHECK32-NEXT:    [[TMP27:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 3
 658 // CHECK32-NEXT:    [[TMP28:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 2
 659 // CHECK32-NEXT:    store <2 x i64> [[TMP27]], ptr [[TMP28]], align 16
 660 // CHECK32-NEXT:    [[TMP29:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 4
 661 // CHECK32-NEXT:    [[TMP30:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 3
 662 // CHECK32-NEXT:    store <2 x i64> [[TMP29]], ptr [[TMP30]], align 16
 663 // CHECK32-NEXT:    [[TMP31:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 5
 664 // CHECK32-NEXT:    [[TMP32:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 4
 665 // CHECK32-NEXT:    store <2 x i64> [[TMP31]], ptr [[TMP32]], align 16
 666 // CHECK32-NEXT:    [[TMP33:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 6
 667 // CHECK32-NEXT:    [[TMP34:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 5
 668 // CHECK32-NEXT:    store <2 x i64> [[TMP33]], ptr [[TMP34]], align 16
 669 // CHECK32-NEXT:    [[TMP35:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 7
 670 // CHECK32-NEXT:    [[TMP36:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 6
 671 // CHECK32-NEXT:    store <2 x i64> [[TMP35]], ptr [[TMP36]], align 16
 672 // CHECK32-NEXT:    [[TMP37:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 8
 673 // CHECK32-NEXT:    [[TMP38:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 7
 674 // CHECK32-NEXT:    store <2 x i64> [[TMP37]], ptr [[TMP38]], align 16
 675 // CHECK32-NEXT:    br label [[_MM_AESENCWIDE128KL_U8_EXIT:%.*]]
 676 // CHECK32:       aesencwide128kl_error.i:
 677 // CHECK32-NEXT:    [[TMP39:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 1
 678 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP3]], align 16
 679 // CHECK32-NEXT:    [[TMP40:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 2
 680 // CHECK32-NEXT:    [[TMP41:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 1
 681 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP41]], align 16
 682 // CHECK32-NEXT:    [[TMP42:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 3
 683 // CHECK32-NEXT:    [[TMP43:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 2
 684 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP43]], align 16
 685 // CHECK32-NEXT:    [[TMP44:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 4
 686 // CHECK32-NEXT:    [[TMP45:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 3
 687 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP45]], align 16
 688 // CHECK32-NEXT:    [[TMP46:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 5
 689 // CHECK32-NEXT:    [[TMP47:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 4
 690 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP47]], align 16
 691 // CHECK32-NEXT:    [[TMP48:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 6
 692 // CHECK32-NEXT:    [[TMP49:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 5
 693 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP49]], align 16
 694 // CHECK32-NEXT:    [[TMP50:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 7
 695 // CHECK32-NEXT:    [[TMP51:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 6
 696 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP51]], align 16
 697 // CHECK32-NEXT:    [[TMP52:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 8
 698 // CHECK32-NEXT:    [[TMP53:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 7
 699 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP53]], align 16
 700 // CHECK32-NEXT:    br label [[_MM_AESENCWIDE128KL_U8_EXIT]]
 701 // CHECK32:       _mm_aesencwide128kl_u8.exit:
 702 // CHECK32-NEXT:    [[TMP54:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 0
 703 // CHECK32-NEXT:    ret i8 [[TMP54]]
 704 //
 705 unsigned char test__mm_aesencwide128kl_u8(__m128i odata[8], const __m128i idata[8], const void* h) {
 706   return _mm_aesencwide128kl_u8(odata, idata, h);
 707 }
 708
 709 // CHECK64-LABEL: @test__mm_aesdecwide128kl_u8(
 710 // CHECK64-NEXT:  entry:
 711 // CHECK64-NEXT:    [[__ODATA_ADDR_I:%.*]] = alloca ptr, align 8
 712 // CHECK64-NEXT:    [[__IDATA_ADDR_I:%.*]] = alloca ptr, align 8
 713 // CHECK64-NEXT:    [[__H_ADDR_I:%.*]] = alloca ptr, align 8
 714 // CHECK64-NEXT:    [[ODATA_ADDR:%.*]] = alloca ptr, align 8
 715 // CHECK64-NEXT:    [[IDATA_ADDR:%.*]] = alloca ptr, align 8
 716 // CHECK64-NEXT:    [[H_ADDR:%.*]] = alloca ptr, align 8
 717 // CHECK64-NEXT:    store ptr [[ODATA:%.*]], ptr [[ODATA_ADDR]], align 8
 718 // CHECK64-NEXT:    store ptr [[IDATA:%.*]], ptr [[IDATA_ADDR]], align 8
 719 // CHECK64-NEXT:    store ptr [[H:%.*]], ptr [[H_ADDR]], align 8
 720 // CHECK64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[ODATA_ADDR]], align 8
 721 // CHECK64-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[IDATA_ADDR]], align 8
 722 // CHECK64-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[H_ADDR]], align 8
 723 // CHECK64-NEXT:    store ptr [[TMP0]], ptr [[__ODATA_ADDR_I]], align 8
 724 // CHECK64-NEXT:    store ptr [[TMP1]], ptr [[__IDATA_ADDR_I]], align 8
 725 // CHECK64-NEXT:    store ptr [[TMP2]], ptr [[__H_ADDR_I]], align 8
 726 // CHECK64-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[__ODATA_ADDR_I]], align 8
 727 // CHECK64-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[__IDATA_ADDR_I]], align 8
 728 // CHECK64-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[__H_ADDR_I]], align 8
 729 // CHECK64-NEXT:    [[TMP6:%.*]] = load <2 x i64>, ptr [[TMP4]], align 16
 730 // CHECK64-NEXT:    [[TMP7:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 1
 731 // CHECK64-NEXT:    [[TMP8:%.*]] = load <2 x i64>, ptr [[TMP7]], align 16
 732 // CHECK64-NEXT:    [[TMP9:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 2
 733 // CHECK64-NEXT:    [[TMP10:%.*]] = load <2 x i64>, ptr [[TMP9]], align 16
 734 // CHECK64-NEXT:    [[TMP11:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 3
 735 // CHECK64-NEXT:    [[TMP12:%.*]] = load <2 x i64>, ptr [[TMP11]], align 16
 736 // CHECK64-NEXT:    [[TMP13:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 4
 737 // CHECK64-NEXT:    [[TMP14:%.*]] = load <2 x i64>, ptr [[TMP13]], align 16
 738 // CHECK64-NEXT:    [[TMP15:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 5
 739 // CHECK64-NEXT:    [[TMP16:%.*]] = load <2 x i64>, ptr [[TMP15]], align 16
 740 // CHECK64-NEXT:    [[TMP17:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 6
 741 // CHECK64-NEXT:    [[TMP18:%.*]] = load <2 x i64>, ptr [[TMP17]], align 16
 742 // CHECK64-NEXT:    [[TMP19:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 7
 743 // CHECK64-NEXT:    [[TMP20:%.*]] = load <2 x i64>, ptr [[TMP19]], align 16
 744 // CHECK64-NEXT:    [[TMP21:%.*]] = call { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.aesdecwide128kl(ptr [[TMP5]], <2 x i64> [[TMP6]], <2 x i64> [[TMP8]], <2 x i64> [[TMP10]], <2 x i64> [[TMP12]], <2 x i64> [[TMP14]], <2 x i64> [[TMP16]], <2 x i64> [[TMP18]], <2 x i64> [[TMP20]])
 745 // CHECK64-NEXT:    [[TMP22:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 0
 746 // CHECK64-NEXT:    [[TMP23:%.*]] = trunc i8 [[TMP22]] to i1
 747 // CHECK64-NEXT:    br i1 [[TMP23]], label [[AESDECWIDE128KL_NO_ERROR_I:%.*]], label [[AESDECWIDE128KL_ERROR_I:%.*]]
 748 // CHECK64:       aesdecwide128kl_no_error.i:
 749 // CHECK64-NEXT:    [[TMP24:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 1
 750 // CHECK64-NEXT:    store <2 x i64> [[TMP24]], ptr [[TMP3]], align 16
 751 // CHECK64-NEXT:    [[TMP25:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 2
 752 // CHECK64-NEXT:    [[TMP26:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 1
 753 // CHECK64-NEXT:    store <2 x i64> [[TMP25]], ptr [[TMP26]], align 16
 754 // CHECK64-NEXT:    [[TMP27:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 3
 755 // CHECK64-NEXT:    [[TMP28:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 2
 756 // CHECK64-NEXT:    store <2 x i64> [[TMP27]], ptr [[TMP28]], align 16
 757 // CHECK64-NEXT:    [[TMP29:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 4
 758 // CHECK64-NEXT:    [[TMP30:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 3
 759 // CHECK64-NEXT:    store <2 x i64> [[TMP29]], ptr [[TMP30]], align 16
 760 // CHECK64-NEXT:    [[TMP31:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 5
 761 // CHECK64-NEXT:    [[TMP32:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 4
 762 // CHECK64-NEXT:    store <2 x i64> [[TMP31]], ptr [[TMP32]], align 16
 763 // CHECK64-NEXT:    [[TMP33:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 6
 764 // CHECK64-NEXT:    [[TMP34:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 5
 765 // CHECK64-NEXT:    store <2 x i64> [[TMP33]], ptr [[TMP34]], align 16
 766 // CHECK64-NEXT:    [[TMP35:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 7
 767 // CHECK64-NEXT:    [[TMP36:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 6
 768 // CHECK64-NEXT:    store <2 x i64> [[TMP35]], ptr [[TMP36]], align 16
 769 // CHECK64-NEXT:    [[TMP37:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 8
 770 // CHECK64-NEXT:    [[TMP38:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 7
 771 // CHECK64-NEXT:    store <2 x i64> [[TMP37]], ptr [[TMP38]], align 16
 772 // CHECK64-NEXT:    br label [[_MM_AESDECWIDE128KL_U8_EXIT:%.*]]
 773 // CHECK64:       aesdecwide128kl_error.i:
 774 // CHECK64-NEXT:    [[TMP39:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 1
 775 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP3]], align 16
 776 // CHECK64-NEXT:    [[TMP40:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 2
 777 // CHECK64-NEXT:    [[TMP41:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 1
 778 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP41]], align 16
 779 // CHECK64-NEXT:    [[TMP42:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 3
 780 // CHECK64-NEXT:    [[TMP43:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 2
 781 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP43]], align 16
 782 // CHECK64-NEXT:    [[TMP44:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 4
 783 // CHECK64-NEXT:    [[TMP45:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 3
 784 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP45]], align 16
 785 // CHECK64-NEXT:    [[TMP46:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 5
 786 // CHECK64-NEXT:    [[TMP47:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 4
 787 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP47]], align 16
 788 // CHECK64-NEXT:    [[TMP48:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 6
 789 // CHECK64-NEXT:    [[TMP49:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 5
 790 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP49]], align 16
 791 // CHECK64-NEXT:    [[TMP50:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 7
 792 // CHECK64-NEXT:    [[TMP51:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 6
 793 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP51]], align 16
 794 // CHECK64-NEXT:    [[TMP52:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 8
 795 // CHECK64-NEXT:    [[TMP53:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 7
 796 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP53]], align 16
 797 // CHECK64-NEXT:    br label [[_MM_AESDECWIDE128KL_U8_EXIT]]
 798 // CHECK64:       _mm_aesdecwide128kl_u8.exit:
 799 // CHECK64-NEXT:    [[TMP54:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 0
 800 // CHECK64-NEXT:    ret i8 [[TMP54]]
 801 //
 802 // CHECK32-LABEL: @test__mm_aesdecwide128kl_u8(
 803 // CHECK32-NEXT:  entry:
 804 // CHECK32-NEXT:    [[__ODATA_ADDR_I:%.*]] = alloca ptr, align 4
 805 // CHECK32-NEXT:    [[__IDATA_ADDR_I:%.*]] = alloca ptr, align 4
 806 // CHECK32-NEXT:    [[__H_ADDR_I:%.*]] = alloca ptr, align 4
 807 // CHECK32-NEXT:    [[ODATA_ADDR:%.*]] = alloca ptr, align 4
 808 // CHECK32-NEXT:    [[IDATA_ADDR:%.*]] = alloca ptr, align 4
 809 // CHECK32-NEXT:    [[H_ADDR:%.*]] = alloca ptr, align 4
 810 // CHECK32-NEXT:    store ptr [[ODATA:%.*]], ptr [[ODATA_ADDR]], align 4
 811 // CHECK32-NEXT:    store ptr [[IDATA:%.*]], ptr [[IDATA_ADDR]], align 4
 812 // CHECK32-NEXT:    store ptr [[H:%.*]], ptr [[H_ADDR]], align 4
 813 // CHECK32-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[ODATA_ADDR]], align 4
 814 // CHECK32-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[IDATA_ADDR]], align 4
 815 // CHECK32-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[H_ADDR]], align 4
 816 // CHECK32-NEXT:    store ptr [[TMP0]], ptr [[__ODATA_ADDR_I]], align 4
 817 // CHECK32-NEXT:    store ptr [[TMP1]], ptr [[__IDATA_ADDR_I]], align 4
 818 // CHECK32-NEXT:    store ptr [[TMP2]], ptr [[__H_ADDR_I]], align 4
 819 // CHECK32-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[__ODATA_ADDR_I]], align 4
 820 // CHECK32-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[__IDATA_ADDR_I]], align 4
 821 // CHECK32-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[__H_ADDR_I]], align 4
 822 // CHECK32-NEXT:    [[TMP6:%.*]] = load <2 x i64>, ptr [[TMP4]], align 16
 823 // CHECK32-NEXT:    [[TMP7:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 1
 824 // CHECK32-NEXT:    [[TMP8:%.*]] = load <2 x i64>, ptr [[TMP7]], align 16
 825 // CHECK32-NEXT:    [[TMP9:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 2
 826 // CHECK32-NEXT:    [[TMP10:%.*]] = load <2 x i64>, ptr [[TMP9]], align 16
 827 // CHECK32-NEXT:    [[TMP11:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 3
 828 // CHECK32-NEXT:    [[TMP12:%.*]] = load <2 x i64>, ptr [[TMP11]], align 16
 829 // CHECK32-NEXT:    [[TMP13:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 4
 830 // CHECK32-NEXT:    [[TMP14:%.*]] = load <2 x i64>, ptr [[TMP13]], align 16
 831 // CHECK32-NEXT:    [[TMP15:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 5
 832 // CHECK32-NEXT:    [[TMP16:%.*]] = load <2 x i64>, ptr [[TMP15]], align 16
 833 // CHECK32-NEXT:    [[TMP17:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 6
 834 // CHECK32-NEXT:    [[TMP18:%.*]] = load <2 x i64>, ptr [[TMP17]], align 16
 835 // CHECK32-NEXT:    [[TMP19:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 7
 836 // CHECK32-NEXT:    [[TMP20:%.*]] = load <2 x i64>, ptr [[TMP19]], align 16
 837 // CHECK32-NEXT:    [[TMP21:%.*]] = call { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.aesdecwide128kl(ptr [[TMP5]], <2 x i64> [[TMP6]], <2 x i64> [[TMP8]], <2 x i64> [[TMP10]], <2 x i64> [[TMP12]], <2 x i64> [[TMP14]], <2 x i64> [[TMP16]], <2 x i64> [[TMP18]], <2 x i64> [[TMP20]])
 838 // CHECK32-NEXT:    [[TMP22:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 0
 839 // CHECK32-NEXT:    [[TMP23:%.*]] = trunc i8 [[TMP22]] to i1
 840 // CHECK32-NEXT:    br i1 [[TMP23]], label [[AESDECWIDE128KL_NO_ERROR_I:%.*]], label [[AESDECWIDE128KL_ERROR_I:%.*]]
 841 // CHECK32:       aesdecwide128kl_no_error.i:
 842 // CHECK32-NEXT:    [[TMP24:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 1
 843 // CHECK32-NEXT:    store <2 x i64> [[TMP24]], ptr [[TMP3]], align 16
 844 // CHECK32-NEXT:    [[TMP25:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 2
 845 // CHECK32-NEXT:    [[TMP26:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 1
 846 // CHECK32-NEXT:    store <2 x i64> [[TMP25]], ptr [[TMP26]], align 16
 847 // CHECK32-NEXT:    [[TMP27:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 3
 848 // CHECK32-NEXT:    [[TMP28:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 2
 849 // CHECK32-NEXT:    store <2 x i64> [[TMP27]], ptr [[TMP28]], align 16
 850 // CHECK32-NEXT:    [[TMP29:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 4
 851 // CHECK32-NEXT:    [[TMP30:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 3
 852 // CHECK32-NEXT:    store <2 x i64> [[TMP29]], ptr [[TMP30]], align 16
 853 // CHECK32-NEXT:    [[TMP31:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 5
 854 // CHECK32-NEXT:    [[TMP32:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 4
 855 // CHECK32-NEXT:    store <2 x i64> [[TMP31]], ptr [[TMP32]], align 16
 856 // CHECK32-NEXT:    [[TMP33:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 6
 857 // CHECK32-NEXT:    [[TMP34:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 5
 858 // CHECK32-NEXT:    store <2 x i64> [[TMP33]], ptr [[TMP34]], align 16
 859 // CHECK32-NEXT:    [[TMP35:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 7
 860 // CHECK32-NEXT:    [[TMP36:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 6
 861 // CHECK32-NEXT:    store <2 x i64> [[TMP35]], ptr [[TMP36]], align 16
 862 // CHECK32-NEXT:    [[TMP37:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 8
 863 // CHECK32-NEXT:    [[TMP38:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 7
 864 // CHECK32-NEXT:    store <2 x i64> [[TMP37]], ptr [[TMP38]], align 16
 865 // CHECK32-NEXT:    br label [[_MM_AESDECWIDE128KL_U8_EXIT:%.*]]
 866 // CHECK32:       aesdecwide128kl_error.i:
 867 // CHECK32-NEXT:    [[TMP39:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 1
 868 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP3]], align 16
 869 // CHECK32-NEXT:    [[TMP40:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 2
 870 // CHECK32-NEXT:    [[TMP41:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 1
 871 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP41]], align 16
 872 // CHECK32-NEXT:    [[TMP42:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 3
 873 // CHECK32-NEXT:    [[TMP43:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 2
 874 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP43]], align 16
 875 // CHECK32-NEXT:    [[TMP44:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 4
 876 // CHECK32-NEXT:    [[TMP45:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 3
 877 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP45]], align 16
 878 // CHECK32-NEXT:    [[TMP46:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 5
 879 // CHECK32-NEXT:    [[TMP47:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 4
 880 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP47]], align 16
 881 // CHECK32-NEXT:    [[TMP48:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 6
 882 // CHECK32-NEXT:    [[TMP49:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 5
 883 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP49]], align 16
 884 // CHECK32-NEXT:    [[TMP50:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 7
 885 // CHECK32-NEXT:    [[TMP51:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 6
 886 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP51]], align 16
 887 // CHECK32-NEXT:    [[TMP52:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 8
 888 // CHECK32-NEXT:    [[TMP53:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 7
 889 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP53]], align 16
 890 // CHECK32-NEXT:    br label [[_MM_AESDECWIDE128KL_U8_EXIT]]
 891 // CHECK32:       _mm_aesdecwide128kl_u8.exit:
 892 // CHECK32-NEXT:    [[TMP54:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 0
 893 // CHECK32-NEXT:    ret i8 [[TMP54]]
 894 //
 895 unsigned char test__mm_aesdecwide128kl_u8(__m128i odata[8], const __m128i idata[8], const void* h) {
 896   return _mm_aesdecwide128kl_u8(odata, idata, h);
 897 }
 898
 899 // CHECK64-LABEL: @test__mm_aesencwide256kl_u8(
 900 // CHECK64-NEXT:  entry:
 901 // CHECK64-NEXT:    [[__ODATA_ADDR_I:%.*]] = alloca ptr, align 8
 902 // CHECK64-NEXT:    [[__IDATA_ADDR_I:%.*]] = alloca ptr, align 8
 903 // CHECK64-NEXT:    [[__H_ADDR_I:%.*]] = alloca ptr, align 8
 904 // CHECK64-NEXT:    [[ODATA_ADDR:%.*]] = alloca ptr, align 8
 905 // CHECK64-NEXT:    [[IDATA_ADDR:%.*]] = alloca ptr, align 8
 906 // CHECK64-NEXT:    [[H_ADDR:%.*]] = alloca ptr, align 8
 907 // CHECK64-NEXT:    store ptr [[ODATA:%.*]], ptr [[ODATA_ADDR]], align 8
 908 // CHECK64-NEXT:    store ptr [[IDATA:%.*]], ptr [[IDATA_ADDR]], align 8
 909 // CHECK64-NEXT:    store ptr [[H:%.*]], ptr [[H_ADDR]], align 8
 910 // CHECK64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[ODATA_ADDR]], align 8
 911 // CHECK64-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[IDATA_ADDR]], align 8
 912 // CHECK64-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[H_ADDR]], align 8
 913 // CHECK64-NEXT:    store ptr [[TMP0]], ptr [[__ODATA_ADDR_I]], align 8
 914 // CHECK64-NEXT:    store ptr [[TMP1]], ptr [[__IDATA_ADDR_I]], align 8
 915 // CHECK64-NEXT:    store ptr [[TMP2]], ptr [[__H_ADDR_I]], align 8
 916 // CHECK64-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[__ODATA_ADDR_I]], align 8
 917 // CHECK64-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[__IDATA_ADDR_I]], align 8
 918 // CHECK64-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[__H_ADDR_I]], align 8
 919 // CHECK64-NEXT:    [[TMP6:%.*]] = load <2 x i64>, ptr [[TMP4]], align 16
 920 // CHECK64-NEXT:    [[TMP7:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 1
 921 // CHECK64-NEXT:    [[TMP8:%.*]] = load <2 x i64>, ptr [[TMP7]], align 16
 922 // CHECK64-NEXT:    [[TMP9:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 2
 923 // CHECK64-NEXT:    [[TMP10:%.*]] = load <2 x i64>, ptr [[TMP9]], align 16
 924 // CHECK64-NEXT:    [[TMP11:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 3
 925 // CHECK64-NEXT:    [[TMP12:%.*]] = load <2 x i64>, ptr [[TMP11]], align 16
 926 // CHECK64-NEXT:    [[TMP13:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 4
 927 // CHECK64-NEXT:    [[TMP14:%.*]] = load <2 x i64>, ptr [[TMP13]], align 16
 928 // CHECK64-NEXT:    [[TMP15:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 5
 929 // CHECK64-NEXT:    [[TMP16:%.*]] = load <2 x i64>, ptr [[TMP15]], align 16
 930 // CHECK64-NEXT:    [[TMP17:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 6
 931 // CHECK64-NEXT:    [[TMP18:%.*]] = load <2 x i64>, ptr [[TMP17]], align 16
 932 // CHECK64-NEXT:    [[TMP19:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 7
 933 // CHECK64-NEXT:    [[TMP20:%.*]] = load <2 x i64>, ptr [[TMP19]], align 16
 934 // CHECK64-NEXT:    [[TMP21:%.*]] = call { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.aesencwide256kl(ptr [[TMP5]], <2 x i64> [[TMP6]], <2 x i64> [[TMP8]], <2 x i64> [[TMP10]], <2 x i64> [[TMP12]], <2 x i64> [[TMP14]], <2 x i64> [[TMP16]], <2 x i64> [[TMP18]], <2 x i64> [[TMP20]])
 935 // CHECK64-NEXT:    [[TMP22:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 0
 936 // CHECK64-NEXT:    [[TMP23:%.*]] = trunc i8 [[TMP22]] to i1
 937 // CHECK64-NEXT:    br i1 [[TMP23]], label [[AESENCWIDE256KL_NO_ERROR_I:%.*]], label [[AESENCWIDE256KL_ERROR_I:%.*]]
 938 // CHECK64:       aesencwide256kl_no_error.i:
 939 // CHECK64-NEXT:    [[TMP24:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 1
 940 // CHECK64-NEXT:    store <2 x i64> [[TMP24]], ptr [[TMP3]], align 16
 941 // CHECK64-NEXT:    [[TMP25:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 2
 942 // CHECK64-NEXT:    [[TMP26:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 1
 943 // CHECK64-NEXT:    store <2 x i64> [[TMP25]], ptr [[TMP26]], align 16
 944 // CHECK64-NEXT:    [[TMP27:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 3
 945 // CHECK64-NEXT:    [[TMP28:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 2
 946 // CHECK64-NEXT:    store <2 x i64> [[TMP27]], ptr [[TMP28]], align 16
 947 // CHECK64-NEXT:    [[TMP29:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 4
 948 // CHECK64-NEXT:    [[TMP30:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 3
 949 // CHECK64-NEXT:    store <2 x i64> [[TMP29]], ptr [[TMP30]], align 16
 950 // CHECK64-NEXT:    [[TMP31:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 5
 951 // CHECK64-NEXT:    [[TMP32:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 4
 952 // CHECK64-NEXT:    store <2 x i64> [[TMP31]], ptr [[TMP32]], align 16
 953 // CHECK64-NEXT:    [[TMP33:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 6
 954 // CHECK64-NEXT:    [[TMP34:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 5
 955 // CHECK64-NEXT:    store <2 x i64> [[TMP33]], ptr [[TMP34]], align 16
 956 // CHECK64-NEXT:    [[TMP35:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 7
 957 // CHECK64-NEXT:    [[TMP36:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 6
 958 // CHECK64-NEXT:    store <2 x i64> [[TMP35]], ptr [[TMP36]], align 16
 959 // CHECK64-NEXT:    [[TMP37:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 8
 960 // CHECK64-NEXT:    [[TMP38:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 7
 961 // CHECK64-NEXT:    store <2 x i64> [[TMP37]], ptr [[TMP38]], align 16
 962 // CHECK64-NEXT:    br label [[_MM_AESENCWIDE256KL_U8_EXIT:%.*]]
 963 // CHECK64:       aesencwide256kl_error.i:
 964 // CHECK64-NEXT:    [[TMP39:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 1
 965 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP3]], align 16
 966 // CHECK64-NEXT:    [[TMP40:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 2
 967 // CHECK64-NEXT:    [[TMP41:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 1
 968 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP41]], align 16
 969 // CHECK64-NEXT:    [[TMP42:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 3
 970 // CHECK64-NEXT:    [[TMP43:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 2
 971 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP43]], align 16
 972 // CHECK64-NEXT:    [[TMP44:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 4
 973 // CHECK64-NEXT:    [[TMP45:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 3
 974 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP45]], align 16
 975 // CHECK64-NEXT:    [[TMP46:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 5
 976 // CHECK64-NEXT:    [[TMP47:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 4
 977 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP47]], align 16
 978 // CHECK64-NEXT:    [[TMP48:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 6
 979 // CHECK64-NEXT:    [[TMP49:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 5
 980 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP49]], align 16
 981 // CHECK64-NEXT:    [[TMP50:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 7
 982 // CHECK64-NEXT:    [[TMP51:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 6
 983 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP51]], align 16
 984 // CHECK64-NEXT:    [[TMP52:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 8
 985 // CHECK64-NEXT:    [[TMP53:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 7
 986 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP53]], align 16
 987 // CHECK64-NEXT:    br label [[_MM_AESENCWIDE256KL_U8_EXIT]]
 988 // CHECK64:       _mm_aesencwide256kl_u8.exit:
 989 // CHECK64-NEXT:    [[TMP54:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 0
 990 // CHECK64-NEXT:    ret i8 [[TMP54]]
 991 //
 992 // CHECK32-LABEL: @test__mm_aesencwide256kl_u8(
 993 // CHECK32-NEXT:  entry:
 994 // CHECK32-NEXT:    [[__ODATA_ADDR_I:%.*]] = alloca ptr, align 4
 995 // CHECK32-NEXT:    [[__IDATA_ADDR_I:%.*]] = alloca ptr, align 4
 996 // CHECK32-NEXT:    [[__H_ADDR_I:%.*]] = alloca ptr, align 4
 997 // CHECK32-NEXT:    [[ODATA_ADDR:%.*]] = alloca ptr, align 4
 998 // CHECK32-NEXT:    [[IDATA_ADDR:%.*]] = alloca ptr, align 4
 999 // CHECK32-NEXT:    [[H_ADDR:%.*]] = alloca ptr, align 4
1000 // CHECK32-NEXT:    store ptr [[ODATA:%.*]], ptr [[ODATA_ADDR]], align 4
1001 // CHECK32-NEXT:    store ptr [[IDATA:%.*]], ptr [[IDATA_ADDR]], align 4
1002 // CHECK32-NEXT:    store ptr [[H:%.*]], ptr [[H_ADDR]], align 4
1003 // CHECK32-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[ODATA_ADDR]], align 4
1004 // CHECK32-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[IDATA_ADDR]], align 4
1005 // CHECK32-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[H_ADDR]], align 4
1006 // CHECK32-NEXT:    store ptr [[TMP0]], ptr [[__ODATA_ADDR_I]], align 4
1007 // CHECK32-NEXT:    store ptr [[TMP1]], ptr [[__IDATA_ADDR_I]], align 4
1008 // CHECK32-NEXT:    store ptr [[TMP2]], ptr [[__H_ADDR_I]], align 4
1009 // CHECK32-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[__ODATA_ADDR_I]], align 4
1010 // CHECK32-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[__IDATA_ADDR_I]], align 4
1011 // CHECK32-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[__H_ADDR_I]], align 4
1012 // CHECK32-NEXT:    [[TMP6:%.*]] = load <2 x i64>, ptr [[TMP4]], align 16
1013 // CHECK32-NEXT:    [[TMP7:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 1
1014 // CHECK32-NEXT:    [[TMP8:%.*]] = load <2 x i64>, ptr [[TMP7]], align 16
1015 // CHECK32-NEXT:    [[TMP9:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 2
1016 // CHECK32-NEXT:    [[TMP10:%.*]] = load <2 x i64>, ptr [[TMP9]], align 16
1017 // CHECK32-NEXT:    [[TMP11:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 3
1018 // CHECK32-NEXT:    [[TMP12:%.*]] = load <2 x i64>, ptr [[TMP11]], align 16
1019 // CHECK32-NEXT:    [[TMP13:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 4
1020 // CHECK32-NEXT:    [[TMP14:%.*]] = load <2 x i64>, ptr [[TMP13]], align 16
1021 // CHECK32-NEXT:    [[TMP15:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 5
1022 // CHECK32-NEXT:    [[TMP16:%.*]] = load <2 x i64>, ptr [[TMP15]], align 16
1023 // CHECK32-NEXT:    [[TMP17:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 6
1024 // CHECK32-NEXT:    [[TMP18:%.*]] = load <2 x i64>, ptr [[TMP17]], align 16
1025 // CHECK32-NEXT:    [[TMP19:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 7
1026 // CHECK32-NEXT:    [[TMP20:%.*]] = load <2 x i64>, ptr [[TMP19]], align 16
1027 // CHECK32-NEXT:    [[TMP21:%.*]] = call { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.aesencwide256kl(ptr [[TMP5]], <2 x i64> [[TMP6]], <2 x i64> [[TMP8]], <2 x i64> [[TMP10]], <2 x i64> [[TMP12]], <2 x i64> [[TMP14]], <2 x i64> [[TMP16]], <2 x i64> [[TMP18]], <2 x i64> [[TMP20]])
1028 // CHECK32-NEXT:    [[TMP22:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 0
1029 // CHECK32-NEXT:    [[TMP23:%.*]] = trunc i8 [[TMP22]] to i1
1030 // CHECK32-NEXT:    br i1 [[TMP23]], label [[AESENCWIDE256KL_NO_ERROR_I:%.*]], label [[AESENCWIDE256KL_ERROR_I:%.*]]
1031 // CHECK32:       aesencwide256kl_no_error.i:
1032 // CHECK32-NEXT:    [[TMP24:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 1
1033 // CHECK32-NEXT:    store <2 x i64> [[TMP24]], ptr [[TMP3]], align 16
1034 // CHECK32-NEXT:    [[TMP25:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 2
1035 // CHECK32-NEXT:    [[TMP26:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 1
1036 // CHECK32-NEXT:    store <2 x i64> [[TMP25]], ptr [[TMP26]], align 16
1037 // CHECK32-NEXT:    [[TMP27:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 3
1038 // CHECK32-NEXT:    [[TMP28:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 2
1039 // CHECK32-NEXT:    store <2 x i64> [[TMP27]], ptr [[TMP28]], align 16
1040 // CHECK32-NEXT:    [[TMP29:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 4
1041 // CHECK32-NEXT:    [[TMP30:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 3
1042 // CHECK32-NEXT:    store <2 x i64> [[TMP29]], ptr [[TMP30]], align 16
1043 // CHECK32-NEXT:    [[TMP31:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 5
1044 // CHECK32-NEXT:    [[TMP32:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 4
1045 // CHECK32-NEXT:    store <2 x i64> [[TMP31]], ptr [[TMP32]], align 16
1046 // CHECK32-NEXT:    [[TMP33:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 6
1047 // CHECK32-NEXT:    [[TMP34:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 5
1048 // CHECK32-NEXT:    store <2 x i64> [[TMP33]], ptr [[TMP34]], align 16
1049 // CHECK32-NEXT:    [[TMP35:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 7
1050 // CHECK32-NEXT:    [[TMP36:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 6
1051 // CHECK32-NEXT:    store <2 x i64> [[TMP35]], ptr [[TMP36]], align 16
1052 // CHECK32-NEXT:    [[TMP37:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 8
1053 // CHECK32-NEXT:    [[TMP38:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 7
1054 // CHECK32-NEXT:    store <2 x i64> [[TMP37]], ptr [[TMP38]], align 16
1055 // CHECK32-NEXT:    br label [[_MM_AESENCWIDE256KL_U8_EXIT:%.*]]
1056 // CHECK32:       aesencwide256kl_error.i:
1057 // CHECK32-NEXT:    [[TMP39:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 1
1058 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP3]], align 16
1059 // CHECK32-NEXT:    [[TMP40:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 2
1060 // CHECK32-NEXT:    [[TMP41:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 1
1061 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP41]], align 16
1062 // CHECK32-NEXT:    [[TMP42:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 3
1063 // CHECK32-NEXT:    [[TMP43:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 2
1064 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP43]], align 16
1065 // CHECK32-NEXT:    [[TMP44:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 4
1066 // CHECK32-NEXT:    [[TMP45:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 3
1067 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP45]], align 16
1068 // CHECK32-NEXT:    [[TMP46:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 5
1069 // CHECK32-NEXT:    [[TMP47:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 4
1070 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP47]], align 16
1071 // CHECK32-NEXT:    [[TMP48:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 6
1072 // CHECK32-NEXT:    [[TMP49:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 5
1073 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP49]], align 16
1074 // CHECK32-NEXT:    [[TMP50:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 7
1075 // CHECK32-NEXT:    [[TMP51:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 6
1076 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP51]], align 16
1077 // CHECK32-NEXT:    [[TMP52:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 8
1078 // CHECK32-NEXT:    [[TMP53:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 7
1079 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP53]], align 16
1080 // CHECK32-NEXT:    br label [[_MM_AESENCWIDE256KL_U8_EXIT]]
1081 // CHECK32:       _mm_aesencwide256kl_u8.exit:
1082 // CHECK32-NEXT:    [[TMP54:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 0
1083 // CHECK32-NEXT:    ret i8 [[TMP54]]
1084 //
1085 unsigned char test__mm_aesencwide256kl_u8(__m128i odata[8], const __m128i idata[8], const void* h) {
1086   return _mm_aesencwide256kl_u8(odata, idata, h);
1087 }
1088
1089 // CHECK64-LABEL: @test__mm_aesdecwide256kl_u8(
1090 // CHECK64-NEXT:  entry:
1091 // CHECK64-NEXT:    [[__ODATA_ADDR_I:%.*]] = alloca ptr, align 8
1092 // CHECK64-NEXT:    [[__IDATA_ADDR_I:%.*]] = alloca ptr, align 8
1093 // CHECK64-NEXT:    [[__H_ADDR_I:%.*]] = alloca ptr, align 8
1094 // CHECK64-NEXT:    [[ODATA_ADDR:%.*]] = alloca ptr, align 8
1095 // CHECK64-NEXT:    [[IDATA_ADDR:%.*]] = alloca ptr, align 8
1096 // CHECK64-NEXT:    [[H_ADDR:%.*]] = alloca ptr, align 8
1097 // CHECK64-NEXT:    store ptr [[ODATA:%.*]], ptr [[ODATA_ADDR]], align 8
1098 // CHECK64-NEXT:    store ptr [[IDATA:%.*]], ptr [[IDATA_ADDR]], align 8
1099 // CHECK64-NEXT:    store ptr [[H:%.*]], ptr [[H_ADDR]], align 8
1100 // CHECK64-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[ODATA_ADDR]], align 8
1101 // CHECK64-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[IDATA_ADDR]], align 8
1102 // CHECK64-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[H_ADDR]], align 8
1103 // CHECK64-NEXT:    store ptr [[TMP0]], ptr [[__ODATA_ADDR_I]], align 8
1104 // CHECK64-NEXT:    store ptr [[TMP1]], ptr [[__IDATA_ADDR_I]], align 8
1105 // CHECK64-NEXT:    store ptr [[TMP2]], ptr [[__H_ADDR_I]], align 8
1106 // CHECK64-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[__ODATA_ADDR_I]], align 8
1107 // CHECK64-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[__IDATA_ADDR_I]], align 8
1108 // CHECK64-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[__H_ADDR_I]], align 8
1109 // CHECK64-NEXT:    [[TMP6:%.*]] = load <2 x i64>, ptr [[TMP4]], align 16
1110 // CHECK64-NEXT:    [[TMP7:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 1
1111 // CHECK64-NEXT:    [[TMP8:%.*]] = load <2 x i64>, ptr [[TMP7]], align 16
1112 // CHECK64-NEXT:    [[TMP9:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 2
1113 // CHECK64-NEXT:    [[TMP10:%.*]] = load <2 x i64>, ptr [[TMP9]], align 16
1114 // CHECK64-NEXT:    [[TMP11:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 3
1115 // CHECK64-NEXT:    [[TMP12:%.*]] = load <2 x i64>, ptr [[TMP11]], align 16
1116 // CHECK64-NEXT:    [[TMP13:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 4
1117 // CHECK64-NEXT:    [[TMP14:%.*]] = load <2 x i64>, ptr [[TMP13]], align 16
1118 // CHECK64-NEXT:    [[TMP15:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 5
1119 // CHECK64-NEXT:    [[TMP16:%.*]] = load <2 x i64>, ptr [[TMP15]], align 16
1120 // CHECK64-NEXT:    [[TMP17:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 6
1121 // CHECK64-NEXT:    [[TMP18:%.*]] = load <2 x i64>, ptr [[TMP17]], align 16
1122 // CHECK64-NEXT:    [[TMP19:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 7
1123 // CHECK64-NEXT:    [[TMP20:%.*]] = load <2 x i64>, ptr [[TMP19]], align 16
1124 // CHECK64-NEXT:    [[TMP21:%.*]] = call { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.aesdecwide256kl(ptr [[TMP5]], <2 x i64> [[TMP6]], <2 x i64> [[TMP8]], <2 x i64> [[TMP10]], <2 x i64> [[TMP12]], <2 x i64> [[TMP14]], <2 x i64> [[TMP16]], <2 x i64> [[TMP18]], <2 x i64> [[TMP20]])
1125 // CHECK64-NEXT:    [[TMP22:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 0
1126 // CHECK64-NEXT:    [[TMP23:%.*]] = trunc i8 [[TMP22]] to i1
1127 // CHECK64-NEXT:    br i1 [[TMP23]], label [[AESDECWIDE256KL_NO_ERROR_I:%.*]], label [[AESDECWIDE256KL_ERROR_I:%.*]]
1128 // CHECK64:       aesdecwide256kl_no_error.i:
1129 // CHECK64-NEXT:    [[TMP24:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 1
1130 // CHECK64-NEXT:    store <2 x i64> [[TMP24]], ptr [[TMP3]], align 16
1131 // CHECK64-NEXT:    [[TMP25:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 2
1132 // CHECK64-NEXT:    [[TMP26:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 1
1133 // CHECK64-NEXT:    store <2 x i64> [[TMP25]], ptr [[TMP26]], align 16
1134 // CHECK64-NEXT:    [[TMP27:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 3
1135 // CHECK64-NEXT:    [[TMP28:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 2
1136 // CHECK64-NEXT:    store <2 x i64> [[TMP27]], ptr [[TMP28]], align 16
1137 // CHECK64-NEXT:    [[TMP29:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 4
1138 // CHECK64-NEXT:    [[TMP30:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 3
1139 // CHECK64-NEXT:    store <2 x i64> [[TMP29]], ptr [[TMP30]], align 16
1140 // CHECK64-NEXT:    [[TMP31:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 5
1141 // CHECK64-NEXT:    [[TMP32:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 4
1142 // CHECK64-NEXT:    store <2 x i64> [[TMP31]], ptr [[TMP32]], align 16
1143 // CHECK64-NEXT:    [[TMP33:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 6
1144 // CHECK64-NEXT:    [[TMP34:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 5
1145 // CHECK64-NEXT:    store <2 x i64> [[TMP33]], ptr [[TMP34]], align 16
1146 // CHECK64-NEXT:    [[TMP35:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 7
1147 // CHECK64-NEXT:    [[TMP36:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 6
1148 // CHECK64-NEXT:    store <2 x i64> [[TMP35]], ptr [[TMP36]], align 16
1149 // CHECK64-NEXT:    [[TMP37:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 8
1150 // CHECK64-NEXT:    [[TMP38:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 7
1151 // CHECK64-NEXT:    store <2 x i64> [[TMP37]], ptr [[TMP38]], align 16
1152 // CHECK64-NEXT:    br label [[_MM_AESDECWIDE256KL_U8_EXIT:%.*]]
1153 // CHECK64:       aesdecwide256kl_error.i:
1154 // CHECK64-NEXT:    [[TMP39:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 1
1155 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP3]], align 16
1156 // CHECK64-NEXT:    [[TMP40:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 2
1157 // CHECK64-NEXT:    [[TMP41:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 1
1158 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP41]], align 16
1159 // CHECK64-NEXT:    [[TMP42:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 3
1160 // CHECK64-NEXT:    [[TMP43:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 2
1161 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP43]], align 16
1162 // CHECK64-NEXT:    [[TMP44:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 4
1163 // CHECK64-NEXT:    [[TMP45:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 3
1164 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP45]], align 16
1165 // CHECK64-NEXT:    [[TMP46:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 5
1166 // CHECK64-NEXT:    [[TMP47:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 4
1167 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP47]], align 16
1168 // CHECK64-NEXT:    [[TMP48:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 6
1169 // CHECK64-NEXT:    [[TMP49:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 5
1170 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP49]], align 16
1171 // CHECK64-NEXT:    [[TMP50:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 7
1172 // CHECK64-NEXT:    [[TMP51:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 6
1173 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP51]], align 16
1174 // CHECK64-NEXT:    [[TMP52:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 8
1175 // CHECK64-NEXT:    [[TMP53:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 7
1176 // CHECK64-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP53]], align 16
1177 // CHECK64-NEXT:    br label [[_MM_AESDECWIDE256KL_U8_EXIT]]
1178 // CHECK64:       _mm_aesdecwide256kl_u8.exit:
1179 // CHECK64-NEXT:    [[TMP54:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 0
1180 // CHECK64-NEXT:    ret i8 [[TMP54]]
1181 //
1182 // CHECK32-LABEL: @test__mm_aesdecwide256kl_u8(
1183 // CHECK32-NEXT:  entry:
1184 // CHECK32-NEXT:    [[__ODATA_ADDR_I:%.*]] = alloca ptr, align 4
1185 // CHECK32-NEXT:    [[__IDATA_ADDR_I:%.*]] = alloca ptr, align 4
1186 // CHECK32-NEXT:    [[__H_ADDR_I:%.*]] = alloca ptr, align 4
1187 // CHECK32-NEXT:    [[ODATA_ADDR:%.*]] = alloca ptr, align 4
1188 // CHECK32-NEXT:    [[IDATA_ADDR:%.*]] = alloca ptr, align 4
1189 // CHECK32-NEXT:    [[H_ADDR:%.*]] = alloca ptr, align 4
1190 // CHECK32-NEXT:    store ptr [[ODATA:%.*]], ptr [[ODATA_ADDR]], align 4
1191 // CHECK32-NEXT:    store ptr [[IDATA:%.*]], ptr [[IDATA_ADDR]], align 4
1192 // CHECK32-NEXT:    store ptr [[H:%.*]], ptr [[H_ADDR]], align 4
1193 // CHECK32-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[ODATA_ADDR]], align 4
1194 // CHECK32-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[IDATA_ADDR]], align 4
1195 // CHECK32-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[H_ADDR]], align 4
1196 // CHECK32-NEXT:    store ptr [[TMP0]], ptr [[__ODATA_ADDR_I]], align 4
1197 // CHECK32-NEXT:    store ptr [[TMP1]], ptr [[__IDATA_ADDR_I]], align 4
1198 // CHECK32-NEXT:    store ptr [[TMP2]], ptr [[__H_ADDR_I]], align 4
1199 // CHECK32-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[__ODATA_ADDR_I]], align 4
1200 // CHECK32-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[__IDATA_ADDR_I]], align 4
1201 // CHECK32-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[__H_ADDR_I]], align 4
1202 // CHECK32-NEXT:    [[TMP6:%.*]] = load <2 x i64>, ptr [[TMP4]], align 16
1203 // CHECK32-NEXT:    [[TMP7:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 1
1204 // CHECK32-NEXT:    [[TMP8:%.*]] = load <2 x i64>, ptr [[TMP7]], align 16
1205 // CHECK32-NEXT:    [[TMP9:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 2
1206 // CHECK32-NEXT:    [[TMP10:%.*]] = load <2 x i64>, ptr [[TMP9]], align 16
1207 // CHECK32-NEXT:    [[TMP11:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 3
1208 // CHECK32-NEXT:    [[TMP12:%.*]] = load <2 x i64>, ptr [[TMP11]], align 16
1209 // CHECK32-NEXT:    [[TMP13:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 4
1210 // CHECK32-NEXT:    [[TMP14:%.*]] = load <2 x i64>, ptr [[TMP13]], align 16
1211 // CHECK32-NEXT:    [[TMP15:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 5
1212 // CHECK32-NEXT:    [[TMP16:%.*]] = load <2 x i64>, ptr [[TMP15]], align 16
1213 // CHECK32-NEXT:    [[TMP17:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 6
1214 // CHECK32-NEXT:    [[TMP18:%.*]] = load <2 x i64>, ptr [[TMP17]], align 16
1215 // CHECK32-NEXT:    [[TMP19:%.*]] = getelementptr <2 x i64>, ptr [[TMP4]], i32 7
1216 // CHECK32-NEXT:    [[TMP20:%.*]] = load <2 x i64>, ptr [[TMP19]], align 16
1217 // CHECK32-NEXT:    [[TMP21:%.*]] = call { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.aesdecwide256kl(ptr [[TMP5]], <2 x i64> [[TMP6]], <2 x i64> [[TMP8]], <2 x i64> [[TMP10]], <2 x i64> [[TMP12]], <2 x i64> [[TMP14]], <2 x i64> [[TMP16]], <2 x i64> [[TMP18]], <2 x i64> [[TMP20]])
1218 // CHECK32-NEXT:    [[TMP22:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 0
1219 // CHECK32-NEXT:    [[TMP23:%.*]] = trunc i8 [[TMP22]] to i1
1220 // CHECK32-NEXT:    br i1 [[TMP23]], label [[AESDECWIDE256KL_NO_ERROR_I:%.*]], label [[AESDECWIDE256KL_ERROR_I:%.*]]
1221 // CHECK32:       aesdecwide256kl_no_error.i:
1222 // CHECK32-NEXT:    [[TMP24:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 1
1223 // CHECK32-NEXT:    store <2 x i64> [[TMP24]], ptr [[TMP3]], align 16
1224 // CHECK32-NEXT:    [[TMP25:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 2
1225 // CHECK32-NEXT:    [[TMP26:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 1
1226 // CHECK32-NEXT:    store <2 x i64> [[TMP25]], ptr [[TMP26]], align 16
1227 // CHECK32-NEXT:    [[TMP27:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 3
1228 // CHECK32-NEXT:    [[TMP28:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 2
1229 // CHECK32-NEXT:    store <2 x i64> [[TMP27]], ptr [[TMP28]], align 16
1230 // CHECK32-NEXT:    [[TMP29:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 4
1231 // CHECK32-NEXT:    [[TMP30:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 3
1232 // CHECK32-NEXT:    store <2 x i64> [[TMP29]], ptr [[TMP30]], align 16
1233 // CHECK32-NEXT:    [[TMP31:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 5
1234 // CHECK32-NEXT:    [[TMP32:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 4
1235 // CHECK32-NEXT:    store <2 x i64> [[TMP31]], ptr [[TMP32]], align 16
1236 // CHECK32-NEXT:    [[TMP33:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 6
1237 // CHECK32-NEXT:    [[TMP34:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 5
1238 // CHECK32-NEXT:    store <2 x i64> [[TMP33]], ptr [[TMP34]], align 16
1239 // CHECK32-NEXT:    [[TMP35:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 7
1240 // CHECK32-NEXT:    [[TMP36:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 6
1241 // CHECK32-NEXT:    store <2 x i64> [[TMP35]], ptr [[TMP36]], align 16
1242 // CHECK32-NEXT:    [[TMP37:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 8
1243 // CHECK32-NEXT:    [[TMP38:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 7
1244 // CHECK32-NEXT:    store <2 x i64> [[TMP37]], ptr [[TMP38]], align 16
1245 // CHECK32-NEXT:    br label [[_MM_AESDECWIDE256KL_U8_EXIT:%.*]]
1246 // CHECK32:       aesdecwide256kl_error.i:
1247 // CHECK32-NEXT:    [[TMP39:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 1
1248 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP3]], align 16
1249 // CHECK32-NEXT:    [[TMP40:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 2
1250 // CHECK32-NEXT:    [[TMP41:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 1
1251 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP41]], align 16
1252 // CHECK32-NEXT:    [[TMP42:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 3
1253 // CHECK32-NEXT:    [[TMP43:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 2
1254 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP43]], align 16
1255 // CHECK32-NEXT:    [[TMP44:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 4
1256 // CHECK32-NEXT:    [[TMP45:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 3
1257 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP45]], align 16
1258 // CHECK32-NEXT:    [[TMP46:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 5
1259 // CHECK32-NEXT:    [[TMP47:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 4
1260 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP47]], align 16
1261 // CHECK32-NEXT:    [[TMP48:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 6
1262 // CHECK32-NEXT:    [[TMP49:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 5
1263 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP49]], align 16
1264 // CHECK32-NEXT:    [[TMP50:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 7
1265 // CHECK32-NEXT:    [[TMP51:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 6
1266 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP51]], align 16
1267 // CHECK32-NEXT:    [[TMP52:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 8
1268 // CHECK32-NEXT:    [[TMP53:%.*]] = getelementptr <2 x i64>, ptr [[TMP3]], i32 7
1269 // CHECK32-NEXT:    store <2 x i64> zeroinitializer, ptr [[TMP53]], align 16
1270 // CHECK32-NEXT:    br label [[_MM_AESDECWIDE256KL_U8_EXIT]]
1271 // CHECK32:       _mm_aesdecwide256kl_u8.exit:
1272 // CHECK32-NEXT:    [[TMP54:%.*]] = extractvalue { i8, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } [[TMP21]], 0
1273 // CHECK32-NEXT:    ret i8 [[TMP54]]
1274 //
1275 unsigned char test__mm_aesdecwide256kl_u8(__m128i odata[8], const __m128i idata[8], const void* h) {
1276   return _mm_aesdecwide256kl_u8(odata, idata, h);
1277 }