clang/test/CodeGen/arm-neon-numeric-maxmin.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature
   2 // RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
   3
   4 // REQUIRES: aarch64-registered-target || arm-registered-target
   5
   6 #include <arm_neon.h>
   7
   8 // CHECK-LABEL: define {{[^@]+}}@test_vmaxnm_f32
   9 // CHECK-SAME: (<2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0:[0-9]+]] {
  10 // CHECK-NEXT:  entry:
  11 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <8 x i8>
  12 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <2 x float> [[B]] to <8 x i8>
  13 // CHECK-NEXT:    [[VMAXNM_V2_I:%.*]] = call <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float> [[A]], <2 x float> [[B]])
  14 // CHECK-NEXT:    [[VMAXNM_V3_I:%.*]] = bitcast <2 x float> [[VMAXNM_V2_I]] to <8 x i8>
  15 // CHECK-NEXT:    ret <2 x float> [[VMAXNM_V2_I]]
  16 //
  17 float32x2_t test_vmaxnm_f32(float32x2_t a, float32x2_t b) {
  18   return vmaxnm_f32(a, b);
  19 }
  20
  21 // CHECK-LABEL: define {{[^@]+}}@test_vmaxnmq_f32
  22 // CHECK-SAME: (<4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]]) #[[ATTR1:[0-9]+]] {
  23 // CHECK-NEXT:  entry:
  24 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <16 x i8>
  25 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x float> [[B]] to <16 x i8>
  26 // CHECK-NEXT:    [[VMAXNMQ_V2_I:%.*]] = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> [[A]], <4 x float> [[B]])
  27 // CHECK-NEXT:    [[VMAXNMQ_V3_I:%.*]] = bitcast <4 x float> [[VMAXNMQ_V2_I]] to <16 x i8>
  28 // CHECK-NEXT:    ret <4 x float> [[VMAXNMQ_V2_I]]
  29 //
  30 float32x4_t test_vmaxnmq_f32(float32x4_t a, float32x4_t b) {
  31   return vmaxnmq_f32(a, b);
  32 }
  33
  34 // CHECK-LABEL: define {{[^@]+}}@test_vminnm_f32
  35 // CHECK-SAME: (<2 x float> noundef [[A:%.*]], <2 x float> noundef [[B:%.*]]) #[[ATTR0]] {
  36 // CHECK-NEXT:  entry:
  37 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <8 x i8>
  38 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <2 x float> [[B]] to <8 x i8>
  39 // CHECK-NEXT:    [[VMINNM_V2_I:%.*]] = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> [[A]], <2 x float> [[B]])
  40 // CHECK-NEXT:    [[VMINNM_V3_I:%.*]] = bitcast <2 x float> [[VMINNM_V2_I]] to <8 x i8>
  41 // CHECK-NEXT:    ret <2 x float> [[VMINNM_V2_I]]
  42 //
  43 float32x2_t test_vminnm_f32(float32x2_t a, float32x2_t b) {
  44   return vminnm_f32(a, b);
  45 }
  46
  47 // CHECK-LABEL: define {{[^@]+}}@test_vminnmq_f32
  48 // CHECK-SAME: (<4 x float> noundef [[A:%.*]], <4 x float> noundef [[B:%.*]]) #[[ATTR1]] {
  49 // CHECK-NEXT:  entry:
  50 // CHECK-NEXT:    [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <16 x i8>
  51 // CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x float> [[B]] to <16 x i8>
  52 // CHECK-NEXT:    [[VMINNMQ_V2_I:%.*]] = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> [[A]], <4 x float> [[B]])
  53 // CHECK-NEXT:    [[VMINNMQ_V3_I:%.*]] = bitcast <4 x float> [[VMINNMQ_V2_I]] to <16 x i8>
  54 // CHECK-NEXT:    ret <4 x float> [[VMINNMQ_V2_I]]
  55 //
  56 float32x4_t test_vminnmq_f32(float32x4_t a, float32x4_t b) {
  57   return vminnmq_f32(a, b);
  58 }
  59