clang/test/CodeGen/arm64_vdupq_n_f64.c

   1 // RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -disable-O0-optnone -emit-llvm %s | opt -S -passes=mem2reg | FileCheck %s
   2
   3 // REQUIRES: aarch64-registered-target || arm-registered-target
   4
   5 #include <arm_neon.h>
   6
   7 // vdupq_n_f64 -> dup.2d v0, v0[0]
   8 //
   9 // CHECK-LABEL: define{{.*}} <2 x double> @test_vdupq_n_f64(double noundef %w) #0 {
  10 // CHECK:   [[VECINIT_I:%.*]] = insertelement <2 x double> poison, double %w, i32 0
  11 // CHECK:   [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double %w, i32 1
  12 // CHECK:   ret <2 x double> [[VECINIT1_I]]
  13 float64x2_t test_vdupq_n_f64(float64_t w) {
  14     return vdupq_n_f64(w);
  15 }
  16
  17 // might as well test this while we're here
  18 // vdupq_n_f32 -> dup.4s v0, v0[0]
  19 // CHECK-LABEL: define{{.*}} <4 x float> @test_vdupq_n_f32(float noundef %w) #0 {
  20 // CHECK:   [[VECINIT_I:%.*]] = insertelement <4 x float> poison, float %w, i32 0
  21 // CHECK:   [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %w, i32 1
  22 // CHECK:   [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float %w, i32 2
  23 // CHECK:   [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float %w, i32 3
  24 // CHECK:   ret <4 x float> [[VECINIT3_I]]
  25 float32x4_t test_vdupq_n_f32(float32_t w) {
  26     return vdupq_n_f32(w);
  27 }
  28
  29 // vdupq_lane_f64 -> dup.2d v0, v0[0]
  30 // CHECK-LABEL: define{{.*}} <2 x double> @test_vdupq_lane_f64(<1 x double> noundef %V) #0 {
  31 // CHECK:   [[TMP0:%.*]] = bitcast <1 x double> %V to <8 x i8>
  32 // CHECK:   [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x double>
  33 // CHECK:   [[SHUFFLE:%.*]] = shufflevector <1 x double> [[TMP1]], <1 x double> [[TMP1]], <2 x i32> zeroinitializer
  34 // CHECK:   ret <2 x double> [[SHUFFLE]]
  35 float64x2_t test_vdupq_lane_f64(float64x1_t V) {
  36     return vdupq_lane_f64(V, 0);
  37 }
  38
  39 // vmovq_n_f64 -> dup Vd.2d,X0
  40 // CHECK-LABEL: define{{.*}} <2 x double> @test_vmovq_n_f64(double noundef %w) #0 {
  41 // CHECK:   [[VECINIT_I:%.*]] = insertelement <2 x double> poison, double %w, i32 0
  42 // CHECK:   [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double %w, i32 1
  43 // CHECK:   ret <2 x double> [[VECINIT1_I]]
  44 float64x2_t test_vmovq_n_f64(float64_t w) {
  45   return vmovq_n_f64(w);
  46 }
  47
  48 // CHECK-LABEL: define{{.*}} <4 x half> @test_vmov_n_f16(ptr noundef %a1) #0 {
  49 // CHECK:   [[TMP0:%.*]] = load half, ptr %a1, align 2
  50 // CHECK:   [[VECINIT:%.*]] = insertelement <4 x half> poison, half [[TMP0]], i32 0
  51 // CHECK:   [[VECINIT1:%.*]] = insertelement <4 x half> [[VECINIT]], half [[TMP0]], i32 1
  52 // CHECK:   [[VECINIT2:%.*]] = insertelement <4 x half> [[VECINIT1]], half [[TMP0]], i32 2
  53 // CHECK:   [[VECINIT3:%.*]] = insertelement <4 x half> [[VECINIT2]], half [[TMP0]], i32 3
  54 // CHECK:   ret <4 x half> [[VECINIT3]]
  55 float16x4_t test_vmov_n_f16(float16_t *a1) {
  56   return vmov_n_f16(*a1);
  57 }
  58
  59 /*
  60 float64x1_t test_vmov_n_f64(float64_t a1) {
  61   return vmov_n_f64(a1);
  62 }
  63 */
  64
  65 // CHECK-LABEL: define{{.*}} <8 x half> @test_vmovq_n_f16(ptr noundef %a1) #0 {
  66 // CHECK:   [[TMP0:%.*]] = load half, ptr %a1, align 2
  67 // CHECK:   [[VECINIT:%.*]] = insertelement <8 x half> poison, half [[TMP0]], i32 0
  68 // CHECK:   [[VECINIT1:%.*]] = insertelement <8 x half> [[VECINIT]], half [[TMP0]], i32 1
  69 // CHECK:   [[VECINIT2:%.*]] = insertelement <8 x half> [[VECINIT1]], half [[TMP0]], i32 2
  70 // CHECK:   [[VECINIT3:%.*]] = insertelement <8 x half> [[VECINIT2]], half [[TMP0]], i32 3
  71 // CHECK:   [[VECINIT4:%.*]] = insertelement <8 x half> [[VECINIT3]], half [[TMP0]], i32 4
  72 // CHECK:   [[VECINIT5:%.*]] = insertelement <8 x half> [[VECINIT4]], half [[TMP0]], i32 5
  73 // CHECK:   [[VECINIT6:%.*]] = insertelement <8 x half> [[VECINIT5]], half [[TMP0]], i32 6
  74 // CHECK:   [[VECINIT7:%.*]] = insertelement <8 x half> [[VECINIT6]], half [[TMP0]], i32 7
  75 // CHECK:   ret <8 x half> [[VECINIT7]]
  76 float16x8_t test_vmovq_n_f16(float16_t *a1) {
  77   return vmovq_n_f16(*a1);
  78 }