clang/test/CodeGen/bittest-intrin.c

   1 // RUN: %clang_cc1 -fms-extensions -triple x86_64-windows-msvc %s -emit-llvm -o - | FileCheck %s --check-prefix=X64
   2 // RUN: %clang_cc1 -fms-extensions -triple thumbv7-windows-msvc %s -emit-llvm -o - | FileCheck %s --check-prefix=ARM
   3 // RUN: %clang_cc1 -fms-extensions -triple aarch64-windows-msvc %s -emit-llvm -o - | FileCheck %s --check-prefix=ARM
   4
   5 volatile unsigned char sink = 0;
   6 void test32(long *base, long idx) {
   7   sink = _bittest(base, idx);
   8   sink = _bittestandcomplement(base, idx);
   9   sink = _bittestandreset(base, idx);
  10   sink = _bittestandset(base, idx);
  11   sink = _interlockedbittestandreset(base, idx);
  12   sink = _interlockedbittestandset(base, idx);
  13   sink = _interlockedbittestandset(base, idx);
  14 }
  15
  16 void test64(__int64 *base, __int64 idx) {
  17   sink = _bittest64(base, idx);
  18   sink = _bittestandcomplement64(base, idx);
  19   sink = _bittestandreset64(base, idx);
  20   sink = _bittestandset64(base, idx);
  21   sink = _interlockedbittestandreset64(base, idx);
  22   sink = _interlockedbittestandset64(base, idx);
  23 }
  24
  25 #if defined(_M_ARM) || defined(_M_ARM64)
  26 void test_arm(long *base, long idx) {
  27   sink = _interlockedbittestandreset_acq(base, idx);
  28   sink = _interlockedbittestandreset_rel(base, idx);
  29   sink = _interlockedbittestandreset_nf(base, idx);
  30   sink = _interlockedbittestandset_acq(base, idx);
  31   sink = _interlockedbittestandset_rel(base, idx);
  32   sink = _interlockedbittestandset_nf(base, idx);
  33 }
  34 #endif
  35
  36 // X64-LABEL: define dso_local void @test32(ptr noundef %base, i32 noundef %idx)
  37 // X64: call i8 asm sideeffect "btl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(ptr %{{.*}}, i32 {{.*}})
  38 // X64: call i8 asm sideeffect "btcl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(ptr %{{.*}}, i32 {{.*}})
  39 // X64: call i8 asm sideeffect "btrl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(ptr %{{.*}}, i32 {{.*}})
  40 // X64: call i8 asm sideeffect "btsl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(ptr %{{.*}}, i32 {{.*}})
  41 // X64: call i8 asm sideeffect "lock btrl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(ptr %{{.*}}, i32 {{.*}})
  42 // X64: call i8 asm sideeffect "lock btsl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(ptr %{{.*}}, i32 {{.*}})
  43
  44 // X64-LABEL: define dso_local void @test64(ptr noundef %base, i64 noundef %idx)
  45 // X64: call i8 asm sideeffect "btq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(ptr %{{.*}}, i64 {{.*}})
  46 // X64: call i8 asm sideeffect "btcq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(ptr %{{.*}}, i64 {{.*}})
  47 // X64: call i8 asm sideeffect "btrq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(ptr %{{.*}}, i64 {{.*}})
  48 // X64: call i8 asm sideeffect "btsq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(ptr %{{.*}}, i64 {{.*}})
  49 // X64: call i8 asm sideeffect "lock btrq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(ptr %{{.*}}, i64 {{.*}})
  50 // X64: call i8 asm sideeffect "lock btsq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(ptr %{{.*}}, i64 {{.*}})
  51
  52 // ARM-LABEL: define dso_local {{.*}}void @test32(ptr noundef %base, i32 noundef %idx)
  53 // ARM: %[[IDXHI:[^ ]*]] = ashr i32 %{{.*}}, 3
  54 // ARM: %[[BYTEADDR:[^ ]*]] = getelementptr inbounds i8, ptr %{{.*}}, i32 %[[IDXHI]]
  55 // ARM: %[[IDX8:[^ ]*]] = trunc i32 %{{.*}} to i8
  56 // ARM: %[[IDXLO:[^ ]*]] = and i8 %[[IDX8]], 7
  57 // ARM: %[[BYTE:[^ ]*]] = load i8, ptr %[[BYTEADDR]], align 1
  58 // ARM: %[[BYTESHR:[^ ]*]] = lshr i8 %[[BYTE]], %[[IDXLO]]
  59 // ARM: %[[RES:[^ ]*]] = and i8 %[[BYTESHR]], 1
  60 // ARM: store volatile i8 %[[RES]], ptr @sink, align 1
  61
  62 // ARM: %[[IDXHI:[^ ]*]] = ashr i32 %{{.*}}, 3
  63 // ARM: %[[BYTEADDR:[^ ]*]] = getelementptr inbounds i8, ptr %{{.*}}, i32 %[[IDXHI]]
  64 // ARM: %[[IDX8:[^ ]*]] = trunc i32 %{{.*}} to i8
  65 // ARM: %[[IDXLO:[^ ]*]] = and i8 %[[IDX8]], 7
  66 // ARM: %[[MASK:[^ ]*]] = shl i8 1, %[[IDXLO]]
  67 // ARM: %[[BYTE:[^ ]*]] = load i8, ptr %[[BYTEADDR]], align 1
  68 // ARM: %[[NEWBYTE:[^ ]*]] = xor i8 %[[BYTE]], %[[MASK]]
  69 // ARM: store i8 %[[NEWBYTE]], ptr %[[BYTEADDR]], align 1
  70 // ARM: %[[BYTESHR:[^ ]*]] = lshr i8 %[[BYTE]], %[[IDXLO]]
  71 // ARM: %[[RES:[^ ]*]] = and i8 %[[BYTESHR]], 1
  72 // ARM: store volatile i8 %[[RES]], ptr @sink, align 1
  73
  74 // ARM: %[[IDXHI:[^ ]*]] = ashr i32 %{{.*}}, 3
  75 // ARM: %[[BYTEADDR:[^ ]*]] = getelementptr inbounds i8, ptr %{{.*}}, i32 %[[IDXHI]]
  76 // ARM: %[[IDX8:[^ ]*]] = trunc i32 %{{.*}} to i8
  77 // ARM: %[[IDXLO:[^ ]*]] = and i8 %[[IDX8]], 7
  78 // ARM: %[[MASK:[^ ]*]] = shl i8 1, %[[IDXLO]]
  79 // ARM: %[[BYTE:[^ ]*]] = load i8, ptr %[[BYTEADDR]], align 1
  80 // ARM: %[[NOTMASK:[^ ]*]] = xor i8 %[[MASK]], -1
  81 // ARM: %[[NEWBYTE:[^ ]*]] = and i8 %[[BYTE]], %[[NOTMASK]]
  82 // ARM: store i8 %[[NEWBYTE]], ptr %[[BYTEADDR]], align 1
  83 // ARM: %[[BYTESHR:[^ ]*]] = lshr i8 %[[BYTE]], %[[IDXLO]]
  84 // ARM: %[[RES:[^ ]*]] = and i8 %[[BYTESHR]], 1
  85 // ARM: store volatile i8 %[[RES]], ptr @sink, align 1
  86
  87 // ARM: %[[IDXHI:[^ ]*]] = ashr i32 %{{.*}}, 3
  88 // ARM: %[[BYTEADDR:[^ ]*]] = getelementptr inbounds i8, ptr %{{.*}}, i32 %[[IDXHI]]
  89 // ARM: %[[IDX8:[^ ]*]] = trunc i32 %{{.*}} to i8
  90 // ARM: %[[IDXLO:[^ ]*]] = and i8 %[[IDX8]], 7
  91 // ARM: %[[MASK:[^ ]*]] = shl i8 1, %[[IDXLO]]
  92 // ARM: %[[BYTE:[^ ]*]] = load i8, ptr %[[BYTEADDR]], align 1
  93 // ARM: %[[NEWBYTE:[^ ]*]] = or i8 %[[BYTE]], %[[MASK]]
  94 // ARM: store i8 %[[NEWBYTE]], ptr %[[BYTEADDR]], align 1
  95 // ARM: %[[BYTESHR:[^ ]*]] = lshr i8 %[[BYTE]], %[[IDXLO]]
  96 // ARM: %[[RES:[^ ]*]] = and i8 %[[BYTESHR]], 1
  97 // ARM: store volatile i8 %[[RES]], ptr @sink, align 1
  98
  99 // ARM: %[[IDXHI:[^ ]*]] = ashr i32 %{{.*}}, 3
 100 // ARM: %[[BYTEADDR:[^ ]*]] = getelementptr inbounds i8, ptr %{{.*}}, i32 %[[IDXHI]]
 101 // ARM: %[[IDX8:[^ ]*]] = trunc i32 %{{.*}} to i8
 102 // ARM: %[[IDXLO:[^ ]*]] = and i8 %[[IDX8]], 7
 103 // ARM: %[[MASK:[^ ]*]] = shl i8 1, %[[IDXLO]]
 104 // ARM: %[[NOTMASK:[^ ]*]] = xor i8 %[[MASK]], -1
 105 // ARM: %[[BYTE:[^ ]*]] = atomicrmw and ptr %[[BYTEADDR]], i8 %[[NOTMASK]] seq_cst, align 1
 106 // ARM: %[[BYTESHR:[^ ]*]] = lshr i8 %[[BYTE]], %[[IDXLO]]
 107 // ARM: %[[RES:[^ ]*]] = and i8 %[[BYTESHR]], 1
 108 // ARM: store volatile i8 %[[RES]], ptr @sink, align 1
 109
 110 // ARM: %[[IDXHI:[^ ]*]] = ashr i32 %{{.*}}, 3
 111 // ARM: %[[BYTEADDR:[^ ]*]] = getelementptr inbounds i8, ptr %{{.*}}, i32 %[[IDXHI]]
 112 // ARM: %[[IDX8:[^ ]*]] = trunc i32 %{{.*}} to i8
 113 // ARM: %[[IDXLO:[^ ]*]] = and i8 %[[IDX8]], 7
 114 // ARM: %[[MASK:[^ ]*]] = shl i8 1, %[[IDXLO]]
 115 // ARM: %[[BYTE:[^ ]*]] = atomicrmw or ptr %[[BYTEADDR]], i8 %[[MASK]] seq_cst, align 1
 116 // ARM: %[[BYTESHR:[^ ]*]] = lshr i8 %[[BYTE]], %[[IDXLO]]
 117 // ARM: %[[RES:[^ ]*]] = and i8 %[[BYTESHR]], 1
 118 // ARM: store volatile i8 %[[RES]], ptr @sink, align 1
 119
 120
 121 // Just look for the atomicrmw instructions.
 122
 123 // ARM-LABEL: define dso_local {{.*}}void @test_arm(ptr noundef %base, i32 noundef %idx)
 124 // ARM: atomicrmw and ptr %{{.*}}, i8 {{.*}} acquire, align 1
 125 // ARM: atomicrmw and ptr %{{.*}}, i8 {{.*}} release, align 1
 126 // ARM: atomicrmw and ptr %{{.*}}, i8 {{.*}} monotonic, align 1
 127 // ARM: atomicrmw or ptr %{{.*}}, i8 {{.*}} acquire, align 1
 128 // ARM: atomicrmw or ptr %{{.*}}, i8 {{.*}} release, align 1
 129 // ARM: atomicrmw or ptr %{{.*}}, i8 {{.*}} monotonic, align 1