clang/test/CodeGen/no-bitfield-type-align.c

   1 // RUN: %clang_cc1 -triple x86_64-apple-darwin -fno-bitfield-type-align -fdump-record-layouts-simple -emit-llvm -o %t %s | FileCheck %s -check-prefix=LAYOUT
   2 // RUN: FileCheck %s <%t
   3
   4 struct S {
   5   unsigned short:   0;
   6   unsigned short  f1:15;
   7   unsigned short:   0;
   8   unsigned short  f2:15;
   9 };
  10
  11 // LAYOUT-LABEL: LLVMType:%struct.S =
  12 // LAYOUT-SAME: type { i32 }
  13 // LAYOUT: BitFields:[
  14 // LAYOUT-NEXT: <CGBitFieldInfo Offset:0 Size:15 IsSigned:0 StorageSize:32 StorageOffset:0
  15 // LAYOUT-NEXT: <CGBitFieldInfo Offset:15 Size:15 IsSigned:0 StorageSize:32 StorageOffset:0
  16 // LAYOUT-NEXT: ]>
  17
  18 // CHECK: define{{.*}} void @test_zero_width_bitfield(ptr noundef %[[A:.*]])
  19 // CHECK: %[[BF_LOAD:.*]] = load i32, ptr %[[V1:.*]], align 1
  20 // CHECK: %[[BF_CLEAR:.*]] = and i32 %[[BF_LOAD]], 32767
  21 // CHECK: %[[BF_CAST:.*]] = trunc i32 %[[BF_CLEAR]] to i16
  22 // CHECK: %[[CONV:.*]] = zext i16 %[[BF_CAST]] to i32
  23 // CHECK: %[[ADD:.*]] = add nsw i32 %[[CONV]], 1
  24 // CHECK: %[[CONV1:.*]] = trunc i32 %[[ADD]] to i16
  25 // CHECK: %[[V2:.*]] = zext i16 %[[CONV1]] to i32
  26 // CHECK: %[[BF_LOAD2:.*]] = load i32, ptr %[[V1]], align 1
  27 // CHECK: %[[BF_VALUE:.*]] = and i32 %[[V2]], 32767
  28 // CHECK: %[[BF_CLEAR3:.*]] = and i32 %[[BF_LOAD2]], -32768
  29 // CHECK: %[[BF_SET:.*]] = or i32 %[[BF_CLEAR3]], %[[BF_VALUE]]
  30 // CHECK: store i32 %[[BF_SET]], ptr %[[V1]], align 1
  31
  32 // CHECK: %[[BF_LOAD4:.*]] = load i32, ptr %[[V4:.*]], align 1
  33 // CHECK: %[[BF_LSHR:.*]] = lshr i32 %[[BF_LOAD4]], 15
  34 // CHECK: %[[BF_CLEAR5:.*]] = and i32 %[[BF_LSHR]], 32767
  35 // CHECK: %[[BF_CAST6:.*]] = trunc i32 %[[BF_CLEAR5]] to i16
  36 // CHECK: %[[CONV7:.*]] = zext i16 %[[BF_CAST6]] to i32
  37 // CHECK: %[[ADD8:.*]] = add nsw i32 %[[CONV7]], 2
  38 // CHECK: %[[CONV9:.*]] = trunc i32 %[[ADD8]] to i16
  39 // CHECK: %[[V5:.*]] = zext i16 %[[CONV9]] to i32
  40 // CHECK: %[[BF_LOAD10:.*]] = load i32, ptr %[[V4]], align 1
  41 // CHECK: %[[BF_VALUE11:.*]] = and i32 %[[V5]], 32767
  42 // CHECK: %[[BF_SHL:.*]] = shl i32 %[[BF_VALUE11]], 15
  43 // CHECK: %[[BF_CLEAR12:.*]] = and i32 %[[BF_LOAD10]], -1073709057
  44 // CHECK: %[[BF_SET13:.*]] = or i32 %[[BF_CLEAR12]], %[[BF_SHL]]
  45 // CHECK: store i32 %[[BF_SET13]], ptr %[[V4]], align 1
  46
  47 void test_zero_width_bitfield(struct S *a) {
  48   a->f1 += 1;
  49   a->f2 += 2;
  50 }