clang/test/CodeGen/sparcv9-inline-asm.c

   1 // RUN: %clang_cc1 -triple sparcv9-unknown-unknown -emit-llvm %s -o - | FileCheck %s
   2
   3 void test_gcc_registers(void) {
   4     register unsigned int regO6 asm("o6") = 0;
   5     register unsigned int regSP asm("sp") = 1;
   6     register unsigned int reg14 asm("r14") = 2;
   7     register unsigned int regI6 asm("i6") = 3;
   8     register unsigned int regFP asm("fp") = 4;
   9     register unsigned int reg30 asm("r30") = 5;
  10
  11     register float fF20 asm("f20") = 8.0;
  12     register double dF40 asm("f40") = 11.0;
  13     register long double qF40 asm("f40") = 14.0;
  14
  15     // Test remapping register names in register ... asm("rN") statments.
  16
  17     // CHECK: call void asm sideeffect "add $0,$1,$2", "{r14},{r14},{r14}"
  18     asm volatile("add %0,%1,%2" : : "r" (regO6), "r" (regSP), "r" (reg14));
  19
  20     // CHECK: call void asm sideeffect "add $0,$1,$2", "{r30},{r30},{r30}"
  21     asm volatile("add %0,%1,%2" : : "r" (regI6), "r" (regFP), "r" (reg30));
  22
  23     // CHECK: call void asm sideeffect "fadds $0,$1,$2", "{f20},{f20},{f20}"
  24     asm volatile("fadds %0,%1,%2" : : "f" (fF20), "f" (fF20), "f"(fF20));
  25
  26     // CHECK: call void asm sideeffect "faddd $0,$1,$2", "{f40},{f40},{f40}"
  27     asm volatile("faddd %0,%1,%2" : : "f" (dF40), "f" (dF40), "f"(dF40));
  28
  29     // CHECK: call void asm sideeffect "faddq $0,$1,$2", "{f40},{f40},{f40}"
  30     asm volatile("faddq %0,%1,%2" : : "f" (qF40), "f" (qF40), "f"(qF40));
  31
  32 }