| blob | 500c6c7876944abbb7fdf23b464b3f5e394022ac |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse2 | FileCheck %s --check-prefix=X64
3 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=sse2 | FileCheck %s --check-prefix=X32
4 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefix=X32AVX
6 ; Use movq or movsd to load / store i64 values if sse2 is available.
7 ; rdar://6659858
9 define void @foo(ptr %x, ptr %y) {
10 ; X64-LABEL: foo:
11 ; X64: # %bb.0:
12 ; X64-NEXT: movq (%rsi), %rax
13 ; X64-NEXT: movq %rax, (%rdi)
14 ; X64-NEXT: retq
15 ;
16 ; X32-LABEL: foo:
17 ; X32: # %bb.0:
18 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
19 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
20 ; X32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
21 ; X32-NEXT: movsd %xmm0, (%eax)
22 ; X32-NEXT: retl
23 ;
24 ; X32AVX-LABEL: foo:
25 ; X32AVX: # %bb.0:
26 ; X32AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
27 ; X32AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx
28 ; X32AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
29 ; X32AVX-NEXT: vmovsd %xmm0, (%eax)
30 ; X32AVX-NEXT: retl
31 %tmp1 = load i64, ptr %y, align 8
32 store i64 %tmp1, ptr %x, align 8
33 ret void
34 }
36 ; Verify that a 64-bit chunk extracted from a vector is stored with a movq
37 ; regardless of whether the system is 64-bit.
39 define void @store_i64_from_vector(<8 x i16> %x, <8 x i16> %y, ptr %i) {
40 ; X64-LABEL: store_i64_from_vector:
41 ; X64: # %bb.0:
42 ; X64-NEXT: paddw %xmm1, %xmm0
43 ; X64-NEXT: movq %xmm0, (%rdi)
44 ; X64-NEXT: retq
45 ;
46 ; X32-LABEL: store_i64_from_vector:
47 ; X32: # %bb.0:
48 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
49 ; X32-NEXT: paddw %xmm1, %xmm0
50 ; X32-NEXT: movq %xmm0, (%eax)
51 ; X32-NEXT: retl
52 ;
53 ; X32AVX-LABEL: store_i64_from_vector:
54 ; X32AVX: # %bb.0:
55 ; X32AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
56 ; X32AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
57 ; X32AVX-NEXT: vmovq %xmm0, (%eax)
58 ; X32AVX-NEXT: retl
59 %z = add <8 x i16> %x, %y ; force execution domain
60 %bc = bitcast <8 x i16> %z to <2 x i64>
61 %vecext = extractelement <2 x i64> %bc, i32 0
62 store i64 %vecext, ptr %i, align 8
63 ret void
64 }
66 define void @store_i64_from_vector256(<16 x i16> %x, <16 x i16> %y, ptr %i) {
67 ; X64-LABEL: store_i64_from_vector256:
68 ; X64: # %bb.0:
69 ; X64-NEXT: paddw %xmm3, %xmm1
70 ; X64-NEXT: movq %xmm1, (%rdi)
71 ; X64-NEXT: retq
72 ;
73 ; X32-LABEL: store_i64_from_vector256:
74 ; X32: # %bb.0:
75 ; X32-NEXT: pushl %ebp
76 ; X32-NEXT: .cfi_def_cfa_offset 8
77 ; X32-NEXT: .cfi_offset %ebp, -8
78 ; X32-NEXT: movl %esp, %ebp
79 ; X32-NEXT: .cfi_def_cfa_register %ebp
80 ; X32-NEXT: andl $-16, %esp
81 ; X32-NEXT: subl $16, %esp
82 ; X32-NEXT: movl 24(%ebp), %eax
83 ; X32-NEXT: paddw 8(%ebp), %xmm1
84 ; X32-NEXT: movq %xmm1, (%eax)
85 ; X32-NEXT: movl %ebp, %esp
86 ; X32-NEXT: popl %ebp
87 ; X32-NEXT: .cfi_def_cfa %esp, 4
88 ; X32-NEXT: retl
89 ;
90 ; X32AVX-LABEL: store_i64_from_vector256:
91 ; X32AVX: # %bb.0:
92 ; X32AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
93 ; X32AVX-NEXT: vextracti128 $1, %ymm1, %xmm1
94 ; X32AVX-NEXT: vextracti128 $1, %ymm0, %xmm0
95 ; X32AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
96 ; X32AVX-NEXT: vmovq %xmm0, (%eax)
97 ; X32AVX-NEXT: vzeroupper
98 ; X32AVX-NEXT: retl
99 %z = add <16 x i16> %x, %y ; force execution domain
100 %bc = bitcast <16 x i16> %z to <4 x i64>
101 %vecext = extractelement <4 x i64> %bc, i32 2
102 store i64 %vecext, ptr %i, align 8
103 ret void
104 }
106 ; PR23476
107 ; Handle extraction from a non-simple / pre-legalization type.
109 define void @PR23476(<5 x i64> %in, ptr %out, i32 %index) nounwind {
110 ; X64-LABEL: PR23476:
111 ; X64: # %bb.0:
112 ; X64-NEXT: movq %rsi, %xmm0
113 ; X64-NEXT: movq %rdi, %xmm1
114 ; X64-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
115 ; X64-NEXT: movq %rcx, %xmm0
116 ; X64-NEXT: movq %rdx, %xmm2
117 ; X64-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0]
118 ; X64-NEXT: movl {{[0-9]+}}(%rsp), %eax
119 ; X64-NEXT: andl $7, %eax
120 ; X64-NEXT: movq %r8, %xmm0
121 ; X64-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)
122 ; X64-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)
123 ; X64-NEXT: movdqa %xmm1, -{{[0-9]+}}(%rsp)
124 ; X64-NEXT: movq -72(%rsp,%rax,8), %rax
125 ; X64-NEXT: movq %rax, (%r9)
126 ; X64-NEXT: retq
127 ;
128 ; X32-LABEL: PR23476:
129 ; X32: # %bb.0:
130 ; X32-NEXT: pushl %ebp
131 ; X32-NEXT: movl %esp, %ebp
132 ; X32-NEXT: andl $-16, %esp
133 ; X32-NEXT: subl $80, %esp
134 ; X32-NEXT: movl 52(%ebp), %eax
135 ; X32-NEXT: andl $7, %eax
136 ; X32-NEXT: movl 48(%ebp), %ecx
137 ; X32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
138 ; X32-NEXT: movups 8(%ebp), %xmm1
139 ; X32-NEXT: movups 24(%ebp), %xmm2
140 ; X32-NEXT: movaps %xmm2, {{[0-9]+}}(%esp)
141 ; X32-NEXT: movaps %xmm1, (%esp)
142 ; X32-NEXT: movaps %xmm0, {{[0-9]+}}(%esp)
143 ; X32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
144 ; X32-NEXT: movsd %xmm0, (%ecx)
145 ; X32-NEXT: movl %ebp, %esp
146 ; X32-NEXT: popl %ebp
147 ; X32-NEXT: retl
148 ;
149 ; X32AVX-LABEL: PR23476:
150 ; X32AVX: # %bb.0:
151 ; X32AVX-NEXT: pushl %ebp
152 ; X32AVX-NEXT: movl %esp, %ebp
153 ; X32AVX-NEXT: andl $-32, %esp
154 ; X32AVX-NEXT: subl $96, %esp
155 ; X32AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
156 ; X32AVX-NEXT: movl 52(%ebp), %eax
157 ; X32AVX-NEXT: andl $7, %eax
158 ; X32AVX-NEXT: movl 48(%ebp), %ecx
159 ; X32AVX-NEXT: vmovups 8(%ebp), %ymm1
160 ; X32AVX-NEXT: vmovaps %ymm1, (%esp)
161 ; X32AVX-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
162 ; X32AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
163 ; X32AVX-NEXT: vmovsd %xmm0, (%ecx)
164 ; X32AVX-NEXT: movl %ebp, %esp
165 ; X32AVX-NEXT: popl %ebp
166 ; X32AVX-NEXT: vzeroupper
167 ; X32AVX-NEXT: retl
168 %ext = extractelement <5 x i64> %in, i32 %index
169 store i64 %ext, ptr %out, align 8
170 ret void
171 }