| blob | 73bdae71654f12e07b8bd26144152758c7430fc6 |
1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
2 ; RUN: opt -S -passes=loop-vectorize < %s | FileCheck %s
3 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
4 target triple = "x86_64-unknown-linux-gnu"
6 ; PR 81872 explains the issue.
8 ; If we vectorize, we have a miscompile where array IV and thereby value stored in (arr[99],
9 ; arr[98]) is calculated incorrectly since disjoint or was only disjoint because
10 ; of dominating conditions. Dropping the disjoint to avoid poison still changes
11 ; the behaviour since now the or is no longer equivalent to the add.
12 ;
13 define void @test(ptr noundef align 8 dereferenceable_or_null(16) %arr) #0 {
14 ; CHECK-LABEL: define void @test(
15 ; CHECK-SAME: ptr noundef align 8 dereferenceable_or_null(16) [[ARR:%.*]]) #[[ATTR0:[0-9]+]] {
16 ; CHECK-NEXT: bb5:
17 ; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]], !prof [[PROF0:![0-9]+]]
18 ; CHECK: vector.ph:
19 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
20 ; CHECK: vector.body:
21 ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
22 ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 99, i64 98, i64 97, i64 96>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
23 ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = sub i64 99, [[INDEX]]
24 ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0
25 ; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[INDEX]], i64 0
26 ; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer
27 ; CHECK-NEXT: [[VEC_IV:%.*]] = add <4 x i64> [[BROADCAST_SPLAT]], <i64 0, i64 1, i64 2, i64 3>
28 ; CHECK-NEXT: [[TMP1:%.*]] = icmp ule <4 x i64> [[VEC_IV]], splat (i64 8)
29 ; CHECK-NEXT: [[TMP2:%.*]] = and <4 x i64> [[VEC_IND]], splat (i64 1)
30 ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq <4 x i64> [[TMP2]], zeroinitializer
31 ; CHECK-NEXT: [[TMP4:%.*]] = select <4 x i1> [[TMP1]], <4 x i1> [[TMP3]], <4 x i1> zeroinitializer
32 ; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[TMP0]], 1
33 ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i64, ptr [[ARR]], i64 [[TMP5]]
34 ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i64, ptr [[TMP6]], i32 0
35 ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[TMP7]], i32 -3
36 ; CHECK-NEXT: [[REVERSE:%.*]] = shufflevector <4 x i1> [[TMP4]], <4 x i1> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
37 ; CHECK-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> splat (i64 1), ptr [[TMP8]], i32 8, <4 x i1> [[REVERSE]])
38 ; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4
39 ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], splat (i64 -4)
40 ; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], 12
41 ; CHECK-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !prof [[PROF1:![0-9]+]], !llvm.loop [[LOOP2:![0-9]+]]
42 ; CHECK: middle.block:
43 ; CHECK-NEXT: br i1 true, label [[BB6:%.*]], label [[SCALAR_PH]], !prof [[PROF5:![0-9]+]]
44 ; CHECK: scalar.ph:
45 ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 87, [[MIDDLE_BLOCK]] ], [ 99, [[BB5:%.*]] ]
46 ; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
47 ; CHECK: loop.header:
48 ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]
49 ; CHECK-NEXT: [[AND:%.*]] = and i64 [[IV]], 1
50 ; CHECK-NEXT: [[ICMP17:%.*]] = icmp eq i64 [[AND]], 0
51 ; CHECK-NEXT: br i1 [[ICMP17]], label [[BB18:%.*]], label [[LOOP_LATCH]], !prof [[PROF6:![0-9]+]]
52 ; CHECK: bb18:
53 ; CHECK-NEXT: [[OR:%.*]] = or disjoint i64 [[IV]], 1
54 ; CHECK-NEXT: [[GETELEMENTPTR19:%.*]] = getelementptr inbounds i64, ptr [[ARR]], i64 [[OR]]
55 ; CHECK-NEXT: store i64 1, ptr [[GETELEMENTPTR19]], align 8
56 ; CHECK-NEXT: br label [[LOOP_LATCH]]
57 ; CHECK: loop.latch:
58 ; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], -1
59 ; CHECK-NEXT: [[ICMP22:%.*]] = icmp eq i64 [[IV_NEXT]], 90
60 ; CHECK-NEXT: br i1 [[ICMP22]], label [[BB6]], label [[LOOP_HEADER]], !prof [[PROF7:![0-9]+]], !llvm.loop [[LOOP8:![0-9]+]]
61 ; CHECK: bb6:
62 ; CHECK-NEXT: ret void
63 ;
64 bb5:
65 br label %loop.header
67 loop.header: ; preds = %loop.latch, %bb8
68 %iv = phi i64 [ 99, %bb5 ], [ %iv.next, %loop.latch ]
69 %and = and i64 %iv, 1
70 %icmp17 = icmp eq i64 %and, 0
71 br i1 %icmp17, label %bb18, label %loop.latch, !prof !21
73 bb18: ; preds = %loop.header
74 %or = or disjoint i64 %iv, 1
75 %getelementptr19 = getelementptr inbounds i64, ptr %arr, i64 %or
76 store i64 1, ptr %getelementptr19, align 8
77 br label %loop.latch
79 loop.latch: ; preds = %bb18, %loop.header
80 %iv.next = add nsw i64 %iv, -1
81 %icmp22 = icmp eq i64 %iv.next, 90
82 br i1 %icmp22, label %bb6, label %loop.header, !prof !22
84 bb6:
85 ret void
86 }
88 attributes #0 = {"target-cpu"="haswell" "target-features"="+avx2" }
90 !4 = !{}
91 !10 = !{i32 1}
92 !16 = !{i64 864}
93 !17 = !{i64 8}
94 !21 = !{!"branch_weights", i32 1, i32 1}
95 !22 = !{!"branch_weights", i32 1, i32 95}
98 ;.
99 ; CHECK: [[PROF0]] = !{!"branch_weights", i32 1, i32 127}
100 ; CHECK: [[PROF1]] = !{!"branch_weights", i32 1, i32 23}
101 ; CHECK: [[LOOP2]] = distinct !{[[LOOP2]], [[META3:![0-9]+]], [[META4:![0-9]+]]}
102 ; CHECK: [[META3]] = !{!"llvm.loop.isvectorized", i32 1}
103 ; CHECK: [[META4]] = !{!"llvm.loop.unroll.runtime.disable"}
104 ; CHECK: [[PROF5]] = !{!"branch_weights", i32 1, i32 3}
105 ; CHECK: [[PROF6]] = !{!"branch_weights", i32 1, i32 1}
106 ; CHECK: [[PROF7]] = !{!"branch_weights", i32 0, i32 0}
107 ; CHECK: [[LOOP8]] = distinct !{[[LOOP8]], [[META4]], [[META3]]}
108 ;.