flang/test/Lower/PowerPC/ppc-vec-store-elem-order.f90

   1 ! RUN: %flang_fc1 -emit-fir %s -fno-ppc-native-vector-element-order -triple ppc64le-unknown-linux -o - | FileCheck --check-prefixes="FIR" %s
   2 ! RUN: %flang_fc1 -emit-llvm %s -fno-ppc-native-vector-element-order -triple ppc64le-unknown-linux -o - | FileCheck --check-prefixes="LLVMIR" %s
   3 ! REQUIRES: target=powerpc{{.*}}
   4
   5 !----------------------
   6 ! vec_st
   7 !----------------------
   8 ! CHECK-LABEL: vec_st_test
   9 subroutine vec_st_test(arg1, arg2, arg3)
  10   vector(integer(2)) :: arg1
  11   integer(4) :: arg2
  12   vector(integer(2)) :: arg3
  13   call vec_st(arg1, arg2, arg3)
  14
  15 ! FIR: %[[arg1:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<8:i16>>
  16 ! FIR: %[[arg2:.*]] = fir.load %arg1 : !fir.ref<i32>
  17 ! FIR: %[[arg3:.*]] = fir.convert %arg2 : (!fir.ref<!fir.vector<8:i16>>) -> !fir.ref<!fir.array<?xi8>>
  18 ! FIR: %[[addr:.*]] = fir.coordinate_of %[[arg3]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i32) -> !fir.ref<!fir.array<?xi8>>
  19 ! FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<8:i16>) -> vector<8xi16>
  20 ! FIR: %[[bc:.*]] = vector.bitcast %[[varg1]] : vector<8xi16> to vector<4xi32>
  21 ! FIR: %[[ordr:.*]] = fir.undefined vector<4xi32>
  22 ! FIR: %[[shf:.*]] = vector.shuffle %[[bc]], %[[ordr]] [3, 2, 1, 0] : vector<4xi32>, vector<4xi32>
  23 ! FIR: fir.call @llvm.ppc.altivec.stvx(%[[shf]], %[[addr]]) fastmath<contract> : (vector<4xi32>, !fir.ref<!fir.array<?xi8>>) -> ()
  24
  25 ! LLVMIR: %[[arg1:.*]] = load <8 x i16>, ptr %0, align 16
  26 ! LLVMIR: %[[arg2:.*]] = load i32, ptr %1, align 4
  27 ! LLVMIR: %[[addr:.*]] = getelementptr i8, ptr %2, i32 %[[arg2]]
  28 ! LLVMIR: %[[bc:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32>
  29 ! LLVMIR: %[[shf:.*]] = shufflevector <4 x i32> %[[bc]], <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
  30 ! LLVMIR:  call void @llvm.ppc.altivec.stvx(<4 x i32> %[[shf]], ptr %[[addr]])
  31 end subroutine vec_st_test
  32
  33 !----------------------
  34 ! vec_ste
  35 !----------------------
  36 ! CHECK-LABEL: vec_ste_test
  37 subroutine vec_ste_test(arg1, arg2, arg3)
  38   vector(real(4)) :: arg1
  39   integer(4) :: arg2
  40   real(4) :: arg3
  41   call vec_ste(arg1, arg2, arg3)
  42
  43 ! FIR: %[[arg1:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<4:f32>>
  44 ! FIR: %[[arg2:.*]] = fir.load %arg1 : !fir.ref<i32>
  45 ! FIR: %[[arg3:.*]] = fir.convert %arg2 : (!fir.ref<f32>) -> !fir.ref<!fir.array<?xi8>>
  46 ! FIR: %[[addr:.*]] = fir.coordinate_of %[[arg3]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i32) -> !fir.ref<!fir.array<?xi8>>
  47 ! FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<4:f32>) -> vector<4xf32>
  48 ! FIR: %[[bc:.*]] = vector.bitcast %[[varg1]] : vector<4xf32> to vector<4xi32>
  49 ! FIR: %[[ordr:.*]] = fir.undefined vector<4xi32>
  50 ! FIR: %[[shf:.*]] = vector.shuffle %[[bc]], %[[ordr]] [3, 2, 1, 0] : vector<4xi32>, vector<4xi32>
  51 ! FIR: fir.call @llvm.ppc.altivec.stvewx(%[[shf]], %[[addr]]) fastmath<contract> : (vector<4xi32>, !fir.ref<!fir.array<?xi8>>) -> ()
  52
  53 ! LLVMIR: %[[arg1:.*]] = load <4 x float>, ptr %0, align 16
  54 ! LLVMIR: %[[arg2:.*]] = load i32, ptr %1, align 4
  55 ! LLVMIR: %[[addr]] = getelementptr i8, ptr %2, i32 %[[arg2]]
  56 ! LLVMIR: %[[bc:.*]] = bitcast <4 x float> %[[arg1]] to <4 x i32>
  57 ! LLVMIR: %[[shf:.*]] = shufflevector <4 x i32> %[[bc]], <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
  58 ! LLVMIR: call void @llvm.ppc.altivec.stvewx(<4 x i32> %[[shf]], ptr %[[addr]])
  59 end subroutine vec_ste_test
  60
  61 !----------------------
  62 ! vec_xst
  63 !----------------------
  64 ! CHECK-LABEL: vec_xst_test
  65 subroutine vec_xst_test(arg1, arg2, arg3)
  66   vector(integer(4)) :: arg1
  67   integer(4) :: arg2
  68   vector(integer(4)) :: arg3
  69   call vec_xst(arg1, arg2, arg3)
  70
  71 ! FIR: %[[arg1:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<4:i32>>
  72 ! FIR: %[[arg2:.*]] = fir.load %arg1 : !fir.ref<i32>
  73 ! FIR: %[[arg3:.*]] = fir.convert %arg2 : (!fir.ref<!fir.vector<4:i32>>) -> !fir.ref<!fir.array<?xi8>>
  74 ! FIR: %[[addr:.*]] = fir.coordinate_of %[[arg3]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i32) -> !fir.ref<!fir.array<?xi8>>
  75 ! FIR: %[[trg:.*]] = fir.convert %[[addr]] : (!fir.ref<!fir.array<?xi8>>) -> !fir.ref<!fir.vector<4:i32>>
  76 ! FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<4:i32>) -> vector<4xi32>
  77 ! FIR: %[[ordr:.*]] = fir.undefined vector<4xi32>
  78 ! FIR: %[[shf:.*]] = vector.shuffle %[[varg1]], %[[ordr]] [3, 2, 1, 0] : vector<4xi32>, vector<4xi32>
  79 ! FIR: %[[src:.*]] = fir.convert %[[shf]] : (vector<4xi32>) -> !fir.vector<4:i32>
  80 ! FIR: fir.store %[[src]] to %[[trg]] {alignment = 1 : i64} : !fir.ref<!fir.vector<4:i32>>
  81
  82 ! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
  83 ! LLVMIR: %[[arg2:.*]] = load i32, ptr %1, align 4
  84 ! LLVMIR: %[[trg:.*]] = getelementptr i8, ptr %2, i32 %[[arg2]]
  85 ! LLVMIR: %[[src:.*]] = shufflevector <4 x i32> %[[arg1]], <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
  86 ! LLVMIR:  store <4 x i32> %[[src]], ptr %[[trg]], align 1
  87 end subroutine vec_xst_test
  88
  89 !----------------------
  90 ! vec_xstd2
  91 !----------------------
  92 ! CHECK-LABEL: vec_xstd2_test
  93 subroutine vec_xstd2_test(arg1, arg2, arg3, i)
  94   vector(real(4)) :: arg1
  95   integer(2) :: arg2
  96   vector(real(4)) :: arg3(*)
  97   integer(4) :: i
  98   call vec_xstd2(arg1, arg2, arg3(i))
  99
 100 ! FIR: %[[arg1:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<4:f32>>
 101 ! FIR: %[[arg2:.*]] = fir.load %arg1 : !fir.ref<i16>
 102 ! FIR: %[[arg4:.*]] = fir.load %arg3 : !fir.ref<i32>
 103 ! FIR: %[[arg4_64:.*]] = fir.convert %[[arg4]] : (i32) -> i64
 104 ! FIR: %[[one:.*]] = arith.constant 1 : i64
 105 ! FIR: %[[idx:.*]] = arith.subi %[[arg4_64]], %[[one]] : i64
 106 ! FIR: %[[elemaddr:.*]] = fir.coordinate_of %arg2, %[[idx]] : (!fir.ref<!fir.array<?x!fir.vector<4:f32>>>, i64) -> !fir.ref<!fir.vector<4:f32>>
 107 ! FIR: %[[elemptr:.*]] = fir.convert %[[elemaddr]] : (!fir.ref<!fir.vector<4:f32>>) -> !fir.ref<!fir.array<?xi8>>
 108 ! FIR: %[[addr:.*]] = fir.coordinate_of %[[elemptr]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i16) -> !fir.ref<!fir.array<?xi8>>
 109 ! FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<4:f32>) -> vector<4xf32>
 110 ! FIR: %[[v2elem:.*]] = vector.bitcast %[[varg1]] : vector<4xf32> to vector<2xi64>
 111 ! FIR: %[[trg:.*]] = fir.convert %[[addr]] : (!fir.ref<!fir.array<?xi8>>) -> !fir.ref<!fir.vector<2:i64>>
 112 ! FIR: %[[undef:.*]] = fir.undefined vector<2xi64>
 113 ! FIR: %[[shf:.*]] = vector.shuffle %[[v2elem]], %[[undef]] [1, 0] : vector<2xi64>, vector<2xi64>
 114 ! FIR: %[[src:.*]] = fir.convert %[[shf]] : (vector<2xi64>) -> !fir.vector<2:i64>
 115 ! FIR: fir.store %[[src]] to %[[trg]] {alignment = 1 : i64} : !fir.ref<!fir.vector<2:i64>>
 116
 117 ! LLVMIR: %[[arg1:.*]] = load <4 x float>, ptr %0, align 16
 118 ! LLVMIR: %[[arg2:.*]] = load i16, ptr %1, align 2
 119 ! LLVMIR: %[[arg4:.*]] = load i32, ptr %3, align 4
 120 ! LLVMIR: %[[arg4_64:.*]] = sext i32 %[[arg4]] to i64
 121 ! LLVMIR: %[[idx:.*]] = sub i64 %[[arg4_64]], 1
 122 ! LLVMIR: %[[elemptr:.*]] = getelementptr <4 x float>, ptr %2, i64 %[[idx]]
 123 ! LLVMIR: %[[trg:.*]] = getelementptr i8, ptr %[[elemptr]], i16 %[[arg2]]
 124 ! LLVMIR: %[[v2elem:.*]] = bitcast <4 x float> %[[arg1]] to <2 x i64>
 125 ! LLVMIR: %[[src:.*]] = shufflevector <2 x i64> %[[v2elem]], <2 x i64> undef, <2 x i32> <i32 1, i32 0>
 126 ! LLVMIR: store <2 x i64> %[[src]], ptr %[[trg]], align 1
 127 end subroutine vec_xstd2_test
 128
 129 !----------------------
 130 ! vec_xstw4
 131 !----------------------
 132 ! CHECK-LABEL: vec_xstw4_test
 133 subroutine vec_xstw4_test(arg1, arg2, arg3, i)
 134   vector(real(4)) :: arg1
 135   integer(2) :: arg2
 136   vector(real(4)) :: arg3(*)
 137   integer(4) :: i
 138   call vec_xstw4(arg1, arg2, arg3(i))
 139
 140 ! FIR: %[[arg1:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<4:f32>>
 141 ! FIR: %[[arg2:.*]] = fir.load %arg1 : !fir.ref<i16>
 142 ! FIR: %[[arg4:.*]] = fir.load %arg3 : !fir.ref<i32>
 143 ! FIR: %[[arg4_64:.*]] = fir.convert %[[arg4]] : (i32) -> i64
 144 ! FIR: %[[one:.*]] = arith.constant 1 : i64
 145 ! FIR: %[[idx:.*]] = arith.subi %[[arg4_64]], %[[one]] : i64
 146 ! FIR: %[[elemaddr:.*]] = fir.coordinate_of %arg2, %[[idx]] : (!fir.ref<!fir.array<?x!fir.vector<4:f32>>>, i64) -> !fir.ref<!fir.vector<4:f32>>
 147 ! FIR: %[[elemptr:.*]] = fir.convert %[[elemaddr]] : (!fir.ref<!fir.vector<4:f32>>) -> !fir.ref<!fir.array<?xi8>>
 148 ! FIR: %[[addr:.*]] = fir.coordinate_of %[[elemptr]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i16) -> !fir.ref<!fir.array<?xi8>>
 149 ! FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<4:f32>) -> vector<4xf32>
 150 ! FIR: %[[trg:.*]] = fir.convert %[[addr]] : (!fir.ref<!fir.array<?xi8>>) -> !fir.ref<!fir.vector<4:f32>>
 151 ! FIR: %[[undef:.*]] = fir.undefined vector<4xf32>
 152 ! FIR: %[[shf:.*]] = vector.shuffle %[[varg1]], %[[undef]] [3, 2, 1, 0] : vector<4xf32>, vector<4xf32>
 153 ! FIR: %[[src:.*]] = fir.convert %[[shf]] : (vector<4xf32>) -> !fir.vector<4:f32>
 154 ! FIR: fir.store %[[src]] to %[[trg]] {alignment = 1 : i64} : !fir.ref<!fir.vector<4:f32>>
 155
 156 ! LLVMIR: %[[arg1:.*]] = load <4 x float>, ptr %0, align 16
 157 ! LLVMIR: %[[arg2:.*]] = load i16, ptr %1, align 2
 158 ! LLVMIR: %[[arg4:.*]] = load i32, ptr %3, align 4
 159 ! LLVMIR: %[[arg4_64:.*]] = sext i32 %[[arg4]] to i64
 160 ! LLVMIR: %[[idx:.*]] = sub i64 %[[arg4_64]], 1
 161 ! LLVMIR: %[[elemptr:.*]] = getelementptr <4 x float>, ptr %2, i64 %[[idx]]
 162 ! LLVMIR: %[[trg:.*]] = getelementptr i8, ptr %[[elemptr]], i16 %[[arg2]]
 163 ! LLVMIR: %[[src:.*]] = shufflevector <4 x float> %[[arg1]], <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
 164 ! LLVMIR: store <4 x float> %[[src]], ptr %[[trg]], align 1
 165 end subroutine vec_xstw4_test