flang/test/Lower/PowerPC/ppc-vec-store.f90

   1 ! RUN: bbc -emit-fir %s -o - | FileCheck --check-prefixes="CHECK-FIR" %s
   2 ! RUN: %flang_fc1 -emit-fir %s -o - | fir-opt --fir-to-llvm-ir | FileCheck --check-prefixes="CHECK-LLVMIR" %s
   3 ! RUN: %flang_fc1 -emit-llvm %s -o - | FileCheck --check-prefixes="CHECK" %s
   4 ! REQUIRES: target=powerpc{{.*}}
   5
   6 !----------------------
   7 ! vec_st
   8 !----------------------
   9
  10 ! CHECK-LABEL: vec_st_vi1i2vi1
  11 subroutine vec_st_vi1i2vi1(arg1, arg2, arg3)
  12   vector(integer(1)) :: arg1, arg3
  13   integer(2) :: arg2
  14   call vec_st(arg1, arg2, arg3)
  15
  16 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:i8>>
  17 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<i16>
  18 ! CHECK-FIR: %[[arg3:.*]] = fir.convert %{{.*}} : (!fir.ref<!fir.vector<16:i8>>) -> !fir.ref<!fir.array<?xi8>>
  19 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[arg3]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i16) -> !fir.ref<!fir.array<?xi8>>
  20 ! CHECK-FIR: %[[cnvArg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<16:i8>) -> vector<16xi8>
  21 ! CHECK-FIR: %[[bcArg1:.*]] = vector.bitcast %[[cnvArg1]] : vector<16xi8> to vector<4xi32>
  22 ! CHECK-FIR: fir.call @llvm.ppc.altivec.stvx(%[[bcArg1]], %[[addr]]) fastmath<contract> : (vector<4xi32>, !fir.ref<!fir.array<?xi8>>) -> ()
  23
  24 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>>
  25 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<i16>
  26 ! CHECK-LLVMIR: %[[arg3:.*]] = llvm.bitcast %{{.*}} : !llvm.ptr<vector<16xi8>> to !llvm.ptr<i8>
  27 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[arg3]][%[[arg2]]] : (!llvm.ptr<i8>, i16) -> !llvm.ptr<i8>
  28 ! CHECK-LLVMIR: %[[bcArg1:.*]] = llvm.bitcast %[[arg1]] : vector<16xi8> to vector<4xi32>
  29 ! CHECK-LLVMIR: llvm.call @llvm.ppc.altivec.stvx(%[[bcArg1]], %[[addr]]) {fastmathFlags = #llvm.fastmath<contract>} : (vector<4xi32>, !llvm.ptr<i8>) -> ()
  30
  31 ! CHECK: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16
  32 ! CHECK: %[[arg2:.*]] = load i16, ptr %{{.*}}, align 2
  33 ! CHECK: %[[arg3:.*]] = getelementptr i8, ptr %{{.*}}, i16 %5
  34 ! CHECK: %[[bcArg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32>
  35 ! CHECK: call void @llvm.ppc.altivec.stvx(<4 x i32> %[[bcArg1]], ptr %[[arg3]])
  36 end subroutine vec_st_vi1i2vi1
  37
  38 ! CHECK-LABEL: vec_st_vi2i2vi2
  39 subroutine vec_st_vi2i2vi2(arg1, arg2, arg3)
  40   vector(integer(2)) :: arg1, arg3
  41   integer(2) :: arg2
  42   call vec_st(arg1, arg2, arg3)
  43
  44 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:i16>>
  45 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<i16>
  46 ! CHECK-FIR: %[[arg3:.*]] = fir.convert %{{.*}} : (!fir.ref<!fir.vector<8:i16>>) -> !fir.ref<!fir.array<?xi8>>
  47 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[arg3]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i16) -> !fir.ref<!fir.array<?xi8>>
  48 ! CHECK-FIR: %[[cnvArg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<8:i16>) -> vector<8xi16>
  49 ! CHECK-FIR: %[[bcArg1:.*]] = vector.bitcast %[[cnvArg1]] : vector<8xi16> to vector<4xi32>
  50 ! CHECK-FIR: fir.call @llvm.ppc.altivec.stvx(%[[bcArg1]], %[[addr]]) fastmath<contract> : (vector<4xi32>, !fir.ref<!fir.array<?xi8>>) -> ()
  51
  52 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>>
  53 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<i16>
  54 ! CHECK-LLVMIR: %[[arg3:.*]] = llvm.bitcast %{{.*}} : !llvm.ptr<vector<8xi16>> to !llvm.ptr<i8>
  55 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[arg3]][%[[arg2]]] : (!llvm.ptr<i8>, i16) -> !llvm.ptr<i8>
  56 ! CHECK-LLVMIR: %[[bcArg1:.*]] = llvm.bitcast %[[arg1]] : vector<8xi16> to vector<4xi32>
  57 ! CHECK-LLVMIR: llvm.call @llvm.ppc.altivec.stvx(%[[bcArg1]], %[[addr]]) {fastmathFlags = #llvm.fastmath<contract>} : (vector<4xi32>, !llvm.ptr<i8>) -> ()
  58
  59 ! CHECK: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16
  60 ! CHECK: %[[arg2:.*]] = load i16, ptr %{{.*}}, align 2
  61 ! CHECK: %[[arg3:.*]] = getelementptr i8, ptr %{{.*}}, i16 %5
  62 ! CHECK: %[[bcArg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32>
  63 ! CHECK: call void @llvm.ppc.altivec.stvx(<4 x i32> %[[bcArg1]], ptr %[[arg3]])
  64 end subroutine vec_st_vi2i2vi2
  65
  66 ! CHECK-LABEL: vec_st_vi4i2vi4
  67 subroutine vec_st_vi4i2vi4(arg1, arg2, arg3)
  68   vector(integer(4)) :: arg1, arg3
  69   integer(2) :: arg2
  70   call vec_st(arg1, arg2, arg3)
  71
  72 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:i32>>
  73 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<i16>
  74 ! CHECK-FIR: %[[arg3:.*]] = fir.convert %{{.*}} : (!fir.ref<!fir.vector<4:i32>>) -> !fir.ref<!fir.array<?xi8>>
  75 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[arg3]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i16) -> !fir.ref<!fir.array<?xi8>>
  76 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<4:i32>) -> vector<4xi32>
  77 ! CHECK-FIR: fir.call @llvm.ppc.altivec.stvx(%[[varg1]], %[[addr]]) fastmath<contract> : (vector<4xi32>, !fir.ref<!fir.array<?xi8>>) -> ()
  78
  79 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>>
  80 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<i16>
  81 ! CHECK-LLVMIR: %[[arg3:.*]] = llvm.bitcast %{{.*}} : !llvm.ptr<vector<4xi32>> to !llvm.ptr<i8>
  82 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[arg3]][%[[arg2]]] : (!llvm.ptr<i8>, i16) -> !llvm.ptr<i8>
  83 ! CHECK-LLVMIR: llvm.call @llvm.ppc.altivec.stvx(%[[arg1]], %[[addr]]) {fastmathFlags = #llvm.fastmath<contract>} : (vector<4xi32>, !llvm.ptr<i8>) -> ()
  84
  85 ! CHECK: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16
  86 ! CHECK: %[[arg2:.*]] = load i16, ptr %{{.*}}, align 2
  87 ! CHECK: %[[arg3:.*]] = getelementptr i8, ptr %{{.*}}, i16 %5
  88 ! CHECK: call void @llvm.ppc.altivec.stvx(<4 x i32> %[[arg1]], ptr %[[arg3]])
  89 end subroutine vec_st_vi4i2vi4
  90
  91 ! CHECK-LABEL: vec_st_vu1i4vu1
  92 subroutine vec_st_vu1i4vu1(arg1, arg2, arg3)
  93   vector(unsigned(1)) :: arg1, arg3
  94   integer(4) :: arg2
  95   call vec_st(arg1, arg2, arg3)
  96
  97 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:ui8>>
  98 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<i32>
  99 ! CHECK-FIR: %[[arg3:.*]] = fir.convert %{{.*}} : (!fir.ref<!fir.vector<16:ui8>>) -> !fir.ref<!fir.array<?xi8>>
 100 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[arg3]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i32) -> !fir.ref<!fir.array<?xi8>>
 101 ! CHECK-FIR: %[[cnvArg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<16:ui8>) -> vector<16xi8>
 102 ! CHECK-FIR: %[[bcArg1:.*]] = vector.bitcast %[[cnvArg1]] : vector<16xi8> to vector<4xi32>
 103 ! CHECK-FIR: fir.call @llvm.ppc.altivec.stvx(%[[bcArg1]], %[[addr]]) fastmath<contract> : (vector<4xi32>, !fir.ref<!fir.array<?xi8>>) -> ()
 104
 105 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>>
 106 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<i32>
 107 ! CHECK-LLVMIR: %[[arg3:.*]] = llvm.bitcast %{{.*}} : !llvm.ptr<vector<16xi8>> to !llvm.ptr<i8>
 108 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[arg3]][%[[arg2]]] : (!llvm.ptr<i8>, i32) -> !llvm.ptr<i8>
 109 ! CHECK-LLVMIR: %[[bcArg1:.*]] = llvm.bitcast %[[arg1]] : vector<16xi8> to vector<4xi32>
 110 ! CHECK-LLVMIR: llvm.call @llvm.ppc.altivec.stvx(%[[bcArg1]], %[[addr]]) {fastmathFlags = #llvm.fastmath<contract>} : (vector<4xi32>, !llvm.ptr<i8>) -> ()
 111
 112 ! CHECK: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16
 113 ! CHECK: %[[arg2:.*]] = load i32, ptr %{{.*}}, align 4
 114 ! CHECK: %[[arg3:.*]] = getelementptr i8, ptr %{{.*}}, i32 %5
 115 ! CHECK: %[[bcArg1:.*]] = bitcast <16 x i8> %[[arg1]] to <4 x i32>
 116 ! CHECK: call void @llvm.ppc.altivec.stvx(<4 x i32> %[[bcArg1]], ptr %[[arg3]])
 117 end subroutine vec_st_vu1i4vu1
 118
 119 ! CHECK-LABEL: vec_st_vu2i4vu2
 120 subroutine vec_st_vu2i4vu2(arg1, arg2, arg3)
 121   vector(unsigned(2)) :: arg1, arg3
 122   integer(4) :: arg2
 123   call vec_st(arg1, arg2, arg3)
 124
 125 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:ui16>>
 126 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<i32>
 127 ! CHECK-FIR: %[[arg3:.*]] = fir.convert %{{.*}} : (!fir.ref<!fir.vector<8:ui16>>) -> !fir.ref<!fir.array<?xi8>>
 128 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[arg3]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i32) -> !fir.ref<!fir.array<?xi8>>
 129 ! CHECK-FIR: %[[cnvArg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<8:ui16>) -> vector<8xi16>
 130 ! CHECK-FIR: %[[bcArg1:.*]] = vector.bitcast %[[cnvArg1]] : vector<8xi16> to vector<4xi32>
 131 ! CHECK-FIR: fir.call @llvm.ppc.altivec.stvx(%[[bcArg1]], %[[addr]]) fastmath<contract> : (vector<4xi32>, !fir.ref<!fir.array<?xi8>>) -> ()
 132
 133 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>>
 134 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<i32>
 135 ! CHECK-LLVMIR: %[[arg3:.*]] = llvm.bitcast %{{.*}} : !llvm.ptr<vector<8xi16>> to !llvm.ptr<i8>
 136 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[arg3]][%[[arg2]]] : (!llvm.ptr<i8>, i32) -> !llvm.ptr<i8>
 137 ! CHECK-LLVMIR: %[[bcArg1:.*]] = llvm.bitcast %[[arg1]] : vector<8xi16> to vector<4xi32>
 138 ! CHECK-LLVMIR: llvm.call @llvm.ppc.altivec.stvx(%[[bcArg1]], %[[addr]]) {fastmathFlags = #llvm.fastmath<contract>} : (vector<4xi32>, !llvm.ptr<i8>) -> ()
 139
 140 ! CHECK: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16
 141 ! CHECK: %[[arg2:.*]] = load i32, ptr %{{.*}}, align 4
 142 ! CHECK: %[[arg3:.*]] = getelementptr i8, ptr %{{.*}}, i32 %5
 143 ! CHECK: %[[bcArg1:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32>
 144 ! CHECK: call void @llvm.ppc.altivec.stvx(<4 x i32> %[[bcArg1]], ptr %[[arg3]])
 145 end subroutine vec_st_vu2i4vu2
 146
 147 ! CHECK-LABEL: vec_st_vu4i4vu4
 148 subroutine vec_st_vu4i4vu4(arg1, arg2, arg3)
 149   vector(unsigned(4)) :: arg1, arg3
 150   integer(4) :: arg2
 151   call vec_st(arg1, arg2, arg3)
 152
 153 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:ui32>>
 154 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<i32>
 155 ! CHECK-FIR: %[[arg3:.*]] = fir.convert %{{.*}} : (!fir.ref<!fir.vector<4:ui32>>) -> !fir.ref<!fir.array<?xi8>>
 156 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[arg3]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i32) -> !fir.ref<!fir.array<?xi8>>
 157 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<4:ui32>) -> vector<4xi32>
 158 ! CHECK-FIR: fir.call @llvm.ppc.altivec.stvx(%[[varg1]], %[[addr]]) fastmath<contract> : (vector<4xi32>, !fir.ref<!fir.array<?xi8>>) -> ()
 159
 160 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>>
 161 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<i32>
 162 ! CHECK-LLVMIR: %[[arg3:.*]] = llvm.bitcast %{{.*}} : !llvm.ptr<vector<4xi32>> to !llvm.ptr<i8>
 163 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[arg3]][%[[arg2]]] : (!llvm.ptr<i8>, i32) -> !llvm.ptr<i8>
 164 ! CHECK-LLVMIR: llvm.call @llvm.ppc.altivec.stvx(%[[arg1]], %[[addr]]) {fastmathFlags = #llvm.fastmath<contract>} : (vector<4xi32>, !llvm.ptr<i8>) -> ()
 165
 166 ! CHECK: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16
 167 ! CHECK: %[[arg2:.*]] = load i32, ptr %{{.*}}, align 4
 168 ! CHECK: %[[arg3:.*]] = getelementptr i8, ptr %{{.*}}, i32 %5
 169 ! CHECK: call void @llvm.ppc.altivec.stvx(<4 x i32> %[[arg1]], ptr %[[arg3]])
 170 end subroutine vec_st_vu4i4vu4
 171
 172 ! CHECK-LABEL: vec_st_vi4i4via4
 173 subroutine vec_st_vi4i4via4(arg1, arg2, arg3, i)
 174   vector(integer(4)) :: arg1, arg3(5)
 175   integer(4) :: arg2, i
 176   call vec_st(arg1, arg2, arg3(i))
 177
 178 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:i32>>
 179 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<i32>
 180 ! CHECK-FIR: %[[idx:.*]] = fir.load %{{.*}} : !fir.ref<i32>
 181 ! CHECK-FIR: %[[idx64:.*]] = fir.convert %[[idx]] : (i32) -> i64
 182 ! CHECK-FIR: %[[cnst:.*]] = arith.constant 1 : i64
 183 ! CHECK-FIR: %[[cnstm1:.*]] = arith.subi %[[idx64]], %[[cnst]] : i64
 184 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %arg2, %[[cnstm1]] : (!fir.ref<!fir.array<5x!fir.vector<4:i32>>>, i64) -> !fir.ref<!fir.vector<4:i32>>
 185 ! CHECK-FIR: %[[ref:.*]] = fir.convert %[[addr]] : (!fir.ref<!fir.vector<4:i32>>) -> !fir.ref<!fir.array<?xi8>>
 186 ! CHECK-FIR: %[[pos:.*]] = fir.coordinate_of %[[ref]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i32) -> !fir.ref<!fir.array<?xi8>>
 187 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<4:i32>) -> vector<4xi32>
 188 ! CHECK-FIR: fir.call @llvm.ppc.altivec.stvx(%[[varg1]], %[[pos]]) fastmath<contract> : (vector<4xi32>, !fir.ref<!fir.array<?xi8>>) -> ()
 189
 190 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %arg0 : !llvm.ptr<vector<4xi32>>
 191 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %arg1 : !llvm.ptr<i32>
 192 ! CHECK-LLVMIR: %[[idx:.*]] = llvm.load %arg3 : !llvm.ptr<i32>
 193 ! CHECK-LLVMIR: %[[idx64:.*]] = llvm.sext %[[idx]] : i32 to i64
 194 ! CHECK-LLVMIR: %[[one:.*]] = llvm.mlir.constant(1 : i64) : i64
 195 ! CHECK-LLVMIR: %[[idx64m1:.*]] = llvm.sub %[[idx64]], %[[one]] : i64
 196 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %arg2[0, %[[idx64m1]]] : (!llvm.ptr<array<5 x vector<4xi32>>>, i64) -> !llvm.ptr<vector<4xi32>>
 197 ! CHECK-LLVMIR: %[[bc:.*]] = llvm.bitcast %[[addr]] : !llvm.ptr<vector<4xi32>> to !llvm.ptr<i8>
 198 ! CHECK-LLVMIR: %[[pos:.*]] = llvm.getelementptr %[[bc]][%[[arg2]]] : (!llvm.ptr<i8>, i32) -> !llvm.ptr<i8>
 199 ! CHECK-LLVMIR: llvm.call @llvm.ppc.altivec.stvx(%[[arg1]], %[[pos]]) {fastmathFlags = #llvm.fastmath<contract>} : (vector<4xi32>, !llvm.ptr<i8>) -> ()
 200
 201 ! CHECK:  %5 = load <4 x i32>, ptr %0, align 16
 202 ! CHECK:  %6 = load i32, ptr %1, align 4
 203 ! CHECK:  %7 = load i32, ptr %3, align 4
 204 ! CHECK:  %8 = sext i32 %7 to i64
 205 ! CHECK:  %9 = sub i64 %8, 1
 206 ! CHECK:  %10 = getelementptr [5 x <4 x i32>], ptr %2, i32 0, i64 %9
 207 ! CHECK:  %11 = getelementptr i8, ptr %10, i32 %6
 208 ! CHECK:  call void @llvm.ppc.altivec.stvx(<4 x i32> %5, ptr %11)
 209 end subroutine vec_st_vi4i4via4
 210
 211 !----------------------
 212 ! vec_ste
 213 !----------------------
 214
 215 ! CHECK-LABEL: vec_ste_vi1i2i1
 216 subroutine vec_ste_vi1i2i1(arg1, arg2, arg3)
 217   vector(integer(1)) :: arg1
 218   integer(2) :: arg2
 219   integer(1) :: arg3
 220   call vec_ste(arg1, arg2, arg3)
 221
 222 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:i8>>
 223 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<i16>
 224 ! CHECK-FIR: %[[arg3:.*]] = fir.convert %{{.*}} : (!fir.ref<i8>) -> !fir.ref<!fir.array<?xi8>>
 225 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[arg3]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i16) -> !fir.ref<!fir.array<?xi8>>
 226 ! CHECK-FIR: %[[cnvArg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<16:i8>) -> vector<16xi8>
 227 ! CHECK-FIR: fir.call @llvm.ppc.altivec.stvebx(%[[cnvArg1]], %[[addr]]) fastmath<contract> : (vector<16xi8>, !fir.ref<!fir.array<?xi8>>) -> ()
 228
 229 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>>
 230 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<i16>
 231 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[arg3:.*]][%[[arg2]]] : (!llvm.ptr<i8>, i16) -> !llvm.ptr<i8>
 232 ! CHECK-LLVMIR: llvm.call @llvm.ppc.altivec.stvebx(%[[arg1]], %[[addr]]) {fastmathFlags = #llvm.fastmath<contract>} : (vector<16xi8>, !llvm.ptr<i8>) -> ()
 233
 234 ! CHECK: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16
 235 ! CHECK: %[[arg2:.*]] = load i16, ptr %{{.*}}, align 2
 236 ! CHECK: %[[arg3:.*]] = getelementptr i8, ptr %{{.*}}, i16 %5
 237 ! CHECK: call void @llvm.ppc.altivec.stvebx(<16 x i8> %[[arg1]], ptr %[[arg3]])
 238 end subroutine vec_ste_vi1i2i1
 239
 240 ! CHECK-LABEL: vec_ste_vi2i2i2
 241 subroutine vec_ste_vi2i2i2(arg1, arg2, arg3)
 242   vector(integer(2)) :: arg1
 243   integer(2) :: arg2
 244   integer(2) :: arg3
 245   call vec_ste(arg1, arg2, arg3)
 246
 247 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:i16>>
 248 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<i16>
 249 ! CHECK-FIR: %[[arg3:.*]] = fir.convert %{{.*}} : (!fir.ref<i16>) -> !fir.ref<!fir.array<?xi8>>
 250 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[arg3]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i16) -> !fir.ref<!fir.array<?xi8>>
 251 ! CHECK-FIR: %[[cnvArg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<8:i16>) -> vector<8xi16>
 252 ! CHECK-FIR: fir.call @llvm.ppc.altivec.stvehx(%[[cnvArg1]], %[[addr]]) fastmath<contract> : (vector<8xi16>, !fir.ref<!fir.array<?xi8>>) -> ()
 253
 254 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>>
 255 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<i16>
 256 ! CHECK-LLVMIR: %[[arg3:.*]] = llvm.bitcast %arg2 : !llvm.ptr<i16> to !llvm.ptr<i8>
 257 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[arg3]][%[[arg2]]] : (!llvm.ptr<i8>, i16) -> !llvm.ptr<i8>
 258 ! CHECK-LLVMIR: llvm.call @llvm.ppc.altivec.stvehx(%[[arg1]], %[[addr]]) {fastmathFlags = #llvm.fastmath<contract>} : (vector<8xi16>, !llvm.ptr<i8>) -> ()
 259
 260 ! CHECK: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16
 261 ! CHECK: %[[arg2:.*]] = load i16, ptr %{{.*}}, align 2
 262 ! CHECK: %[[arg3:.*]] = getelementptr i8, ptr %{{.*}}, i16 %5
 263 ! CHECK: call void @llvm.ppc.altivec.stvehx(<8 x i16> %[[arg1]], ptr %[[arg3]])
 264 end subroutine vec_ste_vi2i2i2
 265
 266 ! CHECK-LABEL: vec_ste_vi4i2i4
 267 subroutine vec_ste_vi4i2i4(arg1, arg2, arg3)
 268   vector(integer(4)) :: arg1
 269   integer(2) :: arg2
 270   integer(4) :: arg3
 271   call vec_ste(arg1, arg2, arg3)
 272
 273 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:i32>>
 274 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<i16>
 275 ! CHECK-FIR: %[[arg3:.*]] = fir.convert %{{.*}} : (!fir.ref<i32>) -> !fir.ref<!fir.array<?xi8>>
 276 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[arg3]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i16) -> !fir.ref<!fir.array<?xi8>>
 277 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<4:i32>) -> vector<4xi32>
 278 ! CHECK-FIR: fir.call @llvm.ppc.altivec.stvewx(%[[varg1]], %[[addr]]) fastmath<contract> : (vector<4xi32>, !fir.ref<!fir.array<?xi8>>) -> ()
 279
 280 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>>
 281 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<i16>
 282 ! CHECK-LLVMIR: %[[arg3:.*]] = llvm.bitcast %{{.*}} : !llvm.ptr<i32> to !llvm.ptr<i8>
 283 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[arg3]][%[[arg2]]] : (!llvm.ptr<i8>, i16) -> !llvm.ptr<i8>
 284 ! CHECK-LLVMIR: llvm.call @llvm.ppc.altivec.stvewx(%[[arg1]], %[[addr]]) {fastmathFlags = #llvm.fastmath<contract>} : (vector<4xi32>, !llvm.ptr<i8>) -> ()
 285
 286 ! CHECK: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16
 287 ! CHECK: %[[arg2:.*]] = load i16, ptr %{{.*}}, align 2
 288 ! CHECK: %[[arg3:.*]] = getelementptr i8, ptr %{{.*}}, i16 %5
 289 ! CHECK: call void @llvm.ppc.altivec.stvewx(<4 x i32> %[[arg1]], ptr %[[arg3]])
 290 end subroutine vec_ste_vi4i2i4
 291
 292 ! CHECK-LABEL: vec_ste_vu1i4u1
 293 subroutine vec_ste_vu1i4u1(arg1, arg2, arg3)
 294   vector(unsigned(1)) :: arg1
 295   integer(4) :: arg2
 296   integer(1) :: arg3
 297   call vec_ste(arg1, arg2, arg3)
 298
 299 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:ui8>>
 300 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<i32>
 301 ! CHECK-FIR: %[[arg3:.*]] = fir.convert %{{.*}} : (!fir.ref<i8>) -> !fir.ref<!fir.array<?xi8>>
 302 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[arg3]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i32) -> !fir.ref<!fir.array<?xi8>>
 303 ! CHECK-FIR: %[[cnvArg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<16:ui8>) -> vector<16xi8>
 304 ! CHECK-FIR: fir.call @llvm.ppc.altivec.stvebx(%[[cnvArg1]], %[[addr]]) fastmath<contract> : (vector<16xi8>, !fir.ref<!fir.array<?xi8>>) -> ()
 305
 306 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>>
 307 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<i32>
 308 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[arg3:.*]][%[[arg2]]] : (!llvm.ptr<i8>, i32) -> !llvm.ptr<i8>
 309 ! CHECK-LLVMIR: llvm.call @llvm.ppc.altivec.stvebx(%[[arg1]], %[[addr]]) {fastmathFlags = #llvm.fastmath<contract>} : (vector<16xi8>, !llvm.ptr<i8>) -> ()
 310
 311 ! CHECK: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16
 312 ! CHECK: %[[arg2:.*]] = load i32, ptr %{{.*}}, align 4
 313 ! CHECK: %[[arg3:.*]] = getelementptr i8, ptr %{{.*}}, i32 %5
 314 ! CHECK: call void @llvm.ppc.altivec.stvebx(<16 x i8> %[[arg1]], ptr %[[arg3]])
 315 end subroutine vec_ste_vu1i4u1
 316
 317 ! CHECK-LABEL: vec_ste_vu2i4u2
 318 subroutine vec_ste_vu2i4u2(arg1, arg2, arg3)
 319   vector(unsigned(2)) :: arg1
 320   integer(4) :: arg2
 321   integer(2) :: arg3
 322   call vec_ste(arg1, arg2, arg3)
 323
 324 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:ui16>>
 325 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<i32>
 326 ! CHECK-FIR: %[[arg3:.*]] = fir.convert %{{.*}} : (!fir.ref<i16>) -> !fir.ref<!fir.array<?xi8>>
 327 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[arg3]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i32) -> !fir.ref<!fir.array<?xi8>>
 328 ! CHECK-FIR: %[[cnvArg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<8:ui16>) -> vector<8xi16>
 329 ! CHECK-FIR: fir.call @llvm.ppc.altivec.stvehx(%[[cnvArg1]], %[[addr]]) fastmath<contract> : (vector<8xi16>, !fir.ref<!fir.array<?xi8>>) -> ()
 330
 331 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>>
 332 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<i32>
 333 ! CHECK-LLVMIR: %[[arg3:.*]] = llvm.bitcast %{{.*}} : !llvm.ptr<i16> to !llvm.ptr<i8>
 334 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[arg3]][%[[arg2]]] : (!llvm.ptr<i8>, i32) -> !llvm.ptr<i8>
 335 ! CHECK-LLVMIR: llvm.call @llvm.ppc.altivec.stvehx(%[[arg1]], %[[addr]]) {fastmathFlags = #llvm.fastmath<contract>} : (vector<8xi16>, !llvm.ptr<i8>) -> ()
 336
 337 ! CHECK: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16
 338 ! CHECK: %[[arg2:.*]] = load i32, ptr %{{.*}}, align 4
 339 ! CHECK: %[[arg3:.*]] = getelementptr i8, ptr %{{.*}}, i32 %5
 340 ! CHECK: call void @llvm.ppc.altivec.stvehx(<8 x i16> %[[arg1]], ptr %[[arg3]])
 341 end subroutine vec_ste_vu2i4u2
 342
 343 ! CHECK-LABEL: vec_ste_vu4i4u4
 344 subroutine vec_ste_vu4i4u4(arg1, arg2, arg3)
 345   vector(unsigned(4)) :: arg1
 346   integer(4) :: arg2
 347   integer(4) :: arg3
 348   call vec_ste(arg1, arg2, arg3)
 349
 350 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:ui32>>
 351 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<i32>
 352 ! CHECK-FIR: %[[arg3:.*]] = fir.convert %{{.*}} : (!fir.ref<i32>) -> !fir.ref<!fir.array<?xi8>>
 353 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[arg3]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i32) -> !fir.ref<!fir.array<?xi8>>
 354 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<4:ui32>) -> vector<4xi32>
 355 ! CHECK-FIR: fir.call @llvm.ppc.altivec.stvewx(%[[varg1]], %[[addr]]) fastmath<contract> : (vector<4xi32>, !fir.ref<!fir.array<?xi8>>) -> ()
 356
 357 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>>
 358 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<i32>
 359 ! CHECK-LLVMIR: %[[arg3:.*]] = llvm.bitcast %{{.*}} : !llvm.ptr<i32> to !llvm.ptr<i8>
 360 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[arg3]][%[[arg2]]] : (!llvm.ptr<i8>, i32) -> !llvm.ptr<i8>
 361 ! CHECK-LLVMIR: llvm.call @llvm.ppc.altivec.stvewx(%[[arg1]], %[[addr]]) {fastmathFlags = #llvm.fastmath<contract>} : (vector<4xi32>, !llvm.ptr<i8>) -> ()
 362
 363 ! CHECK: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16
 364 ! CHECK: %[[arg2:.*]] = load i32, ptr %{{.*}}, align 4
 365 ! CHECK: %[[arg3:.*]] = getelementptr i8, ptr %{{.*}}, i32 %5
 366 ! CHECK: call void @llvm.ppc.altivec.stvewx(<4 x i32> %[[arg1]], ptr %[[arg3]])
 367 end subroutine vec_ste_vu4i4u4
 368
 369 ! CHECK-LABEL: vec_ste_vr4i4r4
 370 subroutine vec_ste_vr4i4r4(arg1, arg2, arg3)
 371   vector(real(4)) :: arg1
 372   integer(4) :: arg2
 373   real(4) :: arg3
 374   call vec_ste(arg1, arg2, arg3)
 375
 376 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:f32>>
 377 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<i32>
 378 ! CHECK-FIR: %[[arg3:.*]] = fir.convert %arg2 : (!fir.ref<f32>) -> !fir.ref<!fir.array<?xi8>>
 379 ! CHECK-FIR: %[[pos:.*]] = fir.coordinate_of %[[arg3]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i32) -> !fir.ref<!fir.array<?xi8>>
 380 ! CHECK-FIR: %[[cnvArg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<4:f32>) -> vector<4xf32>
 381 ! CHECK-FIR: %[[bc:.*]] = vector.bitcast %[[cnvArg1]] : vector<4xf32> to vector<4xi32>
 382 ! CHECK-FIR: fir.call @llvm.ppc.altivec.stvewx(%[[bc]], %[[pos]]) fastmath<contract> : (vector<4xi32>, !fir.ref<!fir.array<?xi8>>) -> ()
 383
 384 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xf32>>
 385 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<i32>
 386 ! CHECK-LLVMIR: %[[arg3:.*]] = llvm.bitcast %arg2 : !llvm.ptr<f32> to !llvm.ptr<i8>
 387 ! CHECK-LLVMIR: %[[pos:.*]] = llvm.getelementptr %[[arg3]][%[[arg2]]] : (!llvm.ptr<i8>, i32) -> !llvm.ptr<i8>
 388 ! CHECK-LLVMIR: %[[bc:.*]] = llvm.bitcast %[[arg1]] : vector<4xf32> to vector<4xi32>
 389 ! CHECK-LLVMIR: llvm.call @llvm.ppc.altivec.stvewx(%[[bc]], %[[pos]]) {fastmathFlags = #llvm.fastmath<contract>} : (vector<4xi32>, !llvm.ptr<i8>) -> ()
 390
 391 ! CHECK: %[[arg1:.*]] = load <4 x float>, ptr %0, align 16
 392 ! CHECK: %[[arg2:.*]] = load i32, ptr %1, align 4
 393 ! CHECK: %[[pos:.*]] = getelementptr i8, ptr %2, i32 %[[arg2]]
 394 ! CHECK: %[[bc:.*]] = bitcast <4 x float> %[[arg1]] to <4 x i32>
 395 ! CHECK: call void @llvm.ppc.altivec.stvewx(<4 x i32> %[[bc]], ptr %[[pos]])
 396
 397 end subroutine vec_ste_vr4i4r4
 398
 399 ! CHECK-LABEL: vec_ste_vi4i4ia4
 400 subroutine vec_ste_vi4i4ia4(arg1, arg2, arg3, i)
 401   vector(integer(4)) :: arg1
 402   integer(4) :: arg2, i
 403   integer(4) :: arg3(5)
 404   call vec_ste(arg1, arg2, arg3(i))
 405
 406 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:i32>>
 407 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<i32>
 408 ! CHECK-FIR: %[[idx:.*]] = fir.load %{{.*}} : !fir.ref<i32>
 409 ! CHECK-FIR: %[[idx64:.*]] = fir.convert %[[idx]] : (i32) -> i64
 410 ! CHECK-FIR: %[[cnst:.*]] = arith.constant 1 : i64
 411 ! CHECK-FIR: %[[cnstm1:.*]] = arith.subi %[[idx64]], %[[cnst]] : i64
 412 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %arg2, %[[cnstm1]] : (!fir.ref<!fir.array<5xi32>>, i64) -> !fir.ref<i32>
 413 ! CHECK-FIR: %[[ref:.*]] = fir.convert %[[addr]] : (!fir.ref<i32>) -> !fir.ref<!fir.array<?xi8>>
 414 ! CHECK-FIR: %[[pos:.*]] = fir.coordinate_of %[[ref]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i32) -> !fir.ref<!fir.array<?xi8>>
 415 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<4:i32>) -> vector<4xi32>
 416 ! CHECK-FIR: fir.call @llvm.ppc.altivec.stvewx(%[[varg1]], %[[pos]]) fastmath<contract> : (vector<4xi32>, !fir.ref<!fir.array<?xi8>>) -> ()
 417
 418 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %arg0 : !llvm.ptr<vector<4xi32>>
 419 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %arg1 : !llvm.ptr<i32>
 420 ! CHECK-LLVMIR: %[[idx:.*]] = llvm.load %arg3 : !llvm.ptr<i32>
 421 ! CHECK-LLVMIR: %[[idx64:.*]] = llvm.sext %[[idx]] : i32 to i64
 422 ! CHECK-LLVMIR: %[[one:.*]] = llvm.mlir.constant(1 : i64) : i64
 423 ! CHECK-LLVMIR: %[[idx64m1:.*]] = llvm.sub %[[idx64]], %[[one]]  : i64
 424 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %arg2[0, %[[idx64m1]]] : (!llvm.ptr<array<5 x i32>>, i64) -> !llvm.ptr<i32>
 425 ! CHECK-LLVMIR: %[[bc:.*]] = llvm.bitcast %[[addr]] : !llvm.ptr<i32> to !llvm.ptr<i8>
 426 ! CHECK-LLVMIR: %[[pos:.*]] = llvm.getelementptr %[[bc]][%[[arg2]]] : (!llvm.ptr<i8>, i32) -> !llvm.ptr<i8>
 427 ! CHECK-LLVMIR: llvm.call @llvm.ppc.altivec.stvewx(%[[arg1]], %[[pos]]) {fastmathFlags = #llvm.fastmath<contract>} : (vector<4xi32>, !llvm.ptr<i8>) -> ()
 428
 429 ! CHECK:  %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
 430 ! CHECK:  %[[arg2:.*]] = load i32, ptr %1, align 4
 431 ! CHECK:  %[[idx:.*]] = load i32, ptr %3, align 4
 432 ! CHECK:  %[[idx64:.*]] = sext i32 %[[idx]] to i64
 433 ! CHECK:  %[[idx64m1:.*]] = sub i64 %[[idx64]], 1
 434 ! CHECK:  %[[addr:.*]] = getelementptr [5 x i32], ptr %[[arg3:.*]], i32 0, i64 %[[idx64m1]]
 435 ! CHECK:  %[[pos:.*]] = getelementptr i8, ptr %[[addr]], i32 %[[arg2]]
 436 ! CHECK:  call void @llvm.ppc.altivec.stvewx(<4 x i32> %[[arg1]], ptr %[[pos]])
 437 end subroutine vec_ste_vi4i4ia4
 438
 439 !----------------------
 440 ! vec_stxv
 441 !----------------------
 442
 443 ! CHECK-LABEL: vec_stxv_test_vr4i2r4
 444 subroutine vec_stxv_test_vr4i2r4(arg1, arg2, arg3)
 445   vector(real(4)) :: arg1
 446   integer(2) :: arg2
 447   real(4) :: arg3
 448   call vec_stxv(arg1, arg2, arg3)
 449
 450 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:f32>>
 451 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<i16>
 452 ! CHECK-FIR: %[[arg3ptr:.*]] = fir.convert %arg2 : (!fir.ref<f32>) -> !fir.ref<!fir.array<?xi8>>
 453 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[arg3ptr]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i16) -> !fir.ref<!fir.array<?xi8>>
 454 ! CHECK-FIR: %[[trg:.*]] = fir.convert %[[addr]] : (!fir.ref<!fir.array<?xi8>>) -> !fir.ref<!fir.vector<4:f32>>
 455 ! CHECK-FIR: fir.store %[[arg1]] to %[[trg]] {alignment = 1 : i64} : !fir.ref<!fir.vector<4:f32>>
 456
 457 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xf32>>
 458 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<i16>
 459 ! CHECK-LLVMIR: %[[arg3ptr:.*]] = llvm.bitcast %{{.*}} : !llvm.ptr<f32> to !llvm.ptr<i8>
 460 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[arg3ptr]][%[[arg2]]] : (!llvm.ptr<i8>, i16) -> !llvm.ptr<i8>
 461 ! CHECK-LLVMIR: %[[trg:.*]] = llvm.bitcast %[[addr]] : !llvm.ptr<i8> to !llvm.ptr<vector<4xf32>>
 462 ! CHECK-LLVMIR: llvm.store %[[arg1]], %[[trg]]
 463
 464 ! CHECK: %[[arg1:.*]] = load <4 x float>, ptr %{{.*}}, align 16
 465 ! CHECK: %[[arg2:.*]] = load i16, ptr %{{.*}}, align 2
 466 ! CHECK: %[[addr:.*]] = getelementptr i8, ptr %{{.*}}, i16 %[[arg2]]
 467 ! CHECK: store <4 x float> %[[arg1]], ptr %[[addr]], align 1
 468 end subroutine vec_stxv_test_vr4i2r4
 469
 470 ! CHECK-LABEL: vec_stxv_test_vi4i8ia4
 471 subroutine vec_stxv_test_vi4i8ia4(arg1, arg2, arg3, i)
 472   vector(integer(4)) :: arg1
 473   integer(8) :: arg2
 474   integer(4) :: arg3(10)
 475   integer(4) :: i
 476   call vec_stxv(arg1, arg2, arg3(i))
 477
 478 ! CHECK-FIR: %[[arg1:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<4:i32>>
 479 ! CHECK-FIR: %[[arg2:.*]] = fir.load %arg1 : !fir.ref<i64>
 480 ! CHECK-FIR: %[[idx:.*]] = fir.load %arg3 : !fir.ref<i32>
 481 ! CHECK-FIR: %[[idx64:.*]] = fir.convert %[[idx]] : (i32) -> i64
 482 ! CHECK-FIR: %[[one:.*]] = arith.constant 1 : i64
 483 ! CHECK-FIR: %[[idx64m1:.*]] = arith.subi %[[idx64]], %[[one]] : i64
 484 ! CHECK-FIR: %[[elem:.*]] = fir.coordinate_of %arg2, %[[idx64m1]] : (!fir.ref<!fir.array<10xi32>>, i64) -> !fir.ref<i32>
 485 ! CHECK-FIR: %[[elemref:.*]] = fir.convert %[[elem]] : (!fir.ref<i32>) -> !fir.ref<!fir.array<?xi8>>
 486 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[elemref]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i64) -> !fir.ref<!fir.array<?xi8>>
 487 ! CHECK-FIR: %[[trg:.*]] = fir.convert %[[addr]] : (!fir.ref<!fir.array<?xi8>>) -> !fir.ref<!fir.vector<4:i32>>
 488 ! CHECK-FIR: fir.store %[[arg1]] to %[[trg]] {alignment = 1 : i64} : !fir.ref<!fir.vector<4:i32>>
 489
 490 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %arg0 : !llvm.ptr<vector<4xi32>>
 491 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %arg1 : !llvm.ptr<i64>
 492 ! CHECK-LLVMIR: %[[idx:.*]] = llvm.load %arg3 : !llvm.ptr<i32>
 493 ! CHECK-LLVMIR: %[[idx64:.*]] = llvm.sext %[[idx]] : i32 to i64
 494 ! CHECK-LLVMIR: %[[one:.*]] = llvm.mlir.constant(1 : i64) : i64
 495 ! CHECK-LLVMIR: %[[idx64m1:.*]] = llvm.sub %[[idx64]], %[[one]]  : i64
 496 ! CHECK-LLVMIR: %[[elem:.*]] = llvm.getelementptr %arg2[0, %[[idx64m1]]] : (!llvm.ptr<array<10 x i32>>, i64) -> !llvm.ptr<i32>
 497 ! CHECK-LLVMIR: %[[elemref:.*]] = llvm.bitcast %[[elem]] : !llvm.ptr<i32> to !llvm.ptr<i8>
 498 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[elemref]][%[[arg2]]] : (!llvm.ptr<i8>, i64) -> !llvm.ptr<i8>
 499 ! CHECK-LLVMIR: %[[trg:.*]] = llvm.bitcast %[[addr]] : !llvm.ptr<i8> to !llvm.ptr<vector<4xi32>>
 500 ! CHECK-LLVMIR: llvm.store %[[arg1]], %[[trg]]
 501
 502 ! CHECK: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
 503 ! CHECK: %[[arg2:.*]] = load i64, ptr %1, align 8
 504 ! CHECK: %[[idx:.*]] = load i32, ptr %3, align 4
 505 ! CHECK: %[[idx64:.*]] = sext i32 %[[idx]] to i64
 506 ! CHECK: %[[idx64m1:.*]] = sub i64 %[[idx64]], 1
 507 ! CHECK: %[[elem:.*]] = getelementptr [10 x i32], ptr %2, i32 0, i64 %[[idx64m1]]
 508 ! CHECK: %[[trg:.*]] = getelementptr i8, ptr %[[elem]], i64 %6
 509 ! CHECK: store <4 x i32> %[[arg1]], ptr %[[trg]], align 1
 510 end subroutine vec_stxv_test_vi4i8ia4
 511
 512 ! CHECK-LABEL: vec_stxv_test_vi2i4vi2
 513 subroutine vec_stxv_test_vi2i4vi2(arg1, arg2, arg3)
 514   vector(integer(2)) :: arg1
 515   integer(4) :: arg2
 516   vector(integer(2)) :: arg3
 517   call vec_stxv(arg1, arg2, arg3)
 518
 519 ! CHECK-FIR: %[[arg1:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<8:i16>>
 520 ! CHECK-FIR: %[[arg2:.*]] = fir.load %arg1 : !fir.ref<i32>
 521 ! CHECK-FIR: %[[arg3:.*]] = fir.convert %arg2 : (!fir.ref<!fir.vector<8:i16>>) -> !fir.ref<!fir.array<?xi8>>
 522 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[arg3]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i32) -> !fir.ref<!fir.array<?xi8>>
 523 ! CHECK-FIR: %[[trg:.*]] = fir.convert %[[addr]] : (!fir.ref<!fir.array<?xi8>>) -> !fir.ref<!fir.vector<8:i16>>
 524 ! CHECK-FIR: fir.store %[[arg1]] to %[[trg]] {alignment = 1 : i64} : !fir.ref<!fir.vector<8:i16>>
 525
 526 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %arg0 : !llvm.ptr<vector<8xi16>>
 527 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %arg1 : !llvm.ptr<i32>
 528 ! CHECK-LLVMIR: %[[arg3:.*]] = llvm.bitcast %arg2 : !llvm.ptr<vector<8xi16>> to !llvm.ptr<i8>
 529 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[arg3]][%[[arg2]]] : (!llvm.ptr<i8>, i32) -> !llvm.ptr<i8>
 530 ! CHECK-LLVMIR: %[[trg:.*]] = llvm.bitcast %[[addr]] : !llvm.ptr<i8> to !llvm.ptr<vector<8xi16>>
 531 ! CHECK-LLVMIR: llvm.store %[[arg1]], %[[trg]]
 532
 533 ! CHECK: %[[arg1:.*]] = load <8 x i16>, ptr %0, align 16
 534 ! CHECK: %[[arg2:.*]] = load i32, ptr %1, align 4
 535 ! CHECK: %[[addr:.*]] = getelementptr i8, ptr %2, i32 %[[arg2]]
 536 ! CHECK:  store <8 x i16> %[[arg1]], ptr %[[addr]], align 1
 537 end subroutine vec_stxv_test_vi2i4vi2
 538
 539 ! CHECK-LABEL: vec_stxv_test_vi4i4vai4
 540 subroutine vec_stxv_test_vi4i4vai4(arg1, arg2, arg3, i)
 541   vector(integer(4)) :: arg1
 542   integer(4) :: arg2
 543   vector(integer(4)) :: arg3(20)
 544   integer(4) :: i
 545   call vec_stxv(arg1, arg2, arg3(i))
 546
 547 ! CHECK-FIR: %[[arg1:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<4:i32>>
 548 ! CHECK-FIR: %[[arg2:.*]] = fir.load %arg1 : !fir.ref<i32>
 549 ! CHECK-FIR: %[[idx:.*]] = fir.load %arg3 : !fir.ref<i32>
 550 ! CHECK-FIR: %[[idx64:.*]] = fir.convert %[[idx]] : (i32) -> i64
 551 ! CHECK-FIR: %[[one:.*]] = arith.constant 1 : i64
 552 ! CHECK-FIR: %[[idx64m1:.*]] = arith.subi %[[idx64]], %[[one]] : i64
 553 ! CHECK-FIR: %[[elem:.*]] = fir.coordinate_of %[[arg3:.*]], %[[idx64m1]] : (!fir.ref<!fir.array<20x!fir.vector<4:i32>>>, i64) -> !fir.ref<!fir.vector<4:i32>>
 554 ! CHECK-FIR: %[[elemptr:.*]] = fir.convert %[[elem]] : (!fir.ref<!fir.vector<4:i32>>) -> !fir.ref<!fir.array<?xi8>>
 555 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[elemptr]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i32) -> !fir.ref<!fir.array<?xi8>>
 556 ! CHECK-FIR: %[[trg:.*]] = fir.convert %[[addr]] : (!fir.ref<!fir.array<?xi8>>) -> !fir.ref<!fir.vector<4:i32>>
 557 ! CHECK-FIR: fir.store %[[arg1]] to %[[trg]] {alignment = 1 : i64} : !fir.ref<!fir.vector<4:i32>>
 558
 559 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %arg0 : !llvm.ptr<vector<4xi32>>
 560 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %arg1 : !llvm.ptr<i32>
 561 ! CHECK-LLVMIR: %[[idx:.*]] = llvm.load %arg3 : !llvm.ptr<i32>
 562 ! CHECK-LLVMIR: %[[idx64:.*]] = llvm.sext %[[idx]] : i32 to i64
 563 ! CHECK-LLVMIR: %[[one:.*]] = llvm.mlir.constant(1 : i64) : i64
 564 ! CHECK-LLVMIR: %[[idx64m1:.*]] = llvm.sub %[[idx64]], %[[one]]  : i64
 565 ! CHECK-LLVMIR: %[[elem:.*]] = llvm.getelementptr %[[arg3:.*]][0, %[[idx64m1]]] : (!llvm.ptr<array<20 x vector<4xi32>>>, i64) -> !llvm.ptr<vector<4xi32>>
 566 ! CHECK-LLVMIR: %[[elemptr:.*]] = llvm.bitcast %[[elem]] : !llvm.ptr<vector<4xi32>> to !llvm.ptr<i8>
 567 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[elemptr]][%[[arg2]]] : (!llvm.ptr<i8>, i32) -> !llvm.ptr<i8>
 568 ! CHECK-LLVMIR: %[[trg:.*]] = llvm.bitcast %[[addr]] : !llvm.ptr<i8> to !llvm.ptr<vector<4xi32>>
 569 ! CHECK-LLVMIR: llvm.store %[[arg1]], %[[trg]]
 570
 571 ! CHECK: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
 572 ! CHECK: %[[arg2:.*]] = load i32, ptr %1, align 4
 573 ! CHECK: %[[idx:.*]] = load i32, ptr %3, align 4
 574 ! CHECK: %[[idx64:.*]] = sext i32 %[[idx]] to i64
 575 ! CHECK: %[[idx64m1:.*]] = sub i64 %[[idx64]], 1
 576 ! CHECK: %[[elem:.*]] = getelementptr [20 x <4 x i32>], ptr %2, i32 0, i64 %[[idx64m1]]
 577 ! CHECK: %[[trg:.*]] = getelementptr i8, ptr %[[elem]], i32 %[[arg2]]
 578 ! CHECK: store <4 x i32> %[[arg1]], ptr %[[trg]], align 1
 579 end subroutine vec_stxv_test_vi4i4vai4
 580
 581 !----------------------
 582 ! vec_xst
 583 !----------------------
 584
 585 ! CHECK-LABEL: vec_xst_test_vr4i2r4
 586 subroutine vec_xst_test_vr4i2r4(arg1, arg2, arg3)
 587   vector(real(4)) :: arg1
 588   integer(2) :: arg2
 589   real(4) :: arg3
 590   call vec_xst(arg1, arg2, arg3)
 591
 592 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:f32>>
 593 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<i16>
 594 ! CHECK-FIR: %[[arg3ptr:.*]] = fir.convert %arg2 : (!fir.ref<f32>) -> !fir.ref<!fir.array<?xi8>>
 595 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[arg3ptr]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i16) -> !fir.ref<!fir.array<?xi8>>
 596 ! CHECK-FIR: %[[trg:.*]] = fir.convert %[[addr]] : (!fir.ref<!fir.array<?xi8>>) -> !fir.ref<!fir.vector<4:f32>>
 597 ! CHECK-FIR: fir.store %[[arg1]] to %[[trg]] {alignment = 1 : i64} : !fir.ref<!fir.vector<4:f32>>
 598
 599 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xf32>>
 600 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<i16>
 601 ! CHECK-LLVMIR: %[[arg3ptr:.*]] = llvm.bitcast %{{.*}} : !llvm.ptr<f32> to !llvm.ptr<i8>
 602 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[arg3ptr]][%[[arg2]]] : (!llvm.ptr<i8>, i16) -> !llvm.ptr<i8>
 603 ! CHECK-LLVMIR: %[[trg:.*]] = llvm.bitcast %[[addr]] : !llvm.ptr<i8> to !llvm.ptr<vector<4xf32>>
 604 ! CHECK-LLVMIR: llvm.store %[[arg1]], %[[trg]]
 605
 606 ! CHECK: %[[arg1:.*]] = load <4 x float>, ptr %{{.*}}, align 16
 607 ! CHECK: %[[arg2:.*]] = load i16, ptr %{{.*}}, align 2
 608 ! CHECK: %[[addr:.*]] = getelementptr i8, ptr %{{.*}}, i16 %[[arg2]]
 609 ! CHECK: store <4 x float> %[[arg1]], ptr %[[addr]], align 1
 610 end subroutine vec_xst_test_vr4i2r4
 611
 612 ! CHECK-LABEL: vec_xst_test_vi4i8ia4
 613 subroutine vec_xst_test_vi4i8ia4(arg1, arg2, arg3, i)
 614   vector(integer(4)) :: arg1
 615   integer(8) :: arg2
 616   integer(4) :: arg3(10)
 617   integer(4) :: i
 618   call vec_xst(arg1, arg2, arg3(i))
 619
 620 ! CHECK-FIR: %[[arg1:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<4:i32>>
 621 ! CHECK-FIR: %[[arg2:.*]] = fir.load %arg1 : !fir.ref<i64>
 622 ! CHECK-FIR: %[[idx:.*]] = fir.load %arg3 : !fir.ref<i32>
 623 ! CHECK-FIR: %[[idx64:.*]] = fir.convert %[[idx]] : (i32) -> i64
 624 ! CHECK-FIR: %[[one:.*]] = arith.constant 1 : i64
 625 ! CHECK-FIR: %[[idx64m1:.*]] = arith.subi %[[idx64]], %[[one]] : i64
 626 ! CHECK-FIR: %[[elem:.*]] = fir.coordinate_of %arg2, %[[idx64m1]] : (!fir.ref<!fir.array<10xi32>>, i64) -> !fir.ref<i32>
 627 ! CHECK-FIR: %[[elemref:.*]] = fir.convert %[[elem]] : (!fir.ref<i32>) -> !fir.ref<!fir.array<?xi8>>
 628 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[elemref]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i64) -> !fir.ref<!fir.array<?xi8>>
 629 ! CHECK-FIR: %[[trg:.*]] = fir.convert %[[addr]] : (!fir.ref<!fir.array<?xi8>>) -> !fir.ref<!fir.vector<4:i32>>
 630 ! CHECK-FIR: fir.store %[[arg1]] to %[[trg]] {alignment = 1 : i64} : !fir.ref<!fir.vector<4:i32>>
 631
 632 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %arg0 : !llvm.ptr<vector<4xi32>>
 633 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %arg1 : !llvm.ptr<i64>
 634 ! CHECK-LLVMIR: %[[idx:.*]] = llvm.load %arg3 : !llvm.ptr<i32>
 635 ! CHECK-LLVMIR: %[[idx64:.*]] = llvm.sext %[[idx]] : i32 to i64
 636 ! CHECK-LLVMIR: %[[one:.*]] = llvm.mlir.constant(1 : i64) : i64
 637 ! CHECK-LLVMIR: %[[idx64m1:.*]] = llvm.sub %[[idx64]], %[[one]]  : i64
 638 ! CHECK-LLVMIR: %[[elem:.*]] = llvm.getelementptr %arg2[0, %[[idx64m1]]] : (!llvm.ptr<array<10 x i32>>, i64) -> !llvm.ptr<i32>
 639 ! CHECK-LLVMIR: %[[elemref:.*]] = llvm.bitcast %[[elem]] : !llvm.ptr<i32> to !llvm.ptr<i8>
 640 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[elemref]][%[[arg2]]] : (!llvm.ptr<i8>, i64) -> !llvm.ptr<i8>
 641 ! CHECK-LLVMIR: %[[trg:.*]] = llvm.bitcast %[[addr]] : !llvm.ptr<i8> to !llvm.ptr<vector<4xi32>>
 642 ! CHECK-LLVMIR: llvm.store %[[arg1]], %[[trg]]
 643
 644 ! CHECK: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
 645 ! CHECK: %[[arg2:.*]] = load i64, ptr %1, align 8
 646 ! CHECK: %[[idx:.*]] = load i32, ptr %3, align 4
 647 ! CHECK: %[[idx64:.*]] = sext i32 %[[idx]] to i64
 648 ! CHECK: %[[idx64m1:.*]] = sub i64 %[[idx64]], 1
 649 ! CHECK: %[[elem:.*]] = getelementptr [10 x i32], ptr %2, i32 0, i64 %[[idx64m1]]
 650 ! CHECK: %[[trg:.*]] = getelementptr i8, ptr %[[elem]], i64 %6
 651 ! CHECK: store <4 x i32> %[[arg1]], ptr %[[trg]], align 1
 652 end subroutine vec_xst_test_vi4i8ia4
 653
 654 ! CHECK-LABEL: vec_xst_test_vi2i4vi2
 655 subroutine vec_xst_test_vi2i4vi2(arg1, arg2, arg3)
 656   vector(integer(2)) :: arg1
 657   integer(4) :: arg2
 658   vector(integer(2)) :: arg3
 659   call vec_xst(arg1, arg2, arg3)
 660
 661 ! CHECK-FIR: %[[arg1:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<8:i16>>
 662 ! CHECK-FIR: %[[arg2:.*]] = fir.load %arg1 : !fir.ref<i32>
 663 ! CHECK-FIR: %[[arg3:.*]] = fir.convert %arg2 : (!fir.ref<!fir.vector<8:i16>>) -> !fir.ref<!fir.array<?xi8>>
 664 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[arg3]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i32) -> !fir.ref<!fir.array<?xi8>>
 665 ! CHECK-FIR: %[[trg:.*]] = fir.convert %[[addr]] : (!fir.ref<!fir.array<?xi8>>) -> !fir.ref<!fir.vector<8:i16>>
 666 ! CHECK-FIR: fir.store %[[arg1]] to %[[trg]] {alignment = 1 : i64} : !fir.ref<!fir.vector<8:i16>>
 667
 668 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %arg0 : !llvm.ptr<vector<8xi16>>
 669 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %arg1 : !llvm.ptr<i32>
 670 ! CHECK-LLVMIR: %[[arg3:.*]] = llvm.bitcast %arg2 : !llvm.ptr<vector<8xi16>> to !llvm.ptr<i8>
 671 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[arg3]][%[[arg2]]] : (!llvm.ptr<i8>, i32) -> !llvm.ptr<i8>
 672 ! CHECK-LLVMIR: %[[trg:.*]] = llvm.bitcast %[[addr]] : !llvm.ptr<i8> to !llvm.ptr<vector<8xi16>>
 673 ! CHECK-LLVMIR: llvm.store %[[arg1]], %[[trg]]
 674
 675 ! CHECK: %[[arg1:.*]] = load <8 x i16>, ptr %0, align 16
 676 ! CHECK: %[[arg2:.*]] = load i32, ptr %1, align 4
 677 ! CHECK: %[[addr:.*]] = getelementptr i8, ptr %2, i32 %[[arg2]]
 678 ! CHECK:  store <8 x i16> %[[arg1]], ptr %[[addr]], align 1
 679 end subroutine vec_xst_test_vi2i4vi2
 680
 681 ! CHECK-LABEL: vec_xst_test_vi4i4vai4
 682 subroutine vec_xst_test_vi4i4vai4(arg1, arg2, arg3, i)
 683   vector(integer(4)) :: arg1
 684   integer(4) :: arg2
 685   vector(integer(4)) :: arg3(20)
 686   integer(4) :: i
 687   call vec_xst(arg1, arg2, arg3(i))
 688
 689 ! CHECK-FIR: %[[arg1:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<4:i32>>
 690 ! CHECK-FIR: %[[arg2:.*]] = fir.load %arg1 : !fir.ref<i32>
 691 ! CHECK-FIR: %[[idx:.*]] = fir.load %arg3 : !fir.ref<i32>
 692 ! CHECK-FIR: %[[idx64:.*]] = fir.convert %[[idx]] : (i32) -> i64
 693 ! CHECK-FIR: %[[one:.*]] = arith.constant 1 : i64
 694 ! CHECK-FIR: %[[idx64m1:.*]] = arith.subi %[[idx64]], %[[one]] : i64
 695 ! CHECK-FIR: %[[elem:.*]] = fir.coordinate_of %[[arg3:.*]], %[[idx64m1]] : (!fir.ref<!fir.array<20x!fir.vector<4:i32>>>, i64) -> !fir.ref<!fir.vector<4:i32>>
 696 ! CHECK-FIR: %[[elemptr:.*]] = fir.convert %[[elem]] : (!fir.ref<!fir.vector<4:i32>>) -> !fir.ref<!fir.array<?xi8>>
 697 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[elemptr]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i32) -> !fir.ref<!fir.array<?xi8>>
 698 ! CHECK-FIR: %[[trg:.*]] = fir.convert %[[addr]] : (!fir.ref<!fir.array<?xi8>>) -> !fir.ref<!fir.vector<4:i32>>
 699 ! CHECK-FIR: fir.store %[[arg1]] to %[[trg]] {alignment = 1 : i64} : !fir.ref<!fir.vector<4:i32>>
 700
 701 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %arg0 : !llvm.ptr<vector<4xi32>>
 702 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %arg1 : !llvm.ptr<i32>
 703 ! CHECK-LLVMIR: %[[idx:.*]] = llvm.load %arg3 : !llvm.ptr<i32>
 704 ! CHECK-LLVMIR: %[[idx64:.*]] = llvm.sext %[[idx]] : i32 to i64
 705 ! CHECK-LLVMIR: %[[one:.*]] = llvm.mlir.constant(1 : i64) : i64
 706 ! CHECK-LLVMIR: %[[idx64m1:.*]] = llvm.sub %[[idx64]], %[[one]]  : i64
 707 ! CHECK-LLVMIR: %[[elem:.*]] = llvm.getelementptr %[[arg3:.*]][0, %[[idx64m1]]] : (!llvm.ptr<array<20 x vector<4xi32>>>, i64) -> !llvm.ptr<vector<4xi32>>
 708 ! CHECK-LLVMIR: %[[elemptr:.*]] = llvm.bitcast %[[elem]] : !llvm.ptr<vector<4xi32>> to !llvm.ptr<i8>
 709 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[elemptr]][%[[arg2]]] : (!llvm.ptr<i8>, i32) -> !llvm.ptr<i8>
 710 ! CHECK-LLVMIR: %[[trg:.*]] = llvm.bitcast %[[addr]] : !llvm.ptr<i8> to !llvm.ptr<vector<4xi32>>
 711 ! CHECK-LLVMIR: llvm.store %[[arg1]], %[[trg]]
 712
 713 ! CHECK: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
 714 ! CHECK: %[[arg2:.*]] = load i32, ptr %1, align 4
 715 ! CHECK: %[[idx:.*]] = load i32, ptr %3, align 4
 716 ! CHECK: %[[idx64:.*]] = sext i32 %[[idx]] to i64
 717 ! CHECK: %[[idx64m1:.*]] = sub i64 %[[idx64]], 1
 718 ! CHECK: %[[elem:.*]] = getelementptr [20 x <4 x i32>], ptr %2, i32 0, i64 %[[idx64m1]]
 719 ! CHECK: %[[trg:.*]] = getelementptr i8, ptr %[[elem]], i32 %[[arg2]]
 720 ! CHECK: store <4 x i32> %[[arg1]], ptr %[[trg]], align 1
 721 end subroutine vec_xst_test_vi4i4vai4
 722
 723 !----------------------
 724 ! vec_xst_be
 725 !----------------------
 726
 727 ! CHECK-LABEL: vec_xst_be_test_vr4i2r4
 728 subroutine vec_xst_be_test_vr4i2r4(arg1, arg2, arg3)
 729   vector(real(4)) :: arg1
 730   integer(2) :: arg2
 731   real(4) :: arg3
 732   call vec_xst_be(arg1, arg2, arg3)
 733
 734 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:f32>>
 735 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<i16>
 736 ! CHECK-FIR: %[[arg3ptr:.*]] = fir.convert %arg2 : (!fir.ref<f32>) -> !fir.ref<!fir.array<?xi8>>
 737 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[arg3ptr]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i16) -> !fir.ref<!fir.array<?xi8>>
 738 ! CHECK-FIR: %[[trg:.*]] = fir.convert %[[addr]] : (!fir.ref<!fir.array<?xi8>>) -> !fir.ref<!fir.vector<4:f32>>
 739 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<4:f32>) -> vector<4xf32>
 740 ! CHECK-FIR: %[[undef:.*]] = fir.undefined vector<4xf32>
 741 ! CHECK-FIR: %[[shf:.*]] = vector.shuffle %[[varg1]], %[[undef]] [3, 2, 1, 0] : vector<4xf32>, vector<4xf32>
 742 ! CHECK-FIR: %[[fvarg1:.*]] = fir.convert %[[shf]] : (vector<4xf32>) -> !fir.vector<4:f32>
 743 ! CHECK-FIR: fir.store %[[fvarg1]] to %[[trg]] {alignment = 1 : i64} : !fir.ref<!fir.vector<4:f32>>
 744
 745 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xf32>>
 746 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<i16>
 747 ! CHECK-LLVMIR: %[[arg3ptr:.*]] = llvm.bitcast %{{.*}} : !llvm.ptr<f32> to !llvm.ptr<i8>
 748 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[arg3ptr]][%[[arg2]]] : (!llvm.ptr<i8>, i16) -> !llvm.ptr<i8>
 749 ! CHECK-LLVMIR: %[[trg:.*]] = llvm.bitcast %[[addr]] : !llvm.ptr<i8> to !llvm.ptr<vector<4xf32>>
 750 ! CHECK-LLVMIR: %[[undef:.*]] = llvm.mlir.undef : vector<4xf32>
 751 ! CHECK-LLVMIR: %[[shf:.*]] = llvm.shufflevector %[[arg1]], %[[undef]] [3, 2, 1, 0] : vector<4xf32>
 752 ! CHECK-LLVMIR: llvm.store %[[shf]], %[[trg]]
 753
 754 ! CHECK: %[[arg1:.*]] = load <4 x float>, ptr %{{.*}}, align 16
 755 ! CHECK: %[[arg2:.*]] = load i16, ptr %{{.*}}, align 2
 756 ! CHECK: %[[addr:.*]] = getelementptr i8, ptr %{{.*}}, i16 %[[arg2]]
 757 ! CHECK: %[[shf:.*]] = shufflevector <4 x float> %[[arg1]], <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
 758 ! CHECK: store <4 x float> %[[shf]], ptr %[[addr]], align 1
 759 end subroutine vec_xst_be_test_vr4i2r4
 760
 761 ! CHECK-LABEL: vec_xst_be_test_vi4i8ia4
 762 subroutine vec_xst_be_test_vi4i8ia4(arg1, arg2, arg3, i)
 763   vector(integer(4)) :: arg1
 764   integer(8) :: arg2
 765   integer(4) :: arg3(10)
 766   integer(4) :: i
 767   call vec_xst_be(arg1, arg2, arg3(i))
 768
 769 ! CHECK-FIR: %[[arg1:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<4:i32>>
 770 ! CHECK-FIR: %[[arg2:.*]] = fir.load %arg1 : !fir.ref<i64>
 771 ! CHECK-FIR: %[[idx:.*]] = fir.load %arg3 : !fir.ref<i32>
 772 ! CHECK-FIR: %[[idx64:.*]] = fir.convert %[[idx]] : (i32) -> i64
 773 ! CHECK-FIR: %[[one:.*]] = arith.constant 1 : i64
 774 ! CHECK-FIR: %[[idx64m1:.*]] = arith.subi %[[idx64]], %[[one]] : i64
 775 ! CHECK-FIR: %[[elem:.*]] = fir.coordinate_of %arg2, %[[idx64m1]] : (!fir.ref<!fir.array<10xi32>>, i64) -> !fir.ref<i32>
 776 ! CHECK-FIR: %[[elemref:.*]] = fir.convert %[[elem]] : (!fir.ref<i32>) -> !fir.ref<!fir.array<?xi8>>
 777 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[elemref]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i64) -> !fir.ref<!fir.array<?xi8>>
 778 ! CHECK-FIR: %[[trg:.*]] = fir.convert %[[addr]] : (!fir.ref<!fir.array<?xi8>>) -> !fir.ref<!fir.vector<4:i32>>
 779 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<4:i32>) -> vector<4xi32>
 780 ! CHECK-FIR: %[[undef:.*]] = fir.undefined vector<4xi32>
 781 ! CHECK-FIR: %[[shf:.*]] = vector.shuffle %[[varg1]], %[[undef]] [3, 2, 1, 0] : vector<4xi32>, vector<4xi32>
 782 ! CHECK-FIR: %[[src:.*]] = fir.convert %[[shf]] : (vector<4xi32>) -> !fir.vector<4:i32>
 783 ! CHECK-FIR: fir.store %[[src]] to %[[trg]] {alignment = 1 : i64} : !fir.ref<!fir.vector<4:i32>>
 784
 785 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %arg0 : !llvm.ptr<vector<4xi32>>
 786 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %arg1 : !llvm.ptr<i64>
 787 ! CHECK-LLVMIR: %[[idx:.*]] = llvm.load %arg3 : !llvm.ptr<i32>
 788 ! CHECK-LLVMIR: %[[idx64:.*]] = llvm.sext %[[idx]] : i32 to i64
 789 ! CHECK-LLVMIR: %[[one:.*]] = llvm.mlir.constant(1 : i64) : i64
 790 ! CHECK-LLVMIR: %[[idx64m1:.*]] = llvm.sub %[[idx64]], %[[one]]  : i64
 791 ! CHECK-LLVMIR: %[[elem:.*]] = llvm.getelementptr %arg2[0, %[[idx64m1]]] : (!llvm.ptr<array<10 x i32>>, i64) -> !llvm.ptr<i32>
 792 ! CHECK-LLVMIR: %[[elemref:.*]] = llvm.bitcast %[[elem]] : !llvm.ptr<i32> to !llvm.ptr<i8>
 793 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[elemref]][%[[arg2]]] : (!llvm.ptr<i8>, i64) -> !llvm.ptr<i8>
 794 ! CHECK-LLVMIR: %[[trg:.*]] = llvm.bitcast %[[addr]] : !llvm.ptr<i8> to !llvm.ptr<vector<4xi32>>
 795 ! CHECK-LLVMIR: %[[undef:.*]] = llvm.mlir.undef : vector<4xi32>
 796 ! CHECK-LLVMIR: %[[src:.*]] = llvm.shufflevector %[[arg1]], %[[undef]] [3, 2, 1, 0] : vector<4xi32>
 797 ! CHECK-LLVMIR: llvm.store %[[src]], %[[trg]]
 798
 799 ! CHECK: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
 800 ! CHECK: %[[arg2:.*]] = load i64, ptr %1, align 8
 801 ! CHECK: %[[idx:.*]] = load i32, ptr %3, align 4
 802 ! CHECK: %[[idx64:.*]] = sext i32 %[[idx]] to i64
 803 ! CHECK: %[[idx64m1:.*]] = sub i64 %[[idx64]], 1
 804 ! CHECK: %[[elem:.*]] = getelementptr [10 x i32], ptr %2, i32 0, i64 %[[idx64m1]]
 805 ! CHECK: %[[trg:.*]] = getelementptr i8, ptr %[[elem]], i64 %6
 806 ! CHECK: %[[src:.*]] = shufflevector <4 x i32> %[[arg1]], <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
 807 ! CHECK: store <4 x i32> %[[src]], ptr %[[trg]], align 1
 808 end subroutine vec_xst_be_test_vi4i8ia4
 809
 810 ! CHECK-LABEL: vec_xst_be_test_vi2i4vi2
 811 subroutine vec_xst_be_test_vi2i4vi2(arg1, arg2, arg3)
 812   vector(integer(2)) :: arg1
 813   integer(4) :: arg2
 814   vector(integer(2)) :: arg3
 815   call vec_xst_be(arg1, arg2, arg3)
 816
 817 ! CHECK-FIR: %[[arg1:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<8:i16>>
 818 ! CHECK-FIR: %[[arg2:.*]] = fir.load %arg1 : !fir.ref<i32>
 819 ! CHECK-FIR: %[[arg3:.*]] = fir.convert %arg2 : (!fir.ref<!fir.vector<8:i16>>) -> !fir.ref<!fir.array<?xi8>>
 820 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[arg3]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i32) -> !fir.ref<!fir.array<?xi8>>
 821 ! CHECK-FIR: %[[trg:.*]] = fir.convert %[[addr]] : (!fir.ref<!fir.array<?xi8>>) -> !fir.ref<!fir.vector<8:i16>>
 822 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<8:i16>) -> vector<8xi16>
 823 ! CHECK-FIR: %[[undef:.*]] = fir.undefined vector<8xi16>
 824 ! CHECK-FIR: %[[shf:.*]] = vector.shuffle %[[varg1]], %[[undef]] [7, 6, 5, 4, 3, 2, 1, 0] : vector<8xi16>, vector<8xi16>
 825 ! CHECK-FIR: %[[src:.*]] = fir.convert %[[shf]] : (vector<8xi16>) -> !fir.vector<8:i16>
 826 ! CHECK-FIR: fir.store %[[src]] to %[[trg]] {alignment = 1 : i64} : !fir.ref<!fir.vector<8:i16>>
 827
 828 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %arg0 : !llvm.ptr<vector<8xi16>>
 829 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %arg1 : !llvm.ptr<i32>
 830 ! CHECK-LLVMIR: %[[arg3:.*]] = llvm.bitcast %arg2 : !llvm.ptr<vector<8xi16>> to !llvm.ptr<i8>
 831 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[arg3]][%[[arg2]]] : (!llvm.ptr<i8>, i32) -> !llvm.ptr<i8>
 832 ! CHECK-LLVMIR: %[[trg:.*]] = llvm.bitcast %[[addr]] : !llvm.ptr<i8> to !llvm.ptr<vector<8xi16>>
 833 ! CHECK-LLVMIR: %[[undef:.*]] = llvm.mlir.undef : vector<8xi16>
 834 ! CHECK-LLVMIR: %[[src:.*]] = llvm.shufflevector %[[arg1]], %[[undef]] [7, 6, 5, 4, 3, 2, 1, 0] : vector<8xi16>
 835 ! CHECK-LLVMIR: llvm.store %[[src]], %[[trg]]
 836
 837 ! CHECK: %[[arg1:.*]] = load <8 x i16>, ptr %0, align 16
 838 ! CHECK: %[[arg2:.*]] = load i32, ptr %1, align 4
 839 ! CHECK: %[[addr:.*]] = getelementptr i8, ptr %2, i32 %[[arg2]]
 840 ! CHECK: %[[src:.*]] = shufflevector <8 x i16> %[[arg1]], <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
 841 ! CHECK:  store <8 x i16> %[[src]], ptr %[[addr]], align 1
 842 end subroutine vec_xst_be_test_vi2i4vi2
 843
 844 ! CHECK-LABEL: vec_xst_be_test_vi4i4vai4
 845 subroutine vec_xst_be_test_vi4i4vai4(arg1, arg2, arg3, i)
 846   vector(integer(4)) :: arg1
 847   integer(4) :: arg2
 848   vector(integer(4)) :: arg3(20)
 849   integer(4) :: i
 850   call vec_xst_be(arg1, arg2, arg3(i))
 851
 852 ! CHECK-FIR: %[[arg1:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<4:i32>>
 853 ! CHECK-FIR: %[[arg2:.*]] = fir.load %arg1 : !fir.ref<i32>
 854 ! CHECK-FIR: %[[idx:.*]] = fir.load %arg3 : !fir.ref<i32>
 855 ! CHECK-FIR: %[[idx64:.*]] = fir.convert %[[idx]] : (i32) -> i64
 856 ! CHECK-FIR: %[[one:.*]] = arith.constant 1 : i64
 857 ! CHECK-FIR: %[[idx64m1:.*]] = arith.subi %[[idx64]], %[[one]] : i64
 858 ! CHECK-FIR: %[[elem:.*]] = fir.coordinate_of %[[arg3:.*]], %[[idx64m1]] : (!fir.ref<!fir.array<20x!fir.vector<4:i32>>>, i64) -> !fir.ref<!fir.vector<4:i32>>
 859 ! CHECK-FIR: %[[elemptr:.*]] = fir.convert %[[elem]] : (!fir.ref<!fir.vector<4:i32>>) -> !fir.ref<!fir.array<?xi8>>
 860 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[elemptr]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i32) -> !fir.ref<!fir.array<?xi8>>
 861 ! CHECK-FIR: %[[trg:.*]] = fir.convert %[[addr]] : (!fir.ref<!fir.array<?xi8>>) -> !fir.ref<!fir.vector<4:i32>>
 862 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<4:i32>) -> vector<4xi32>
 863 ! CHECK-FIR: %[[undef:.*]] = fir.undefined vector<4xi32>
 864 ! CHECK-FIR: %[[shf:.*]] = vector.shuffle %[[varg1]], %[[undef]] [3, 2, 1, 0] : vector<4xi32>, vector<4xi32>
 865 ! CHECK-FIR: %[[src:.*]] = fir.convert %[[shf]] : (vector<4xi32>) -> !fir.vector<4:i32>
 866 ! CHECK-FIR: fir.store %[[src]] to %[[trg]] {alignment = 1 : i64} : !fir.ref<!fir.vector<4:i32>>
 867
 868 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %arg0 : !llvm.ptr<vector<4xi32>>
 869 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %arg1 : !llvm.ptr<i32>
 870 ! CHECK-LLVMIR: %[[idx:.*]] = llvm.load %arg3 : !llvm.ptr<i32>
 871 ! CHECK-LLVMIR: %[[idx64:.*]] = llvm.sext %[[idx]] : i32 to i64
 872 ! CHECK-LLVMIR: %[[one:.*]] = llvm.mlir.constant(1 : i64) : i64
 873 ! CHECK-LLVMIR: %[[idx64m1:.*]] = llvm.sub %[[idx64]], %[[one]]  : i64
 874 ! CHECK-LLVMIR: %[[elem:.*]] = llvm.getelementptr %[[arg3:.*]][0, %[[idx64m1]]] : (!llvm.ptr<array<20 x vector<4xi32>>>, i64) -> !llvm.ptr<vector<4xi32>>
 875 ! CHECK-LLVMIR: %[[elemptr:.*]] = llvm.bitcast %[[elem]] : !llvm.ptr<vector<4xi32>> to !llvm.ptr<i8>
 876 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[elemptr]][%[[arg2]]] : (!llvm.ptr<i8>, i32) -> !llvm.ptr<i8>
 877 ! CHECK-LLVMIR: %[[trg:.*]] = llvm.bitcast %[[addr]] : !llvm.ptr<i8> to !llvm.ptr<vector<4xi32>>
 878 ! CHECK-LLVMIR: %[[undef:.*]] = llvm.mlir.undef : vector<4xi32>
 879 ! CHECK-LLVMIR: %[[src:.*]] = llvm.shufflevector %[[arg1]], %[[undef]] [3, 2, 1, 0] : vector<4xi32>
 880 ! CHECK-LLVMIR: llvm.store %[[src]], %[[trg]]
 881
 882 ! CHECK: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
 883 ! CHECK: %[[arg2:.*]] = load i32, ptr %1, align 4
 884 ! CHECK: %[[idx:.*]] = load i32, ptr %3, align 4
 885 ! CHECK: %[[idx64:.*]] = sext i32 %[[idx]] to i64
 886 ! CHECK: %[[idx64m1:.*]] = sub i64 %[[idx64]], 1
 887 ! CHECK: %[[elem:.*]] = getelementptr [20 x <4 x i32>], ptr %2, i32 0, i64 %[[idx64m1]]
 888 ! CHECK: %[[trg:.*]] = getelementptr i8, ptr %[[elem]], i32 %[[arg2]]
 889 ! CHECK: %[[src:.*]] = shufflevector <4 x i32> %[[arg1]], <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
 890 ! CHECK: store <4 x i32> %[[src]], ptr %[[trg]], align 1
 891 end subroutine vec_xst_be_test_vi4i4vai4
 892
 893 !----------------------
 894 ! vec_xstd2
 895 !----------------------
 896
 897 ! CHECK-LABEL: vec_xstd2_test_vr4i2r4
 898 subroutine vec_xstd2_test_vr4i2r4(arg1, arg2, arg3)
 899   vector(real(4)) :: arg1
 900   integer(2) :: arg2
 901   real(4) :: arg3
 902   call vec_xstd2(arg1, arg2, arg3)
 903
 904 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:f32>>
 905 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<i16>
 906 ! CHECK-FIR: %[[arg3ptr:.*]] = fir.convert %arg2 : (!fir.ref<f32>) -> !fir.ref<!fir.array<?xi8>>
 907 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[arg3ptr]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i16) -> !fir.ref<!fir.array<?xi8>>
 908 ! CHECK-FIR: %[[vsrc:.*]] = fir.convert %[[arg1]] : (!fir.vector<4:f32>) -> vector<4xf32>
 909 ! CHECK-FIR: %[[bcsrc:.*]] = vector.bitcast %[[vsrc]] : vector<4xf32> to vector<2xi64>
 910 ! CHECK-FIR: %[[trg:.*]] = fir.convert %[[addr]] : (!fir.ref<!fir.array<?xi8>>) -> !fir.ref<!fir.vector<2:i64>>
 911 ! CHECK-FIR: %[[cnvsrc:.*]] = fir.convert %[[bcsrc]] : (vector<2xi64>) -> !fir.vector<2:i64>
 912 ! CHECK-FIR: fir.store %[[cnvsrc]] to %[[trg]] {alignment = 1 : i64} : !fir.ref<!fir.vector<2:i64>>
 913
 914 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xf32>>
 915 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<i16>
 916 ! CHECK-LLVMIR: %[[arg3ptr:.*]] = llvm.bitcast %{{.*}} : !llvm.ptr<f32> to !llvm.ptr<i8>
 917 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[arg3ptr]][%[[arg2]]] : (!llvm.ptr<i8>, i16) -> !llvm.ptr<i8>
 918 ! CHECK-LLVMIR: %[[src:.*]] = llvm.bitcast %[[arg1]] : vector<4xf32> to vector<2xi64>
 919 ! CHECK-LLVMIR: %[[trg:.*]] = llvm.bitcast %[[addr]] : !llvm.ptr<i8> to !llvm.ptr<vector<2xi64>>
 920 ! CHECK-LLVMIR: llvm.store %[[src]], %[[trg]]
 921
 922 ! CHECK: %[[arg1:.*]] = load <4 x float>, ptr %{{.*}}, align 16
 923 ! CHECK: %[[arg2:.*]] = load i16, ptr %{{.*}}, align 2
 924 ! CHECK: %[[addr:.*]] = getelementptr i8, ptr %{{.*}}, i16 %[[arg2]]
 925 ! CHECK: %[[src:.*]] = bitcast <4 x float> %[[arg1]] to <2 x i64>
 926 ! CHECK: store <2 x i64> %[[src]], ptr %[[addr]], align 1
 927 end subroutine vec_xstd2_test_vr4i2r4
 928
 929 ! CHECK-LABEL: vec_xstd2_test_vi4i8ia4
 930 subroutine vec_xstd2_test_vi4i8ia4(arg1, arg2, arg3, i)
 931   vector(integer(4)) :: arg1
 932   integer(8) :: arg2
 933   integer(4) :: arg3(10)
 934   integer(4) :: i
 935   call vec_xstd2(arg1, arg2, arg3(i))
 936
 937 ! CHECK-FIR: %[[arg1:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<4:i32>>
 938 ! CHECK-FIR: %[[arg2:.*]] = fir.load %arg1 : !fir.ref<i64>
 939 ! CHECK-FIR: %[[idx:.*]] = fir.load %arg3 : !fir.ref<i32>
 940 ! CHECK-FIR: %[[idx64:.*]] = fir.convert %[[idx]] : (i32) -> i64
 941 ! CHECK-FIR: %[[one:.*]] = arith.constant 1 : i64
 942 ! CHECK-FIR: %[[idx64m1:.*]] = arith.subi %[[idx64]], %[[one]] : i64
 943 ! CHECK-FIR: %[[elem:.*]] = fir.coordinate_of %arg2, %[[idx64m1]] : (!fir.ref<!fir.array<10xi32>>, i64) -> !fir.ref<i32>
 944 ! CHECK-FIR: %[[elemref:.*]] = fir.convert %[[elem]] : (!fir.ref<i32>) -> !fir.ref<!fir.array<?xi8>>
 945 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[elemref]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i64) -> !fir.ref<!fir.array<?xi8>>
 946 ! CHECK-FIR: %[[vsrc:.*]] = fir.convert %[[arg1]] : (!fir.vector<4:i32>) -> vector<4xi32>
 947 ! CHECK-FIR: %[[bcsrc:.*]] = vector.bitcast %[[vsrc]] : vector<4xi32> to vector<2xi64>
 948 ! CHECK-FIR: %[[trg:.*]] = fir.convert %[[addr]] : (!fir.ref<!fir.array<?xi8>>) -> !fir.ref<!fir.vector<2:i64>>
 949 ! CHECK-FIR: %[[cnvsrc:.*]] = fir.convert %[[bcsrc]] : (vector<2xi64>) -> !fir.vector<2:i64>
 950 ! CHECK-FIR: fir.store %[[cnvsrc]] to %[[trg]] {alignment = 1 : i64} : !fir.ref<!fir.vector<2:i64>>
 951
 952 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %arg0 : !llvm.ptr<vector<4xi32>>
 953 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %arg1 : !llvm.ptr<i64>
 954 ! CHECK-LLVMIR: %[[idx:.*]] = llvm.load %arg3 : !llvm.ptr<i32>
 955 ! CHECK-LLVMIR: %[[idx64:.*]] = llvm.sext %[[idx]] : i32 to i64
 956 ! CHECK-LLVMIR: %[[one:.*]] = llvm.mlir.constant(1 : i64) : i64
 957 ! CHECK-LLVMIR: %[[idx64m1:.*]] = llvm.sub %[[idx64]], %[[one]]  : i64
 958 ! CHECK-LLVMIR: %[[elem:.*]] = llvm.getelementptr %arg2[0, %[[idx64m1]]] : (!llvm.ptr<array<10 x i32>>, i64) -> !llvm.ptr<i32>
 959 ! CHECK-LLVMIR: %[[elemref:.*]] = llvm.bitcast %[[elem]] : !llvm.ptr<i32> to !llvm.ptr<i8>
 960 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[elemref]][%[[arg2]]] : (!llvm.ptr<i8>, i64) -> !llvm.ptr<i8>
 961 ! CHECK-LLVMIR: %[[src:.*]] = llvm.bitcast %[[arg1]] : vector<4xi32> to vector<2xi64>
 962 ! CHECK-LLVMIR: %[[trg:.*]] = llvm.bitcast %[[addr]] : !llvm.ptr<i8> to !llvm.ptr<vector<2xi64>>
 963 ! CHECK-LLVMIR: llvm.store %[[src]], %[[trg]]
 964
 965 ! CHECK: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
 966 ! CHECK: %[[arg2:.*]] = load i64, ptr %1, align 8
 967 ! CHECK: %[[idx:.*]] = load i32, ptr %3, align 4
 968 ! CHECK: %[[idx64:.*]] = sext i32 %[[idx]] to i64
 969 ! CHECK: %[[idx64m1:.*]] = sub i64 %[[idx64]], 1
 970 ! CHECK: %[[elem:.*]] = getelementptr [10 x i32], ptr %2, i32 0, i64 %[[idx64m1]]
 971 ! CHECK: %[[trg:.*]] = getelementptr i8, ptr %[[elem]], i64 %6
 972 ! CHECK: %[[src:.*]] = bitcast <4 x i32> %[[arg1]] to <2 x i64>
 973 ! CHECK: store <2 x i64> %[[src]], ptr %[[trg]], align 1
 974 end subroutine vec_xstd2_test_vi4i8ia4
 975
 976 ! CHECK-LABEL: vec_xstd2_test_vi2i4vi2
 977 subroutine vec_xstd2_test_vi2i4vi2(arg1, arg2, arg3)
 978   vector(integer(2)) :: arg1
 979   integer(4) :: arg2
 980   vector(integer(2)) :: arg3
 981   call vec_xstd2(arg1, arg2, arg3)
 982
 983 ! CHECK-FIR: %[[arg1:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<8:i16>>
 984 ! CHECK-FIR: %[[arg2:.*]] = fir.load %arg1 : !fir.ref<i32>
 985 ! CHECK-FIR: %[[arg3:.*]] = fir.convert %arg2 : (!fir.ref<!fir.vector<8:i16>>) -> !fir.ref<!fir.array<?xi8>>
 986 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[arg3]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i32) -> !fir.ref<!fir.array<?xi8>>
 987 ! CHECK-FIR: %[[vsrc:.*]] = fir.convert %[[arg1]] : (!fir.vector<8:i16>) -> vector<8xi16>
 988 ! CHECK-FIR: %[[bcsrc:.*]] = vector.bitcast %[[vsrc]] : vector<8xi16> to vector<2xi64>
 989 ! CHECK-FIR: %[[trg:.*]] = fir.convert %[[addr]] : (!fir.ref<!fir.array<?xi8>>) -> !fir.ref<!fir.vector<2:i64>>
 990 ! CHECK-FIR: %[[cnvsrc:.*]] = fir.convert %[[bcsrc]] : (vector<2xi64>) -> !fir.vector<2:i64>
 991 ! CHECK-FIR: fir.store %[[cnvsrc]] to %[[trg]] {alignment = 1 : i64} : !fir.ref<!fir.vector<2:i64>>
 992
 993 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %arg0 : !llvm.ptr<vector<8xi16>>
 994 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %arg1 : !llvm.ptr<i32>
 995 ! CHECK-LLVMIR: %[[arg3:.*]] = llvm.bitcast %arg2 : !llvm.ptr<vector<8xi16>> to !llvm.ptr<i8>
 996 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[arg3]][%[[arg2]]] : (!llvm.ptr<i8>, i32) -> !llvm.ptr<i8>
 997 ! CHECK-LLVMIR: %[[src:.*]] = llvm.bitcast %[[arg1]] : vector<8xi16> to vector<2xi64>
 998 ! CHECK-LLVMIR: %[[trg:.*]] = llvm.bitcast %[[addr]] : !llvm.ptr<i8> to !llvm.ptr<vector<2xi64>>
 999 ! CHECK-LLVMIR: llvm.store %[[src]], %[[trg]]
1000
1001 ! CHECK: %[[arg1:.*]] = load <8 x i16>, ptr %0, align 16
1002 ! CHECK: %[[arg2:.*]] = load i32, ptr %1, align 4
1003 ! CHECK: %[[addr:.*]] = getelementptr i8, ptr %2, i32 %[[arg2]]
1004 ! CHECK: %[[src:.*]] = bitcast <8 x i16> %[[arg1]] to <2 x i64>
1005 ! CHECK:  store <2 x i64> %[[src]], ptr %[[addr]], align 1
1006 end subroutine vec_xstd2_test_vi2i4vi2
1007
1008 ! CHECK-LABEL: vec_xstd2_test_vi4i4vai4
1009 subroutine vec_xstd2_test_vi4i4vai4(arg1, arg2, arg3, i)
1010   vector(integer(4)) :: arg1
1011   integer(4) :: arg2
1012   vector(integer(4)) :: arg3(20)
1013   integer(4) :: i
1014   call vec_xstd2(arg1, arg2, arg3(i))
1015
1016 ! CHECK-FIR: %[[arg1:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<4:i32>>
1017 ! CHECK-FIR: %[[arg2:.*]] = fir.load %arg1 : !fir.ref<i32>
1018 ! CHECK-FIR: %[[idx:.*]] = fir.load %arg3 : !fir.ref<i32>
1019 ! CHECK-FIR: %[[idx64:.*]] = fir.convert %[[idx]] : (i32) -> i64
1020 ! CHECK-FIR: %[[one:.*]] = arith.constant 1 : i64
1021 ! CHECK-FIR: %[[idx64m1:.*]] = arith.subi %[[idx64]], %[[one]] : i64
1022 ! CHECK-FIR: %[[elem:.*]] = fir.coordinate_of %[[arg3:.*]], %[[idx64m1]] : (!fir.ref<!fir.array<20x!fir.vector<4:i32>>>, i64) -> !fir.ref<!fir.vector<4:i32>>
1023 ! CHECK-FIR: %[[elemptr:.*]] = fir.convert %[[elem]] : (!fir.ref<!fir.vector<4:i32>>) -> !fir.ref<!fir.array<?xi8>>
1024 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[elemptr]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i32) -> !fir.ref<!fir.array<?xi8>>
1025 ! CHECK-FIR: %[[vsrc:.*]] = fir.convert %[[arg1]] : (!fir.vector<4:i32>) -> vector<4xi32>
1026 ! CHECK-FIR: %[[bcsrc:.*]] = vector.bitcast %[[vsrc]] : vector<4xi32> to vector<2xi64>
1027 ! CHECK-FIR: %[[trg:.*]] = fir.convert %[[addr]] : (!fir.ref<!fir.array<?xi8>>) -> !fir.ref<!fir.vector<2:i64>>
1028 ! CHECK-FIR: %[[cnvsrc:.*]] = fir.convert %[[bcsrc]] : (vector<2xi64>) -> !fir.vector<2:i64>
1029 ! CHECK-FIR: fir.store %[[cnvsrc]] to %[[trg]] {alignment = 1 : i64} : !fir.ref<!fir.vector<2:i64>>
1030
1031 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %arg0 : !llvm.ptr<vector<4xi32>>
1032 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %arg1 : !llvm.ptr<i32>
1033 ! CHECK-LLVMIR: %[[idx:.*]] = llvm.load %arg3 : !llvm.ptr<i32>
1034 ! CHECK-LLVMIR: %[[idx64:.*]] = llvm.sext %[[idx]] : i32 to i64
1035 ! CHECK-LLVMIR: %[[one:.*]] = llvm.mlir.constant(1 : i64) : i64
1036 ! CHECK-LLVMIR: %[[idx64m1:.*]] = llvm.sub %[[idx64]], %[[one]]  : i64
1037 ! CHECK-LLVMIR: %[[elem:.*]] = llvm.getelementptr %[[arg3:.*]][0, %[[idx64m1]]] : (!llvm.ptr<array<20 x vector<4xi32>>>, i64) -> !llvm.ptr<vector<4xi32>>
1038 ! CHECK-LLVMIR: %[[elemptr:.*]] = llvm.bitcast %[[elem]] : !llvm.ptr<vector<4xi32>> to !llvm.ptr<i8>
1039 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[elemptr]][%[[arg2]]] : (!llvm.ptr<i8>, i32) -> !llvm.ptr<i8>
1040 ! CHECK-LLVMIR: %[[src:.*]] = llvm.bitcast %[[arg1]] : vector<4xi32> to vector<2xi64>
1041 ! CHECK-LLVMIR: %[[trg:.*]] = llvm.bitcast %[[addr]] : !llvm.ptr<i8> to !llvm.ptr<vector<2xi64>>
1042 ! CHECK-LLVMIR: llvm.store %[[src]], %[[trg]]
1043
1044 ! CHECK: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
1045 ! CHECK: %[[arg2:.*]] = load i32, ptr %1, align 4
1046 ! CHECK: %[[idx:.*]] = load i32, ptr %3, align 4
1047 ! CHECK: %[[idx64:.*]] = sext i32 %[[idx]] to i64
1048 ! CHECK: %[[idx64m1:.*]] = sub i64 %[[idx64]], 1
1049 ! CHECK: %[[elem:.*]] = getelementptr [20 x <4 x i32>], ptr %2, i32 0, i64 %[[idx64m1]]
1050 ! CHECK: %[[trg:.*]] = getelementptr i8, ptr %[[elem]], i32 %[[arg2]]
1051 ! CHECK: %[[src:.*]] = bitcast <4 x i32> %[[arg1]] to <2 x i64>
1052 ! CHECK: store <2 x i64> %[[src]], ptr %[[trg]], align 1
1053 end subroutine vec_xstd2_test_vi4i4vai4
1054
1055 !----------------------
1056 ! vec_xstw4
1057 !----------------------
1058
1059 ! CHECK-LABEL: vec_xstw4_test_vr4i2r4
1060 subroutine vec_xstw4_test_vr4i2r4(arg1, arg2, arg3)
1061   vector(real(4)) :: arg1
1062   integer(2) :: arg2
1063   real(4) :: arg3
1064   call vec_xstw4(arg1, arg2, arg3)
1065
1066 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:f32>>
1067 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<i16>
1068 ! CHECK-FIR: %[[arg3ptr:.*]] = fir.convert %arg2 : (!fir.ref<f32>) -> !fir.ref<!fir.array<?xi8>>
1069 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[arg3ptr]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i16) -> !fir.ref<!fir.array<?xi8>>
1070 ! CHECK-FIR: %[[vsrc:.*]] = fir.convert %[[arg1]] : (!fir.vector<4:f32>) -> vector<4xf32>
1071 ! CHECK-FIR: %[[trg:.*]] = fir.convert %[[addr]] : (!fir.ref<!fir.array<?xi8>>) -> !fir.ref<!fir.vector<4:f32>>
1072 ! CHECK-FIR: %[[cnvsrc:.*]] = fir.convert %[[vsrc]] : (vector<4xf32>) -> !fir.vector<4:f32>
1073 ! CHECK-FIR: fir.store %[[cnvsrc]] to %[[trg]] {alignment = 1 : i64} : !fir.ref<!fir.vector<4:f32>>
1074
1075 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xf32>>
1076 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<i16>
1077 ! CHECK-LLVMIR: %[[arg3ptr:.*]] = llvm.bitcast %{{.*}} : !llvm.ptr<f32> to !llvm.ptr<i8>
1078 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[arg3ptr]][%[[arg2]]] : (!llvm.ptr<i8>, i16) -> !llvm.ptr<i8>
1079 ! CHECK-LLVMIR: %[[trg:.*]] = llvm.bitcast %[[addr]] : !llvm.ptr<i8> to !llvm.ptr<vector<4xf32>>
1080 ! CHECK-LLVMIR: llvm.store %[[arg1]], %[[trg]]
1081
1082 ! CHECK: %[[arg1:.*]] = load <4 x float>, ptr %{{.*}}, align 16
1083 ! CHECK: %[[arg2:.*]] = load i16, ptr %{{.*}}, align 2
1084 ! CHECK: %[[addr:.*]] = getelementptr i8, ptr %{{.*}}, i16 %[[arg2]]
1085 ! CHECK: store <4 x float> %[[arg1]], ptr %[[addr]], align 1
1086 end subroutine vec_xstw4_test_vr4i2r4
1087
1088 ! CHECK-LABEL: vec_xstw4_test_vi4i8ia4
1089 subroutine vec_xstw4_test_vi4i8ia4(arg1, arg2, arg3, i)
1090   vector(integer(4)) :: arg1
1091   integer(8) :: arg2
1092   integer(4) :: arg3(10)
1093   integer(4) :: i
1094   call vec_xstw4(arg1, arg2, arg3(i))
1095
1096 ! CHECK-FIR: %[[arg1:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<4:i32>>
1097 ! CHECK-FIR: %[[arg2:.*]] = fir.load %arg1 : !fir.ref<i64>
1098 ! CHECK-FIR: %[[idx:.*]] = fir.load %arg3 : !fir.ref<i32>
1099 ! CHECK-FIR: %[[idx64:.*]] = fir.convert %[[idx]] : (i32) -> i64
1100 ! CHECK-FIR: %[[one:.*]] = arith.constant 1 : i64
1101 ! CHECK-FIR: %[[idx64m1:.*]] = arith.subi %[[idx64]], %[[one]] : i64
1102 ! CHECK-FIR: %[[elem:.*]] = fir.coordinate_of %arg2, %[[idx64m1]] : (!fir.ref<!fir.array<10xi32>>, i64) -> !fir.ref<i32>
1103 ! CHECK-FIR: %[[elemref:.*]] = fir.convert %[[elem]] : (!fir.ref<i32>) -> !fir.ref<!fir.array<?xi8>>
1104 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[elemref]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i64) -> !fir.ref<!fir.array<?xi8>>
1105 ! CHECK-FIR: %[[vsrc:.*]] = fir.convert %[[arg1]] : (!fir.vector<4:i32>) -> vector<4xi32>
1106 ! CHECK-FIR: %[[trg:.*]] = fir.convert %[[addr]] : (!fir.ref<!fir.array<?xi8>>) -> !fir.ref<!fir.vector<4:i32>>
1107 ! CHECK-FIR: %[[cnvsrc:.*]] = fir.convert %[[vsrc]] : (vector<4xi32>) -> !fir.vector<4:i32>
1108 ! CHECK-FIR: fir.store %[[cnvsrc]] to %[[trg]]
1109
1110 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %arg0 : !llvm.ptr<vector<4xi32>>
1111 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %arg1 : !llvm.ptr<i64>
1112 ! CHECK-LLVMIR: %[[idx:.*]] = llvm.load %arg3 : !llvm.ptr<i32>
1113 ! CHECK-LLVMIR: %[[idx64:.*]] = llvm.sext %[[idx]] : i32 to i64
1114 ! CHECK-LLVMIR: %[[one:.*]] = llvm.mlir.constant(1 : i64) : i64
1115 ! CHECK-LLVMIR: %[[idx64m1:.*]] = llvm.sub %[[idx64]], %[[one]]  : i64
1116 ! CHECK-LLVMIR: %[[elem:.*]] = llvm.getelementptr %arg2[0, %[[idx64m1]]] : (!llvm.ptr<array<10 x i32>>, i64) -> !llvm.ptr<i32>
1117 ! CHECK-LLVMIR: %[[elemref:.*]] = llvm.bitcast %[[elem]] : !llvm.ptr<i32> to !llvm.ptr<i8>
1118 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[elemref]][%[[arg2]]] : (!llvm.ptr<i8>, i64) -> !llvm.ptr<i8>
1119 ! CHECK-LLVMIR: %[[trg:.*]] = llvm.bitcast %[[addr]] : !llvm.ptr<i8> to !llvm.ptr<vector<4xi32>>
1120 ! CHECK-LLVMIR: llvm.store %[[arg1]], %[[trg]]
1121
1122 ! CHECK: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
1123 ! CHECK: %[[arg2:.*]] = load i64, ptr %1, align 8
1124 ! CHECK: %[[idx:.*]] = load i32, ptr %3, align 4
1125 ! CHECK: %[[idx64:.*]] = sext i32 %[[idx]] to i64
1126 ! CHECK: %[[idx64m1:.*]] = sub i64 %[[idx64]], 1
1127 ! CHECK: %[[elem:.*]] = getelementptr [10 x i32], ptr %2, i32 0, i64 %[[idx64m1]]
1128 ! CHECK: %[[trg:.*]] = getelementptr i8, ptr %[[elem]], i64 %6
1129 ! CHECK: store <4 x i32> %[[arg1]], ptr %[[trg]], align 1
1130 end subroutine vec_xstw4_test_vi4i8ia4
1131
1132 ! CHECK-LABEL: vec_xstw4_test_vi2i4vi2
1133 subroutine vec_xstw4_test_vi2i4vi2(arg1, arg2, arg3)
1134   vector(integer(2)) :: arg1
1135   integer(4) :: arg2
1136   vector(integer(2)) :: arg3
1137   call vec_xstw4(arg1, arg2, arg3)
1138
1139 ! CHECK-FIR: %[[arg1:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<8:i16>>
1140 ! CHECK-FIR: %[[arg2:.*]] = fir.load %arg1 : !fir.ref<i32>
1141 ! CHECK-FIR: %[[arg3:.*]] = fir.convert %arg2 : (!fir.ref<!fir.vector<8:i16>>) -> !fir.ref<!fir.array<?xi8>>
1142 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[arg3]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i32) -> !fir.ref<!fir.array<?xi8>>
1143 ! CHECK-FIR: %[[vsrc:.*]] = fir.convert %[[arg1]] : (!fir.vector<8:i16>) -> vector<8xi16>
1144 ! CHECK-FIR: %[[bcsrc:.*]] = vector.bitcast %[[vsrc]] : vector<8xi16> to vector<4xi32>
1145 ! CHECK-FIR: %[[trg:.*]] = fir.convert %[[addr]] : (!fir.ref<!fir.array<?xi8>>) -> !fir.ref<!fir.vector<4:i32>>
1146 ! CHECK-FIR: %[[cnvsrc:.*]] = fir.convert %[[bcsrc]] : (vector<4xi32>) -> !fir.vector<4:i32>
1147 ! CHECK-FIR: fir.store %[[cnvsrc]] to %[[trg]] {alignment = 1 : i64} : !fir.ref<!fir.vector<4:i32>>
1148
1149 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %arg0 : !llvm.ptr<vector<8xi16>>
1150 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %arg1 : !llvm.ptr<i32>
1151 ! CHECK-LLVMIR: %[[arg3:.*]] = llvm.bitcast %arg2 : !llvm.ptr<vector<8xi16>> to !llvm.ptr<i8>
1152 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[arg3]][%[[arg2]]] : (!llvm.ptr<i8>, i32) -> !llvm.ptr<i8>
1153 ! CHECK-LLVMIR: %[[src:.*]] = llvm.bitcast %[[arg1]] : vector<8xi16> to vector<4xi32>
1154 ! CHECK-LLVMIR: %[[trg:.*]] = llvm.bitcast %[[addr]] : !llvm.ptr<i8> to !llvm.ptr<vector<4xi32>>
1155 ! CHECK-LLVMIR: llvm.store %[[src]], %[[trg]]
1156
1157 ! CHECK: %[[arg1:.*]] = load <8 x i16>, ptr %0, align 16
1158 ! CHECK: %[[arg2:.*]] = load i32, ptr %1, align 4
1159 ! CHECK: %[[addr:.*]] = getelementptr i8, ptr %2, i32 %[[arg2]]
1160 ! CHECK: %[[src:.*]] = bitcast <8 x i16> %[[arg1]] to <4 x i32>
1161 ! CHECK:  store <4 x i32> %[[src]], ptr %[[addr]], align 1
1162 end subroutine vec_xstw4_test_vi2i4vi2
1163
1164 ! CHECK-LABEL: vec_xstw4_test_vi4i4vai4
1165 subroutine vec_xstw4_test_vi4i4vai4(arg1, arg2, arg3, i)
1166   vector(integer(4)) :: arg1
1167   integer(4) :: arg2
1168   vector(integer(4)) :: arg3(20)
1169   integer(4) :: i
1170   call vec_xstw4(arg1, arg2, arg3(i))
1171
1172 ! CHECK-FIR: %[[arg1:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<4:i32>>
1173 ! CHECK-FIR: %[[arg2:.*]] = fir.load %arg1 : !fir.ref<i32>
1174 ! CHECK-FIR: %[[idx:.*]] = fir.load %arg3 : !fir.ref<i32>
1175 ! CHECK-FIR: %[[idx64:.*]] = fir.convert %[[idx]] : (i32) -> i64
1176 ! CHECK-FIR: %[[one:.*]] = arith.constant 1 : i64
1177 ! CHECK-FIR: %[[idx64m1:.*]] = arith.subi %[[idx64]], %[[one]] : i64
1178 ! CHECK-FIR: %[[elem:.*]] = fir.coordinate_of %[[arg3:.*]], %[[idx64m1]] : (!fir.ref<!fir.array<20x!fir.vector<4:i32>>>, i64) -> !fir.ref<!fir.vector<4:i32>>
1179 ! CHECK-FIR: %[[elemptr:.*]] = fir.convert %[[elem]] : (!fir.ref<!fir.vector<4:i32>>) -> !fir.ref<!fir.array<?xi8>>
1180 ! CHECK-FIR: %[[addr:.*]] = fir.coordinate_of %[[elemptr]], %[[arg2]] : (!fir.ref<!fir.array<?xi8>>, i32) -> !fir.ref<!fir.array<?xi8>>
1181 ! CHECK-FIR: %[[vsrc:.*]] = fir.convert %[[arg1]] : (!fir.vector<4:i32>) -> vector<4xi32>
1182 ! CHECK-FIR: %[[trg:.*]] = fir.convert %[[addr]] : (!fir.ref<!fir.array<?xi8>>) -> !fir.ref<!fir.vector<4:i32>>
1183 ! CHECK-FIR: %[[cnvsrc:.*]] = fir.convert %[[vsrc]] : (vector<4xi32>) -> !fir.vector<4:i32>
1184 ! CHECK-FIR: fir.store %[[cnvsrc]] to %[[trg]]
1185
1186 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %arg0 : !llvm.ptr<vector<4xi32>>
1187 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %arg1 : !llvm.ptr<i32>
1188 ! CHECK-LLVMIR: %[[idx:.*]] = llvm.load %arg3 : !llvm.ptr<i32>
1189 ! CHECK-LLVMIR: %[[idx64:.*]] = llvm.sext %[[idx]] : i32 to i64
1190 ! CHECK-LLVMIR: %[[one:.*]] = llvm.mlir.constant(1 : i64) : i64
1191 ! CHECK-LLVMIR: %[[idx64m1:.*]] = llvm.sub %[[idx64]], %[[one]]  : i64
1192 ! CHECK-LLVMIR: %[[elem:.*]] = llvm.getelementptr %[[arg3:.*]][0, %[[idx64m1]]] : (!llvm.ptr<array<20 x vector<4xi32>>>, i64) -> !llvm.ptr<vector<4xi32>>
1193 ! CHECK-LLVMIR: %[[elemptr:.*]] = llvm.bitcast %[[elem]] : !llvm.ptr<vector<4xi32>> to !llvm.ptr<i8>
1194 ! CHECK-LLVMIR: %[[addr:.*]] = llvm.getelementptr %[[elemptr]][%[[arg2]]] : (!llvm.ptr<i8>, i32) -> !llvm.ptr<i8>
1195 ! CHECK-LLVMIR: %[[trg:.*]] = llvm.bitcast %[[addr]] : !llvm.ptr<i8> to !llvm.ptr<vector<4xi32>>
1196 ! CHECK-LLVMIR: llvm.store %[[arg1]], %[[trg]]
1197
1198 ! CHECK: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
1199 ! CHECK: %[[arg2:.*]] = load i32, ptr %1, align 4
1200 ! CHECK: %[[idx:.*]] = load i32, ptr %3, align 4
1201 ! CHECK: %[[idx64:.*]] = sext i32 %[[idx]] to i64
1202 ! CHECK: %[[idx64m1:.*]] = sub i64 %[[idx64]], 1
1203 ! CHECK: %[[elem:.*]] = getelementptr [20 x <4 x i32>], ptr %2, i32 0, i64 %[[idx64m1]]
1204 ! CHECK: %[[trg:.*]] = getelementptr i8, ptr %[[elem]], i32 %[[arg2]]
1205 ! CHECK: store <4 x i32> %[[arg1]], ptr %[[trg]], align 1
1206 end subroutine vec_xstw4_test_vi4i4vai4