clang/lib/Basic/Targets/PPC.h

   1 //===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file declares PPC TargetInfo objects.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
  14 #define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
  15
  16 #include "OSTargets.h"
  17 #include "clang/Basic/TargetInfo.h"
  18 #include "clang/Basic/TargetOptions.h"
  19 #include "llvm/ADT/Triple.h"
  20 #include "llvm/ADT/StringSwitch.h"
  21 #include "llvm/Support/Compiler.h"
  22
  23 namespace clang {
  24 namespace targets {
  25
  26 // PPC abstract base class
  27 class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
  28
  29   /// Flags for architecture specific defines.
  30   typedef enum {
  31     ArchDefineNone = 0,
  32     ArchDefineName = 1 << 0, // <name> is substituted for arch name.
  33     ArchDefinePpcgr = 1 << 1,
  34     ArchDefinePpcsq = 1 << 2,
  35     ArchDefine440 = 1 << 3,
  36     ArchDefine603 = 1 << 4,
  37     ArchDefine604 = 1 << 5,
  38     ArchDefinePwr4 = 1 << 6,
  39     ArchDefinePwr5 = 1 << 7,
  40     ArchDefinePwr5x = 1 << 8,
  41     ArchDefinePwr6 = 1 << 9,
  42     ArchDefinePwr6x = 1 << 10,
  43     ArchDefinePwr7 = 1 << 11,
  44     ArchDefinePwr8 = 1 << 12,
  45     ArchDefinePwr9 = 1 << 13,
  46     ArchDefinePwr10 = 1 << 14,
  47     ArchDefineFuture = 1 << 15,
  48     ArchDefineA2 = 1 << 16,
  49     ArchDefineE500 = 1 << 18
  50   } ArchDefineTypes;
  51
  52   ArchDefineTypes ArchDefs = ArchDefineNone;
  53   static const Builtin::Info BuiltinInfo[];
  54   static const char *const GCCRegNames[];
  55   static const TargetInfo::GCCRegAlias GCCRegAliases[];
  56   std::string CPU;
  57   enum PPCFloatABI { HardFloat, SoftFloat } FloatABI;
  58
  59   // Target cpu features.
  60   bool HasAltivec = false;
  61   bool HasMMA = false;
  62   bool HasROPProtect = false;
  63   bool HasPrivileged = false;
  64   bool HasVSX = false;
  65   bool UseCRBits = false;
  66   bool HasP8Vector = false;
  67   bool HasP8Crypto = false;
  68   bool HasDirectMove = false;
  69   bool HasHTM = false;
  70   bool HasBPERMD = false;
  71   bool HasExtDiv = false;
  72   bool HasP9Vector = false;
  73   bool HasSPE = false;
  74   bool PairedVectorMemops = false;
  75   bool HasP10Vector = false;
  76   bool HasPCRelativeMemops = false;
  77   bool HasPrefixInstrs = false;
  78   bool IsISA2_06 = false;
  79   bool IsISA2_07 = false;
  80   bool IsISA3_0 = false;
  81   bool IsISA3_1 = false;
  82   bool HasQuadwordAtomics = false;
  83
  84 protected:
  85   std::string ABI;
  86
  87 public:
  88   PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
  89       : TargetInfo(Triple) {
  90     SuitableAlign = 128;
  91     SimdDefaultAlign = 128;
  92     LongDoubleWidth = LongDoubleAlign = 128;
  93     LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
  94     HasStrictFP = true;
  95     HasIbm128 = true;
  96   }
  97
  98   // Set the language option for altivec based on our value.
  99   void adjust(DiagnosticsEngine &Diags, LangOptions &Opts) override;
 100
 101   // Note: GCC recognizes the following additional cpus:
 102   //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
 103   //  821, 823, 8540, e300c2, e300c3, e500mc64, e6500, 860, cell, titan, rs64.
 104   bool isValidCPUName(StringRef Name) const override;
 105   void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
 106
 107   bool setCPU(const std::string &Name) override {
 108     bool CPUKnown = isValidCPUName(Name);
 109     if (CPUKnown) {
 110       CPU = Name;
 111
 112       // CPU identification.
 113       ArchDefs =
 114           (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
 115               .Case("440", ArchDefineName)
 116               .Case("450", ArchDefineName | ArchDefine440)
 117               .Case("601", ArchDefineName)
 118               .Case("602", ArchDefineName | ArchDefinePpcgr)
 119               .Case("603", ArchDefineName | ArchDefinePpcgr)
 120               .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
 121               .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
 122               .Case("604", ArchDefineName | ArchDefinePpcgr)
 123               .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
 124               .Case("620", ArchDefineName | ArchDefinePpcgr)
 125               .Case("630", ArchDefineName | ArchDefinePpcgr)
 126               .Case("7400", ArchDefineName | ArchDefinePpcgr)
 127               .Case("7450", ArchDefineName | ArchDefinePpcgr)
 128               .Case("750", ArchDefineName | ArchDefinePpcgr)
 129               .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
 130                                ArchDefinePpcsq)
 131               .Case("a2", ArchDefineA2)
 132               .Cases("power3", "pwr3", ArchDefinePpcgr)
 133               .Cases("power4", "pwr4",
 134                      ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
 135               .Cases("power5", "pwr5",
 136                      ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
 137                          ArchDefinePpcsq)
 138               .Cases("power5x", "pwr5x",
 139                      ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
 140                          ArchDefinePpcgr | ArchDefinePpcsq)
 141               .Cases("power6", "pwr6",
 142                      ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
 143                          ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
 144               .Cases("power6x", "pwr6x",
 145                      ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
 146                          ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
 147                          ArchDefinePpcsq)
 148               .Cases("power7", "pwr7",
 149                      ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
 150                          ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
 151                          ArchDefinePpcsq)
 152               // powerpc64le automatically defaults to at least power8.
 153               .Cases("power8", "pwr8", "ppc64le",
 154                      ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
 155                          ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
 156                          ArchDefinePpcgr | ArchDefinePpcsq)
 157               .Cases("power9", "pwr9",
 158                      ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
 159                          ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
 160                          ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
 161               .Cases("power10", "pwr10",
 162                      ArchDefinePwr10 | ArchDefinePwr9 | ArchDefinePwr8 |
 163                          ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
 164                          ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
 165                          ArchDefinePpcsq)
 166               .Case("future",
 167                     ArchDefineFuture | ArchDefinePwr10 | ArchDefinePwr9 |
 168                         ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
 169                         ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
 170                         ArchDefinePpcgr | ArchDefinePpcsq)
 171               .Cases("8548", "e500", ArchDefineE500)
 172               .Default(ArchDefineNone);
 173     }
 174     return CPUKnown;
 175   }
 176
 177   StringRef getABI() const override { return ABI; }
 178
 179   ArrayRef<Builtin::Info> getTargetBuiltins() const override;
 180
 181   bool isCLZForZeroUndef() const override { return false; }
 182
 183   void getTargetDefines(const LangOptions &Opts,
 184                         MacroBuilder &Builder) const override;
 185
 186   bool
 187   initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
 188                  StringRef CPU,
 189                  const std::vector<std::string> &FeaturesVec) const override;
 190
 191   void addP10SpecificFeatures(llvm::StringMap<bool> &Features) const;
 192   void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const;
 193
 194   bool handleTargetFeatures(std::vector<std::string> &Features,
 195                             DiagnosticsEngine &Diags) override;
 196
 197   bool hasFeature(StringRef Feature) const override;
 198
 199   void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
 200                          bool Enabled) const override;
 201
 202   ArrayRef<const char *> getGCCRegNames() const override;
 203
 204   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
 205
 206   ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override;
 207
 208   bool validateAsmConstraint(const char *&Name,
 209                              TargetInfo::ConstraintInfo &Info) const override {
 210     switch (*Name) {
 211     default:
 212       return false;
 213     case 'O': // Zero
 214       break;
 215     case 'f': // Floating point register
 216       // Don't use floating point registers on soft float ABI.
 217       if (FloatABI == SoftFloat)
 218         return false;
 219       [[fallthrough]];
 220     case 'b': // Base register
 221       Info.setAllowsRegister();
 222       break;
 223     // FIXME: The following are added to allow parsing.
 224     // I just took a guess at what the actions should be.
 225     // Also, is more specific checking needed?  I.e. specific registers?
 226     case 'd': // Floating point register (containing 64-bit value)
 227     case 'v': // Altivec vector register
 228       // Don't use floating point and altivec vector registers
 229       // on soft float ABI
 230       if (FloatABI == SoftFloat)
 231         return false;
 232       Info.setAllowsRegister();
 233       break;
 234     case 'w':
 235       switch (Name[1]) {
 236       case 'd': // VSX vector register to hold vector double data
 237       case 'f': // VSX vector register to hold vector float data
 238       case 's': // VSX vector register to hold scalar double data
 239       case 'w': // VSX vector register to hold scalar double data
 240       case 'a': // Any VSX register
 241       case 'c': // An individual CR bit
 242       case 'i': // FP or VSX register to hold 64-bit integers data
 243         break;
 244       default:
 245         return false;
 246       }
 247       Info.setAllowsRegister();
 248       Name++; // Skip over 'w'.
 249       break;
 250     case 'h': // `MQ', `CTR', or `LINK' register
 251     case 'q': // `MQ' register
 252     case 'c': // `CTR' register
 253     case 'l': // `LINK' register
 254     case 'x': // `CR' register (condition register) number 0
 255     case 'y': // `CR' register (condition register)
 256     case 'z': // `XER[CA]' carry bit (part of the XER register)
 257       Info.setAllowsRegister();
 258       break;
 259     case 'I': // Signed 16-bit constant
 260     case 'J': // Unsigned 16-bit constant shifted left 16 bits
 261               //  (use `L' instead for SImode constants)
 262     case 'K': // Unsigned 16-bit constant
 263     case 'L': // Signed 16-bit constant shifted left 16 bits
 264     case 'M': // Constant larger than 31
 265     case 'N': // Exact power of 2
 266     case 'P': // Constant whose negation is a signed 16-bit constant
 267     case 'G': // Floating point constant that can be loaded into a
 268               // register with one instruction per word
 269     case 'H': // Integer/Floating point constant that can be loaded
 270               // into a register using three instructions
 271       break;
 272     case 'm': // Memory operand. Note that on PowerPC targets, m can
 273               // include addresses that update the base register. It
 274               // is therefore only safe to use `m' in an asm statement
 275               // if that asm statement accesses the operand exactly once.
 276               // The asm statement must also use `%U<opno>' as a
 277               // placeholder for the "update" flag in the corresponding
 278               // load or store instruction. For example:
 279               // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
 280               // is correct but:
 281               // asm ("st %1,%0" : "=m" (mem) : "r" (val));
 282               // is not. Use es rather than m if you don't want the base
 283               // register to be updated.
 284     case 'e':
 285       if (Name[1] != 's')
 286         return false;
 287       // es: A "stable" memory operand; that is, one which does not
 288       // include any automodification of the base register. Unlike
 289       // `m', this constraint can be used in asm statements that
 290       // might access the operand several times, or that might not
 291       // access it at all.
 292       Info.setAllowsMemory();
 293       Name++; // Skip over 'e'.
 294       break;
 295     case 'Q': // Memory operand that is an offset from a register (it is
 296               // usually better to use `m' or `es' in asm statements)
 297       Info.setAllowsRegister();
 298       [[fallthrough]];
 299     case 'Z': // Memory operand that is an indexed or indirect from a
 300               // register (it is usually better to use `m' or `es' in
 301               // asm statements)
 302       Info.setAllowsMemory();
 303       break;
 304     case 'R': // AIX TOC entry
 305     case 'a': // Address operand that is an indexed or indirect from a
 306               // register (`p' is preferable for asm statements)
 307     case 'S': // Constant suitable as a 64-bit mask operand
 308     case 'T': // Constant suitable as a 32-bit mask operand
 309     case 'U': // System V Release 4 small data area reference
 310     case 't': // AND masks that can be performed by two rldic{l, r}
 311               // instructions
 312     case 'W': // Vector constant that does not require memory
 313     case 'j': // Vector constant that is all zeros.
 314       break;
 315       // End FIXME.
 316     }
 317     return true;
 318   }
 319
 320   std::string convertConstraint(const char *&Constraint) const override {
 321     std::string R;
 322     switch (*Constraint) {
 323     case 'e':
 324     case 'w':
 325       // Two-character constraint; add "^" hint for later parsing.
 326       R = std::string("^") + std::string(Constraint, 2);
 327       Constraint++;
 328       break;
 329     default:
 330       return TargetInfo::convertConstraint(Constraint);
 331     }
 332     return R;
 333   }
 334
 335   const char *getClobbers() const override { return ""; }
 336   int getEHDataRegisterNumber(unsigned RegNo) const override {
 337     if (RegNo == 0)
 338       return 3;
 339     if (RegNo == 1)
 340       return 4;
 341     return -1;
 342   }
 343
 344   bool hasSjLjLowering() const override { return true; }
 345
 346   const char *getLongDoubleMangling() const override {
 347     if (LongDoubleWidth == 64)
 348       return "e";
 349     return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble()
 350                ? "g"
 351                : "u9__ieee128";
 352   }
 353   const char *getFloat128Mangling() const override { return "u9__ieee128"; }
 354   const char *getIbm128Mangling() const override { return "g"; }
 355
 356   bool hasBitIntType() const override { return true; }
 357
 358   bool isSPRegName(StringRef RegName) const override {
 359     return RegName.equals("r1") || RegName.equals("x1");
 360   }
 361 };
 362
 363 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
 364 public:
 365   PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
 366       : PPCTargetInfo(Triple, Opts) {
 367     if (Triple.isOSAIX())
 368       resetDataLayout("E-m:a-p:32:32-i64:64-n32");
 369     else if (Triple.getArch() == llvm::Triple::ppcle)
 370       resetDataLayout("e-m:e-p:32:32-i64:64-n32");
 371     else
 372       resetDataLayout("E-m:e-p:32:32-i64:64-n32");
 373
 374     switch (getTriple().getOS()) {
 375     case llvm::Triple::Linux:
 376     case llvm::Triple::FreeBSD:
 377     case llvm::Triple::NetBSD:
 378       SizeType = UnsignedInt;
 379       PtrDiffType = SignedInt;
 380       IntPtrType = SignedInt;
 381       break;
 382     case llvm::Triple::AIX:
 383       SizeType = UnsignedLong;
 384       PtrDiffType = SignedLong;
 385       IntPtrType = SignedLong;
 386       LongDoubleWidth = 64;
 387       LongDoubleAlign = DoubleAlign = 32;
 388       LongDoubleFormat = &llvm::APFloat::IEEEdouble();
 389       break;
 390     default:
 391       break;
 392     }
 393
 394     if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() ||
 395         Triple.isMusl()) {
 396       LongDoubleWidth = LongDoubleAlign = 64;
 397       LongDoubleFormat = &llvm::APFloat::IEEEdouble();
 398     }
 399
 400     // PPC32 supports atomics up to 4 bytes.
 401     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
 402   }
 403
 404   BuiltinVaListKind getBuiltinVaListKind() const override {
 405     // This is the ELF definition, and is overridden by the Darwin sub-target
 406     return TargetInfo::PowerABIBuiltinVaList;
 407   }
 408 };
 409
 410 // Note: ABI differences may eventually require us to have a separate
 411 // TargetInfo for little endian.
 412 class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo {
 413 public:
 414   PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
 415       : PPCTargetInfo(Triple, Opts) {
 416     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
 417     IntMaxType = SignedLong;
 418     Int64Type = SignedLong;
 419     std::string DataLayout;
 420
 421     if (Triple.isOSAIX()) {
 422       // TODO: Set appropriate ABI for AIX platform.
 423       DataLayout = "E-m:a-i64:64-n32:64";
 424       LongDoubleWidth = 64;
 425       LongDoubleAlign = DoubleAlign = 32;
 426       LongDoubleFormat = &llvm::APFloat::IEEEdouble();
 427     } else if ((Triple.getArch() == llvm::Triple::ppc64le)) {
 428       DataLayout = "e-m:e-i64:64-n32:64";
 429       ABI = "elfv2";
 430     } else {
 431       DataLayout = "E-m:e-i64:64-n32:64";
 432       ABI = "elfv1";
 433     }
 434
 435     if (Triple.isOSFreeBSD() || Triple.isOSOpenBSD() || Triple.isMusl()) {
 436       LongDoubleWidth = LongDoubleAlign = 64;
 437       LongDoubleFormat = &llvm::APFloat::IEEEdouble();
 438     }
 439
 440     if (Triple.isOSAIX() || Triple.isOSLinux())
 441       DataLayout += "-S128-v256:256:256-v512:512:512";
 442     resetDataLayout(DataLayout);
 443
 444     // Newer PPC64 instruction sets support atomics up to 16 bytes.
 445     MaxAtomicPromoteWidth = 128;
 446     // Baseline PPC64 supports inlining atomics up to 8 bytes.
 447     MaxAtomicInlineWidth = 64;
 448   }
 449
 450   void setMaxAtomicWidth() override {
 451     // For power8 and up, backend is able to inline 16-byte atomic lock free
 452     // code.
 453     // TODO: We should allow AIX to inline quadword atomics in the future.
 454     if (!getTriple().isOSAIX() && hasFeature("quadword-atomics"))
 455       MaxAtomicInlineWidth = 128;
 456   }
 457
 458   BuiltinVaListKind getBuiltinVaListKind() const override {
 459     return TargetInfo::CharPtrBuiltinVaList;
 460   }
 461
 462   // PPC64 Linux-specific ABI options.
 463   bool setABI(const std::string &Name) override {
 464     if (Name == "elfv1" || Name == "elfv2") {
 465       ABI = Name;
 466       return true;
 467     }
 468     return false;
 469   }
 470
 471   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
 472     switch (CC) {
 473     case CC_Swift:
 474       return CCCR_OK;
 475     case CC_SwiftAsync:
 476       return CCCR_Error;
 477     default:
 478       return CCCR_Warning;
 479     }
 480   }
 481 };
 482
 483 class LLVM_LIBRARY_VISIBILITY DarwinPPC32TargetInfo
 484     : public DarwinTargetInfo<PPC32TargetInfo> {
 485 public:
 486   DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
 487       : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) {
 488     HasAlignMac68kSupport = true;
 489     BoolWidth = BoolAlign = 32; // XXX support -mone-byte-bool?
 490     PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
 491     LongLongAlign = 32;
 492     resetDataLayout("E-m:o-p:32:32-f64:32:64-n32", "_");
 493   }
 494
 495   BuiltinVaListKind getBuiltinVaListKind() const override {
 496     return TargetInfo::CharPtrBuiltinVaList;
 497   }
 498 };
 499
 500 class LLVM_LIBRARY_VISIBILITY DarwinPPC64TargetInfo
 501     : public DarwinTargetInfo<PPC64TargetInfo> {
 502 public:
 503   DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
 504       : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) {
 505     HasAlignMac68kSupport = true;
 506     resetDataLayout("E-m:o-i64:64-n32:64", "_");
 507   }
 508 };
 509
 510 class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo :
 511   public AIXTargetInfo<PPC32TargetInfo> {
 512 public:
 513   using AIXTargetInfo::AIXTargetInfo;
 514   BuiltinVaListKind getBuiltinVaListKind() const override {
 515     return TargetInfo::CharPtrBuiltinVaList;
 516   }
 517 };
 518
 519 class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo :
 520   public AIXTargetInfo<PPC64TargetInfo> {
 521 public:
 522   using AIXTargetInfo::AIXTargetInfo;
 523 };
 524
 525 } // namespace targets
 526 } // namespace clang
 527 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H