clang/lib/Basic/Targets/X86.cpp

   1 //===--- X86.cpp - Implement X86 target feature support -------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file implements X86 TargetInfo objects.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "X86.h"
  14 #include "clang/Basic/Builtins.h"
  15 #include "clang/Basic/Diagnostic.h"
  16 #include "clang/Basic/TargetBuiltins.h"
  17 #include "llvm/ADT/StringExtras.h"
  18 #include "llvm/ADT/StringRef.h"
  19 #include "llvm/ADT/StringSwitch.h"
  20 #include "llvm/Support/X86TargetParser.h"
  21
  22 namespace clang {
  23 namespace targets {
  24
  25 const Builtin::Info BuiltinInfoX86[] = {
  26 #define BUILTIN(ID, TYPE, ATTRS)                                               \
  27   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
  28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
  29   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
  30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
  31   {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
  32 #include "clang/Basic/BuiltinsX86.def"
  33
  34 #define BUILTIN(ID, TYPE, ATTRS)                                               \
  35   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
  36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
  37   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
  38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
  39   {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
  40 #include "clang/Basic/BuiltinsX86_64.def"
  41 };
  42
  43 static const char *const GCCRegNames[] = {
  44     "ax",    "dx",    "cx",    "bx",    "si",      "di",    "bp",    "sp",
  45     "st",    "st(1)", "st(2)", "st(3)", "st(4)",   "st(5)", "st(6)", "st(7)",
  46     "argp",  "flags", "fpcr",  "fpsr",  "dirflag", "frame", "xmm0",  "xmm1",
  47     "xmm2",  "xmm3",  "xmm4",  "xmm5",  "xmm6",    "xmm7",  "mm0",   "mm1",
  48     "mm2",   "mm3",   "mm4",   "mm5",   "mm6",     "mm7",   "r8",    "r9",
  49     "r10",   "r11",   "r12",   "r13",   "r14",     "r15",   "xmm8",  "xmm9",
  50     "xmm10", "xmm11", "xmm12", "xmm13", "xmm14",   "xmm15", "ymm0",  "ymm1",
  51     "ymm2",  "ymm3",  "ymm4",  "ymm5",  "ymm6",    "ymm7",  "ymm8",  "ymm9",
  52     "ymm10", "ymm11", "ymm12", "ymm13", "ymm14",   "ymm15", "xmm16", "xmm17",
  53     "xmm18", "xmm19", "xmm20", "xmm21", "xmm22",   "xmm23", "xmm24", "xmm25",
  54     "xmm26", "xmm27", "xmm28", "xmm29", "xmm30",   "xmm31", "ymm16", "ymm17",
  55     "ymm18", "ymm19", "ymm20", "ymm21", "ymm22",   "ymm23", "ymm24", "ymm25",
  56     "ymm26", "ymm27", "ymm28", "ymm29", "ymm30",   "ymm31", "zmm0",  "zmm1",
  57     "zmm2",  "zmm3",  "zmm4",  "zmm5",  "zmm6",    "zmm7",  "zmm8",  "zmm9",
  58     "zmm10", "zmm11", "zmm12", "zmm13", "zmm14",   "zmm15", "zmm16", "zmm17",
  59     "zmm18", "zmm19", "zmm20", "zmm21", "zmm22",   "zmm23", "zmm24", "zmm25",
  60     "zmm26", "zmm27", "zmm28", "zmm29", "zmm30",   "zmm31", "k0",    "k1",
  61     "k2",    "k3",    "k4",    "k5",    "k6",      "k7",
  62     "cr0",   "cr2",   "cr3",   "cr4",   "cr8",
  63     "dr0",   "dr1",   "dr2",   "dr3",   "dr6",     "dr7",
  64     "bnd0",  "bnd1",  "bnd2",  "bnd3",
  65     "tmm0",  "tmm1",  "tmm2",  "tmm3",  "tmm4",    "tmm5",  "tmm6",  "tmm7",
  66 };
  67
  68 const TargetInfo::AddlRegName AddlRegNames[] = {
  69     {{"al", "ah", "eax", "rax"}, 0},
  70     {{"bl", "bh", "ebx", "rbx"}, 3},
  71     {{"cl", "ch", "ecx", "rcx"}, 2},
  72     {{"dl", "dh", "edx", "rdx"}, 1},
  73     {{"esi", "rsi"}, 4},
  74     {{"edi", "rdi"}, 5},
  75     {{"esp", "rsp"}, 7},
  76     {{"ebp", "rbp"}, 6},
  77     {{"r8d", "r8w", "r8b"}, 38},
  78     {{"r9d", "r9w", "r9b"}, 39},
  79     {{"r10d", "r10w", "r10b"}, 40},
  80     {{"r11d", "r11w", "r11b"}, 41},
  81     {{"r12d", "r12w", "r12b"}, 42},
  82     {{"r13d", "r13w", "r13b"}, 43},
  83     {{"r14d", "r14w", "r14b"}, 44},
  84     {{"r15d", "r15w", "r15b"}, 45},
  85 };
  86
  87 } // namespace targets
  88 } // namespace clang
  89
  90 using namespace clang;
  91 using namespace clang::targets;
  92
  93 bool X86TargetInfo::setFPMath(StringRef Name) {
  94   if (Name == "387") {
  95     FPMath = FP_387;
  96     return true;
  97   }
  98   if (Name == "sse") {
  99     FPMath = FP_SSE;
 100     return true;
 101   }
 102   return false;
 103 }
 104
 105 bool X86TargetInfo::initFeatureMap(
 106     llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
 107     const std::vector<std::string> &FeaturesVec) const {
 108   // FIXME: This *really* should not be here.
 109   // X86_64 always has SSE2.
 110   if (getTriple().getArch() == llvm::Triple::x86_64)
 111     setFeatureEnabled(Features, "sse2", true);
 112
 113   using namespace llvm::X86;
 114
 115   SmallVector<StringRef, 16> CPUFeatures;
 116   getFeaturesForCPU(CPU, CPUFeatures);
 117   for (auto &F : CPUFeatures)
 118     setFeatureEnabled(Features, F, true);
 119
 120   std::vector<std::string> UpdatedFeaturesVec;
 121   for (const auto &Feature : FeaturesVec) {
 122     // Expand general-regs-only to -x86, -mmx and -sse
 123     if (Feature == "+general-regs-only") {
 124       UpdatedFeaturesVec.push_back("-x87");
 125       UpdatedFeaturesVec.push_back("-mmx");
 126       UpdatedFeaturesVec.push_back("-sse");
 127       continue;
 128     }
 129
 130     UpdatedFeaturesVec.push_back(Feature);
 131   }
 132
 133   if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec))
 134     return false;
 135
 136   // Can't do this earlier because we need to be able to explicitly enable
 137   // or disable these features and the things that they depend upon.
 138
 139   // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
 140   auto I = Features.find("sse4.2");
 141   if (I != Features.end() && I->getValue() &&
 142       !llvm::is_contained(UpdatedFeaturesVec, "-popcnt"))
 143     Features["popcnt"] = true;
 144
 145   // Additionally, if SSE is enabled and mmx is not explicitly disabled,
 146   // then enable MMX.
 147   I = Features.find("sse");
 148   if (I != Features.end() && I->getValue() &&
 149       !llvm::is_contained(UpdatedFeaturesVec, "-mmx"))
 150     Features["mmx"] = true;
 151
 152   // Enable xsave if avx is enabled and xsave is not explicitly disabled.
 153   I = Features.find("avx");
 154   if (I != Features.end() && I->getValue() &&
 155       !llvm::is_contained(UpdatedFeaturesVec, "-xsave"))
 156     Features["xsave"] = true;
 157
 158   // Enable CRC32 if SSE4.2 is enabled and CRC32 is not explicitly disabled.
 159   I = Features.find("sse4.2");
 160   if (I != Features.end() && I->getValue() &&
 161       !llvm::is_contained(UpdatedFeaturesVec, "-crc32"))
 162     Features["crc32"] = true;
 163
 164   return true;
 165 }
 166
 167 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
 168                                       StringRef Name, bool Enabled) const {
 169   if (Name == "sse4") {
 170     // We can get here via the __target__ attribute since that's not controlled
 171     // via the -msse4/-mno-sse4 command line alias. Handle this the same way
 172     // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
 173     // disabled.
 174     if (Enabled)
 175       Name = "sse4.2";
 176     else
 177       Name = "sse4.1";
 178   }
 179
 180   Features[Name] = Enabled;
 181   llvm::X86::updateImpliedFeatures(Name, Enabled, Features);
 182 }
 183
 184 /// handleTargetFeatures - Perform initialization based on the user
 185 /// configured set of features.
 186 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
 187                                          DiagnosticsEngine &Diags) {
 188   for (const auto &Feature : Features) {
 189     if (Feature[0] != '+')
 190       continue;
 191
 192     if (Feature == "+aes") {
 193       HasAES = true;
 194     } else if (Feature == "+vaes") {
 195       HasVAES = true;
 196     } else if (Feature == "+pclmul") {
 197       HasPCLMUL = true;
 198     } else if (Feature == "+vpclmulqdq") {
 199       HasVPCLMULQDQ = true;
 200     } else if (Feature == "+lzcnt") {
 201       HasLZCNT = true;
 202     } else if (Feature == "+rdrnd") {
 203       HasRDRND = true;
 204     } else if (Feature == "+fsgsbase") {
 205       HasFSGSBASE = true;
 206     } else if (Feature == "+bmi") {
 207       HasBMI = true;
 208     } else if (Feature == "+bmi2") {
 209       HasBMI2 = true;
 210     } else if (Feature == "+popcnt") {
 211       HasPOPCNT = true;
 212     } else if (Feature == "+rtm") {
 213       HasRTM = true;
 214     } else if (Feature == "+prfchw") {
 215       HasPRFCHW = true;
 216     } else if (Feature == "+rdseed") {
 217       HasRDSEED = true;
 218     } else if (Feature == "+adx") {
 219       HasADX = true;
 220     } else if (Feature == "+tbm") {
 221       HasTBM = true;
 222     } else if (Feature == "+lwp") {
 223       HasLWP = true;
 224     } else if (Feature == "+fma") {
 225       HasFMA = true;
 226     } else if (Feature == "+f16c") {
 227       HasF16C = true;
 228     } else if (Feature == "+gfni") {
 229       HasGFNI = true;
 230     } else if (Feature == "+avx512cd") {
 231       HasAVX512CD = true;
 232     } else if (Feature == "+avx512vpopcntdq") {
 233       HasAVX512VPOPCNTDQ = true;
 234     } else if (Feature == "+avx512vnni") {
 235       HasAVX512VNNI = true;
 236     } else if (Feature == "+avx512bf16") {
 237       HasAVX512BF16 = true;
 238     } else if (Feature == "+avx512er") {
 239       HasAVX512ER = true;
 240     } else if (Feature == "+avx512fp16") {
 241       HasAVX512FP16 = true;
 242       HasLegalHalfType = true;
 243     } else if (Feature == "+avx512pf") {
 244       HasAVX512PF = true;
 245     } else if (Feature == "+avx512dq") {
 246       HasAVX512DQ = true;
 247     } else if (Feature == "+avx512bitalg") {
 248       HasAVX512BITALG = true;
 249     } else if (Feature == "+avx512bw") {
 250       HasAVX512BW = true;
 251     } else if (Feature == "+avx512vl") {
 252       HasAVX512VL = true;
 253     } else if (Feature == "+avx512vbmi") {
 254       HasAVX512VBMI = true;
 255     } else if (Feature == "+avx512vbmi2") {
 256       HasAVX512VBMI2 = true;
 257     } else if (Feature == "+avx512ifma") {
 258       HasAVX512IFMA = true;
 259     } else if (Feature == "+avx512vp2intersect") {
 260       HasAVX512VP2INTERSECT = true;
 261     } else if (Feature == "+sha") {
 262       HasSHA = true;
 263     } else if (Feature == "+shstk") {
 264       HasSHSTK = true;
 265     } else if (Feature == "+movbe") {
 266       HasMOVBE = true;
 267     } else if (Feature == "+sgx") {
 268       HasSGX = true;
 269     } else if (Feature == "+cx8") {
 270       HasCX8 = true;
 271     } else if (Feature == "+cx16") {
 272       HasCX16 = true;
 273     } else if (Feature == "+fxsr") {
 274       HasFXSR = true;
 275     } else if (Feature == "+xsave") {
 276       HasXSAVE = true;
 277     } else if (Feature == "+xsaveopt") {
 278       HasXSAVEOPT = true;
 279     } else if (Feature == "+xsavec") {
 280       HasXSAVEC = true;
 281     } else if (Feature == "+xsaves") {
 282       HasXSAVES = true;
 283     } else if (Feature == "+mwaitx") {
 284       HasMWAITX = true;
 285     } else if (Feature == "+pku") {
 286       HasPKU = true;
 287     } else if (Feature == "+clflushopt") {
 288       HasCLFLUSHOPT = true;
 289     } else if (Feature == "+clwb") {
 290       HasCLWB = true;
 291     } else if (Feature == "+wbnoinvd") {
 292       HasWBNOINVD = true;
 293     } else if (Feature == "+prefetchwt1") {
 294       HasPREFETCHWT1 = true;
 295     } else if (Feature == "+clzero") {
 296       HasCLZERO = true;
 297     } else if (Feature == "+cldemote") {
 298       HasCLDEMOTE = true;
 299     } else if (Feature == "+rdpid") {
 300       HasRDPID = true;
 301     } else if (Feature == "+rdpru") {
 302       HasRDPRU = true;
 303     } else if (Feature == "+kl") {
 304       HasKL = true;
 305     } else if (Feature == "+widekl") {
 306       HasWIDEKL = true;
 307     } else if (Feature == "+retpoline-external-thunk") {
 308       HasRetpolineExternalThunk = true;
 309     } else if (Feature == "+sahf") {
 310       HasLAHFSAHF = true;
 311     } else if (Feature == "+waitpkg") {
 312       HasWAITPKG = true;
 313     } else if (Feature == "+movdiri") {
 314       HasMOVDIRI = true;
 315     } else if (Feature == "+movdir64b") {
 316       HasMOVDIR64B = true;
 317     } else if (Feature == "+pconfig") {
 318       HasPCONFIG = true;
 319     } else if (Feature == "+ptwrite") {
 320       HasPTWRITE = true;
 321     } else if (Feature == "+invpcid") {
 322       HasINVPCID = true;
 323     } else if (Feature == "+enqcmd") {
 324       HasENQCMD = true;
 325     } else if (Feature == "+hreset") {
 326       HasHRESET = true;
 327     } else if (Feature == "+amx-bf16") {
 328       HasAMXBF16 = true;
 329     } else if (Feature == "+amx-int8") {
 330       HasAMXINT8 = true;
 331     } else if (Feature == "+amx-tile") {
 332       HasAMXTILE = true;
 333     } else if (Feature == "+avxvnni") {
 334       HasAVXVNNI = true;
 335     } else if (Feature == "+serialize") {
 336       HasSERIALIZE = true;
 337     } else if (Feature == "+tsxldtrk") {
 338       HasTSXLDTRK = true;
 339     } else if (Feature == "+uintr") {
 340       HasUINTR = true;
 341     } else if (Feature == "+crc32") {
 342       HasCRC32 = true;
 343     } else if (Feature == "+x87") {
 344       HasX87 = true;
 345     }
 346
 347     X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
 348                            .Case("+avx512f", AVX512F)
 349                            .Case("+avx2", AVX2)
 350                            .Case("+avx", AVX)
 351                            .Case("+sse4.2", SSE42)
 352                            .Case("+sse4.1", SSE41)
 353                            .Case("+ssse3", SSSE3)
 354                            .Case("+sse3", SSE3)
 355                            .Case("+sse2", SSE2)
 356                            .Case("+sse", SSE1)
 357                            .Default(NoSSE);
 358     SSELevel = std::max(SSELevel, Level);
 359
 360     HasFloat16 = SSELevel >= SSE2;
 361
 362     HasBFloat16 = SSELevel >= SSE2;
 363
 364     MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature)
 365                                       .Case("+3dnowa", AMD3DNowAthlon)
 366                                       .Case("+3dnow", AMD3DNow)
 367                                       .Case("+mmx", MMX)
 368                                       .Default(NoMMX3DNow);
 369     MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
 370
 371     XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
 372                          .Case("+xop", XOP)
 373                          .Case("+fma4", FMA4)
 374                          .Case("+sse4a", SSE4A)
 375                          .Default(NoXOP);
 376     XOPLevel = std::max(XOPLevel, XLevel);
 377   }
 378
 379   // LLVM doesn't have a separate switch for fpmath, so only accept it if it
 380   // matches the selected sse level.
 381   if ((FPMath == FP_SSE && SSELevel < SSE1) ||
 382       (FPMath == FP_387 && SSELevel >= SSE1)) {
 383     Diags.Report(diag::err_target_unsupported_fpmath)
 384         << (FPMath == FP_SSE ? "sse" : "387");
 385     return false;
 386   }
 387
 388   SimdDefaultAlign =
 389       hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
 390
 391   // FIXME: We should allow long double type on 32-bits to match with GCC.
 392   // This requires backend to be able to lower f80 without x87 first.
 393   if (!HasX87 && LongDoubleFormat == &llvm::APFloat::x87DoubleExtended())
 394     HasLongDouble = false;
 395
 396   return true;
 397 }
 398
 399 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
 400 /// definitions for this particular subtarget.
 401 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
 402                                      MacroBuilder &Builder) const {
 403   // Inline assembly supports X86 flag outputs.
 404   Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
 405
 406   std::string CodeModel = getTargetOpts().CodeModel;
 407   if (CodeModel == "default")
 408     CodeModel = "small";
 409   Builder.defineMacro("__code_model_" + CodeModel + "__");
 410
 411   // Target identification.
 412   if (getTriple().getArch() == llvm::Triple::x86_64) {
 413     Builder.defineMacro("__amd64__");
 414     Builder.defineMacro("__amd64");
 415     Builder.defineMacro("__x86_64");
 416     Builder.defineMacro("__x86_64__");
 417     if (getTriple().getArchName() == "x86_64h") {
 418       Builder.defineMacro("__x86_64h");
 419       Builder.defineMacro("__x86_64h__");
 420     }
 421   } else {
 422     DefineStd(Builder, "i386", Opts);
 423   }
 424
 425   Builder.defineMacro("__SEG_GS");
 426   Builder.defineMacro("__SEG_FS");
 427   Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))");
 428   Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))");
 429
 430   // Subtarget options.
 431   // FIXME: We are hard-coding the tune parameters based on the CPU, but they
 432   // truly should be based on -mtune options.
 433   using namespace llvm::X86;
 434   switch (CPU) {
 435   case CK_None:
 436     break;
 437   case CK_i386:
 438     // The rest are coming from the i386 define above.
 439     Builder.defineMacro("__tune_i386__");
 440     break;
 441   case CK_i486:
 442   case CK_WinChipC6:
 443   case CK_WinChip2:
 444   case CK_C3:
 445     defineCPUMacros(Builder, "i486");
 446     break;
 447   case CK_PentiumMMX:
 448     Builder.defineMacro("__pentium_mmx__");
 449     Builder.defineMacro("__tune_pentium_mmx__");
 450     [[fallthrough]];
 451   case CK_i586:
 452   case CK_Pentium:
 453     defineCPUMacros(Builder, "i586");
 454     defineCPUMacros(Builder, "pentium");
 455     break;
 456   case CK_Pentium3:
 457   case CK_PentiumM:
 458     Builder.defineMacro("__tune_pentium3__");
 459     [[fallthrough]];
 460   case CK_Pentium2:
 461   case CK_C3_2:
 462     Builder.defineMacro("__tune_pentium2__");
 463     [[fallthrough]];
 464   case CK_PentiumPro:
 465   case CK_i686:
 466     defineCPUMacros(Builder, "i686");
 467     defineCPUMacros(Builder, "pentiumpro");
 468     break;
 469   case CK_Pentium4:
 470     defineCPUMacros(Builder, "pentium4");
 471     break;
 472   case CK_Yonah:
 473   case CK_Prescott:
 474   case CK_Nocona:
 475     defineCPUMacros(Builder, "nocona");
 476     break;
 477   case CK_Core2:
 478   case CK_Penryn:
 479     defineCPUMacros(Builder, "core2");
 480     break;
 481   case CK_Bonnell:
 482     defineCPUMacros(Builder, "atom");
 483     break;
 484   case CK_Silvermont:
 485     defineCPUMacros(Builder, "slm");
 486     break;
 487   case CK_Goldmont:
 488     defineCPUMacros(Builder, "goldmont");
 489     break;
 490   case CK_GoldmontPlus:
 491     defineCPUMacros(Builder, "goldmont_plus");
 492     break;
 493   case CK_Tremont:
 494     defineCPUMacros(Builder, "tremont");
 495     break;
 496   case CK_Nehalem:
 497   case CK_Westmere:
 498   case CK_SandyBridge:
 499   case CK_IvyBridge:
 500   case CK_Haswell:
 501   case CK_Broadwell:
 502   case CK_SkylakeClient:
 503   case CK_SkylakeServer:
 504   case CK_Cascadelake:
 505   case CK_Cooperlake:
 506   case CK_Cannonlake:
 507   case CK_IcelakeClient:
 508   case CK_Rocketlake:
 509   case CK_IcelakeServer:
 510   case CK_Tigerlake:
 511   case CK_SapphireRapids:
 512   case CK_Alderlake:
 513     // FIXME: Historically, we defined this legacy name, it would be nice to
 514     // remove it at some point. We've never exposed fine-grained names for
 515     // recent primary x86 CPUs, and we should keep it that way.
 516     defineCPUMacros(Builder, "corei7");
 517     break;
 518   case CK_KNL:
 519     defineCPUMacros(Builder, "knl");
 520     break;
 521   case CK_KNM:
 522     break;
 523   case CK_Lakemont:
 524     defineCPUMacros(Builder, "i586", /*Tuning*/false);
 525     defineCPUMacros(Builder, "pentium", /*Tuning*/false);
 526     Builder.defineMacro("__tune_lakemont__");
 527     break;
 528   case CK_K6_2:
 529     Builder.defineMacro("__k6_2__");
 530     Builder.defineMacro("__tune_k6_2__");
 531     [[fallthrough]];
 532   case CK_K6_3:
 533     if (CPU != CK_K6_2) { // In case of fallthrough
 534       // FIXME: GCC may be enabling these in cases where some other k6
 535       // architecture is specified but -m3dnow is explicitly provided. The
 536       // exact semantics need to be determined and emulated here.
 537       Builder.defineMacro("__k6_3__");
 538       Builder.defineMacro("__tune_k6_3__");
 539     }
 540     [[fallthrough]];
 541   case CK_K6:
 542     defineCPUMacros(Builder, "k6");
 543     break;
 544   case CK_Athlon:
 545   case CK_AthlonXP:
 546     defineCPUMacros(Builder, "athlon");
 547     if (SSELevel != NoSSE) {
 548       Builder.defineMacro("__athlon_sse__");
 549       Builder.defineMacro("__tune_athlon_sse__");
 550     }
 551     break;
 552   case CK_K8:
 553   case CK_K8SSE3:
 554   case CK_x86_64:
 555     defineCPUMacros(Builder, "k8");
 556     break;
 557   case CK_x86_64_v2:
 558   case CK_x86_64_v3:
 559   case CK_x86_64_v4:
 560     break;
 561   case CK_AMDFAM10:
 562     defineCPUMacros(Builder, "amdfam10");
 563     break;
 564   case CK_BTVER1:
 565     defineCPUMacros(Builder, "btver1");
 566     break;
 567   case CK_BTVER2:
 568     defineCPUMacros(Builder, "btver2");
 569     break;
 570   case CK_BDVER1:
 571     defineCPUMacros(Builder, "bdver1");
 572     break;
 573   case CK_BDVER2:
 574     defineCPUMacros(Builder, "bdver2");
 575     break;
 576   case CK_BDVER3:
 577     defineCPUMacros(Builder, "bdver3");
 578     break;
 579   case CK_BDVER4:
 580     defineCPUMacros(Builder, "bdver4");
 581     break;
 582   case CK_ZNVER1:
 583     defineCPUMacros(Builder, "znver1");
 584     break;
 585   case CK_ZNVER2:
 586     defineCPUMacros(Builder, "znver2");
 587     break;
 588   case CK_ZNVER3:
 589     defineCPUMacros(Builder, "znver3");
 590     break;
 591   case CK_Geode:
 592     defineCPUMacros(Builder, "geode");
 593     break;
 594   }
 595
 596   // Target properties.
 597   Builder.defineMacro("__REGISTER_PREFIX__", "");
 598
 599   // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
 600   // functions in glibc header files that use FP Stack inline asm which the
 601   // backend can't deal with (PR879).
 602   Builder.defineMacro("__NO_MATH_INLINES");
 603
 604   if (HasAES)
 605     Builder.defineMacro("__AES__");
 606
 607   if (HasVAES)
 608     Builder.defineMacro("__VAES__");
 609
 610   if (HasPCLMUL)
 611     Builder.defineMacro("__PCLMUL__");
 612
 613   if (HasVPCLMULQDQ)
 614     Builder.defineMacro("__VPCLMULQDQ__");
 615
 616   // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM,
 617   // the feature flag only applies to 64-bit mode.
 618   if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86)
 619     Builder.defineMacro("__LAHF_SAHF__");
 620
 621   if (HasLZCNT)
 622     Builder.defineMacro("__LZCNT__");
 623
 624   if (HasRDRND)
 625     Builder.defineMacro("__RDRND__");
 626
 627   if (HasFSGSBASE)
 628     Builder.defineMacro("__FSGSBASE__");
 629
 630   if (HasBMI)
 631     Builder.defineMacro("__BMI__");
 632
 633   if (HasBMI2)
 634     Builder.defineMacro("__BMI2__");
 635
 636   if (HasPOPCNT)
 637     Builder.defineMacro("__POPCNT__");
 638
 639   if (HasRTM)
 640     Builder.defineMacro("__RTM__");
 641
 642   if (HasPRFCHW)
 643     Builder.defineMacro("__PRFCHW__");
 644
 645   if (HasRDSEED)
 646     Builder.defineMacro("__RDSEED__");
 647
 648   if (HasADX)
 649     Builder.defineMacro("__ADX__");
 650
 651   if (HasTBM)
 652     Builder.defineMacro("__TBM__");
 653
 654   if (HasLWP)
 655     Builder.defineMacro("__LWP__");
 656
 657   if (HasMWAITX)
 658     Builder.defineMacro("__MWAITX__");
 659
 660   if (HasMOVBE)
 661     Builder.defineMacro("__MOVBE__");
 662
 663   switch (XOPLevel) {
 664   case XOP:
 665     Builder.defineMacro("__XOP__");
 666     [[fallthrough]];
 667   case FMA4:
 668     Builder.defineMacro("__FMA4__");
 669     [[fallthrough]];
 670   case SSE4A:
 671     Builder.defineMacro("__SSE4A__");
 672     [[fallthrough]];
 673   case NoXOP:
 674     break;
 675   }
 676
 677   if (HasFMA)
 678     Builder.defineMacro("__FMA__");
 679
 680   if (HasF16C)
 681     Builder.defineMacro("__F16C__");
 682
 683   if (HasGFNI)
 684     Builder.defineMacro("__GFNI__");
 685
 686   if (HasAVX512CD)
 687     Builder.defineMacro("__AVX512CD__");
 688   if (HasAVX512VPOPCNTDQ)
 689     Builder.defineMacro("__AVX512VPOPCNTDQ__");
 690   if (HasAVX512VNNI)
 691     Builder.defineMacro("__AVX512VNNI__");
 692   if (HasAVX512BF16)
 693     Builder.defineMacro("__AVX512BF16__");
 694   if (HasAVX512ER)
 695     Builder.defineMacro("__AVX512ER__");
 696   if (HasAVX512FP16)
 697     Builder.defineMacro("__AVX512FP16__");
 698   if (HasAVX512PF)
 699     Builder.defineMacro("__AVX512PF__");
 700   if (HasAVX512DQ)
 701     Builder.defineMacro("__AVX512DQ__");
 702   if (HasAVX512BITALG)
 703     Builder.defineMacro("__AVX512BITALG__");
 704   if (HasAVX512BW)
 705     Builder.defineMacro("__AVX512BW__");
 706   if (HasAVX512VL)
 707     Builder.defineMacro("__AVX512VL__");
 708   if (HasAVX512VBMI)
 709     Builder.defineMacro("__AVX512VBMI__");
 710   if (HasAVX512VBMI2)
 711     Builder.defineMacro("__AVX512VBMI2__");
 712   if (HasAVX512IFMA)
 713     Builder.defineMacro("__AVX512IFMA__");
 714   if (HasAVX512VP2INTERSECT)
 715     Builder.defineMacro("__AVX512VP2INTERSECT__");
 716   if (HasSHA)
 717     Builder.defineMacro("__SHA__");
 718
 719   if (HasFXSR)
 720     Builder.defineMacro("__FXSR__");
 721   if (HasXSAVE)
 722     Builder.defineMacro("__XSAVE__");
 723   if (HasXSAVEOPT)
 724     Builder.defineMacro("__XSAVEOPT__");
 725   if (HasXSAVEC)
 726     Builder.defineMacro("__XSAVEC__");
 727   if (HasXSAVES)
 728     Builder.defineMacro("__XSAVES__");
 729   if (HasPKU)
 730     Builder.defineMacro("__PKU__");
 731   if (HasCLFLUSHOPT)
 732     Builder.defineMacro("__CLFLUSHOPT__");
 733   if (HasCLWB)
 734     Builder.defineMacro("__CLWB__");
 735   if (HasWBNOINVD)
 736     Builder.defineMacro("__WBNOINVD__");
 737   if (HasSHSTK)
 738     Builder.defineMacro("__SHSTK__");
 739   if (HasSGX)
 740     Builder.defineMacro("__SGX__");
 741   if (HasPREFETCHWT1)
 742     Builder.defineMacro("__PREFETCHWT1__");
 743   if (HasCLZERO)
 744     Builder.defineMacro("__CLZERO__");
 745   if (HasKL)
 746     Builder.defineMacro("__KL__");
 747   if (HasWIDEKL)
 748     Builder.defineMacro("__WIDEKL__");
 749   if (HasRDPID)
 750     Builder.defineMacro("__RDPID__");
 751   if (HasRDPRU)
 752     Builder.defineMacro("__RDPRU__");
 753   if (HasCLDEMOTE)
 754     Builder.defineMacro("__CLDEMOTE__");
 755   if (HasWAITPKG)
 756     Builder.defineMacro("__WAITPKG__");
 757   if (HasMOVDIRI)
 758     Builder.defineMacro("__MOVDIRI__");
 759   if (HasMOVDIR64B)
 760     Builder.defineMacro("__MOVDIR64B__");
 761   if (HasPCONFIG)
 762     Builder.defineMacro("__PCONFIG__");
 763   if (HasPTWRITE)
 764     Builder.defineMacro("__PTWRITE__");
 765   if (HasINVPCID)
 766     Builder.defineMacro("__INVPCID__");
 767   if (HasENQCMD)
 768     Builder.defineMacro("__ENQCMD__");
 769   if (HasHRESET)
 770     Builder.defineMacro("__HRESET__");
 771   if (HasAMXTILE)
 772     Builder.defineMacro("__AMXTILE__");
 773   if (HasAMXINT8)
 774     Builder.defineMacro("__AMXINT8__");
 775   if (HasAMXBF16)
 776     Builder.defineMacro("__AMXBF16__");
 777   if (HasAVXVNNI)
 778     Builder.defineMacro("__AVXVNNI__");
 779   if (HasSERIALIZE)
 780     Builder.defineMacro("__SERIALIZE__");
 781   if (HasTSXLDTRK)
 782     Builder.defineMacro("__TSXLDTRK__");
 783   if (HasUINTR)
 784     Builder.defineMacro("__UINTR__");
 785   if (HasCRC32)
 786     Builder.defineMacro("__CRC32__");
 787
 788   // Each case falls through to the previous one here.
 789   switch (SSELevel) {
 790   case AVX512F:
 791     Builder.defineMacro("__AVX512F__");
 792     [[fallthrough]];
 793   case AVX2:
 794     Builder.defineMacro("__AVX2__");
 795     [[fallthrough]];
 796   case AVX:
 797     Builder.defineMacro("__AVX__");
 798     [[fallthrough]];
 799   case SSE42:
 800     Builder.defineMacro("__SSE4_2__");
 801     [[fallthrough]];
 802   case SSE41:
 803     Builder.defineMacro("__SSE4_1__");
 804     [[fallthrough]];
 805   case SSSE3:
 806     Builder.defineMacro("__SSSE3__");
 807     [[fallthrough]];
 808   case SSE3:
 809     Builder.defineMacro("__SSE3__");
 810     [[fallthrough]];
 811   case SSE2:
 812     Builder.defineMacro("__SSE2__");
 813     Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
 814     [[fallthrough]];
 815   case SSE1:
 816     Builder.defineMacro("__SSE__");
 817     Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
 818     [[fallthrough]];
 819   case NoSSE:
 820     break;
 821   }
 822
 823   if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
 824     switch (SSELevel) {
 825     case AVX512F:
 826     case AVX2:
 827     case AVX:
 828     case SSE42:
 829     case SSE41:
 830     case SSSE3:
 831     case SSE3:
 832     case SSE2:
 833       Builder.defineMacro("_M_IX86_FP", Twine(2));
 834       break;
 835     case SSE1:
 836       Builder.defineMacro("_M_IX86_FP", Twine(1));
 837       break;
 838     default:
 839       Builder.defineMacro("_M_IX86_FP", Twine(0));
 840       break;
 841     }
 842   }
 843
 844   // Each case falls through to the previous one here.
 845   switch (MMX3DNowLevel) {
 846   case AMD3DNowAthlon:
 847     Builder.defineMacro("__3dNOW_A__");
 848     [[fallthrough]];
 849   case AMD3DNow:
 850     Builder.defineMacro("__3dNOW__");
 851     [[fallthrough]];
 852   case MMX:
 853     Builder.defineMacro("__MMX__");
 854     [[fallthrough]];
 855   case NoMMX3DNow:
 856     break;
 857   }
 858
 859   if (CPU >= CK_i486 || CPU == CK_None) {
 860     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
 861     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
 862     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
 863   }
 864   if (HasCX8)
 865     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
 866   if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64)
 867     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
 868
 869   if (HasFloat128)
 870     Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
 871 }
 872
 873 bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
 874   return llvm::StringSwitch<bool>(Name)
 875       .Case("3dnow", true)
 876       .Case("3dnowa", true)
 877       .Case("adx", true)
 878       .Case("aes", true)
 879       .Case("amx-bf16", true)
 880       .Case("amx-int8", true)
 881       .Case("amx-tile", true)
 882       .Case("avx", true)
 883       .Case("avx2", true)
 884       .Case("avx512f", true)
 885       .Case("avx512cd", true)
 886       .Case("avx512vpopcntdq", true)
 887       .Case("avx512vnni", true)
 888       .Case("avx512bf16", true)
 889       .Case("avx512er", true)
 890       .Case("avx512fp16", true)
 891       .Case("avx512pf", true)
 892       .Case("avx512dq", true)
 893       .Case("avx512bitalg", true)
 894       .Case("avx512bw", true)
 895       .Case("avx512vl", true)
 896       .Case("avx512vbmi", true)
 897       .Case("avx512vbmi2", true)
 898       .Case("avx512ifma", true)
 899       .Case("avx512vp2intersect", true)
 900       .Case("avxvnni", true)
 901       .Case("bmi", true)
 902       .Case("bmi2", true)
 903       .Case("cldemote", true)
 904       .Case("clflushopt", true)
 905       .Case("clwb", true)
 906       .Case("clzero", true)
 907       .Case("crc32", true)
 908       .Case("cx16", true)
 909       .Case("enqcmd", true)
 910       .Case("f16c", true)
 911       .Case("fma", true)
 912       .Case("fma4", true)
 913       .Case("fsgsbase", true)
 914       .Case("fxsr", true)
 915       .Case("general-regs-only", true)
 916       .Case("gfni", true)
 917       .Case("hreset", true)
 918       .Case("invpcid", true)
 919       .Case("kl", true)
 920       .Case("widekl", true)
 921       .Case("lwp", true)
 922       .Case("lzcnt", true)
 923       .Case("mmx", true)
 924       .Case("movbe", true)
 925       .Case("movdiri", true)
 926       .Case("movdir64b", true)
 927       .Case("mwaitx", true)
 928       .Case("pclmul", true)
 929       .Case("pconfig", true)
 930       .Case("pku", true)
 931       .Case("popcnt", true)
 932       .Case("prefetchwt1", true)
 933       .Case("prfchw", true)
 934       .Case("ptwrite", true)
 935       .Case("rdpid", true)
 936       .Case("rdpru", true)
 937       .Case("rdrnd", true)
 938       .Case("rdseed", true)
 939       .Case("rtm", true)
 940       .Case("sahf", true)
 941       .Case("serialize", true)
 942       .Case("sgx", true)
 943       .Case("sha", true)
 944       .Case("shstk", true)
 945       .Case("sse", true)
 946       .Case("sse2", true)
 947       .Case("sse3", true)
 948       .Case("ssse3", true)
 949       .Case("sse4", true)
 950       .Case("sse4.1", true)
 951       .Case("sse4.2", true)
 952       .Case("sse4a", true)
 953       .Case("tbm", true)
 954       .Case("tsxldtrk", true)
 955       .Case("uintr", true)
 956       .Case("vaes", true)
 957       .Case("vpclmulqdq", true)
 958       .Case("wbnoinvd", true)
 959       .Case("waitpkg", true)
 960       .Case("x87", true)
 961       .Case("xop", true)
 962       .Case("xsave", true)
 963       .Case("xsavec", true)
 964       .Case("xsaves", true)
 965       .Case("xsaveopt", true)
 966       .Default(false);
 967 }
 968
 969 bool X86TargetInfo::hasFeature(StringRef Feature) const {
 970   return llvm::StringSwitch<bool>(Feature)
 971       .Case("adx", HasADX)
 972       .Case("aes", HasAES)
 973       .Case("amx-bf16", HasAMXBF16)
 974       .Case("amx-int8", HasAMXINT8)
 975       .Case("amx-tile", HasAMXTILE)
 976       .Case("avxvnni", HasAVXVNNI)
 977       .Case("avx", SSELevel >= AVX)
 978       .Case("avx2", SSELevel >= AVX2)
 979       .Case("avx512f", SSELevel >= AVX512F)
 980       .Case("avx512cd", HasAVX512CD)
 981       .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
 982       .Case("avx512vnni", HasAVX512VNNI)
 983       .Case("avx512bf16", HasAVX512BF16)
 984       .Case("avx512er", HasAVX512ER)
 985       .Case("avx512fp16", HasAVX512FP16)
 986       .Case("avx512pf", HasAVX512PF)
 987       .Case("avx512dq", HasAVX512DQ)
 988       .Case("avx512bitalg", HasAVX512BITALG)
 989       .Case("avx512bw", HasAVX512BW)
 990       .Case("avx512vl", HasAVX512VL)
 991       .Case("avx512vbmi", HasAVX512VBMI)
 992       .Case("avx512vbmi2", HasAVX512VBMI2)
 993       .Case("avx512ifma", HasAVX512IFMA)
 994       .Case("avx512vp2intersect", HasAVX512VP2INTERSECT)
 995       .Case("bmi", HasBMI)
 996       .Case("bmi2", HasBMI2)
 997       .Case("cldemote", HasCLDEMOTE)
 998       .Case("clflushopt", HasCLFLUSHOPT)
 999       .Case("clwb", HasCLWB)
1000       .Case("clzero", HasCLZERO)
1001       .Case("crc32", HasCRC32)
1002       .Case("cx8", HasCX8)
1003       .Case("cx16", HasCX16)
1004       .Case("enqcmd", HasENQCMD)
1005       .Case("f16c", HasF16C)
1006       .Case("fma", HasFMA)
1007       .Case("fma4", XOPLevel >= FMA4)
1008       .Case("fsgsbase", HasFSGSBASE)
1009       .Case("fxsr", HasFXSR)
1010       .Case("gfni", HasGFNI)
1011       .Case("hreset", HasHRESET)
1012       .Case("invpcid", HasINVPCID)
1013       .Case("kl", HasKL)
1014       .Case("widekl", HasWIDEKL)
1015       .Case("lwp", HasLWP)
1016       .Case("lzcnt", HasLZCNT)
1017       .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
1018       .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
1019       .Case("mmx", MMX3DNowLevel >= MMX)
1020       .Case("movbe", HasMOVBE)
1021       .Case("movdiri", HasMOVDIRI)
1022       .Case("movdir64b", HasMOVDIR64B)
1023       .Case("mwaitx", HasMWAITX)
1024       .Case("pclmul", HasPCLMUL)
1025       .Case("pconfig", HasPCONFIG)
1026       .Case("pku", HasPKU)
1027       .Case("popcnt", HasPOPCNT)
1028       .Case("prefetchwt1", HasPREFETCHWT1)
1029       .Case("prfchw", HasPRFCHW)
1030       .Case("ptwrite", HasPTWRITE)
1031       .Case("rdpid", HasRDPID)
1032       .Case("rdpru", HasRDPRU)
1033       .Case("rdrnd", HasRDRND)
1034       .Case("rdseed", HasRDSEED)
1035       .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1036       .Case("rtm", HasRTM)
1037       .Case("sahf", HasLAHFSAHF)
1038       .Case("serialize", HasSERIALIZE)
1039       .Case("sgx", HasSGX)
1040       .Case("sha", HasSHA)
1041       .Case("shstk", HasSHSTK)
1042       .Case("sse", SSELevel >= SSE1)
1043       .Case("sse2", SSELevel >= SSE2)
1044       .Case("sse3", SSELevel >= SSE3)
1045       .Case("ssse3", SSELevel >= SSSE3)
1046       .Case("sse4.1", SSELevel >= SSE41)
1047       .Case("sse4.2", SSELevel >= SSE42)
1048       .Case("sse4a", XOPLevel >= SSE4A)
1049       .Case("tbm", HasTBM)
1050       .Case("tsxldtrk", HasTSXLDTRK)
1051       .Case("uintr", HasUINTR)
1052       .Case("vaes", HasVAES)
1053       .Case("vpclmulqdq", HasVPCLMULQDQ)
1054       .Case("wbnoinvd", HasWBNOINVD)
1055       .Case("waitpkg", HasWAITPKG)
1056       .Case("x86", true)
1057       .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1058       .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1059       .Case("x87", HasX87)
1060       .Case("xop", XOPLevel >= XOP)
1061       .Case("xsave", HasXSAVE)
1062       .Case("xsavec", HasXSAVEC)
1063       .Case("xsaves", HasXSAVES)
1064       .Case("xsaveopt", HasXSAVEOPT)
1065       .Default(false);
1066 }
1067
1068 // We can't use a generic validation scheme for the features accepted here
1069 // versus subtarget features accepted in the target attribute because the
1070 // bitfield structure that's initialized in the runtime only supports the
1071 // below currently rather than the full range of subtarget features. (See
1072 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
1073 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1074   return llvm::StringSwitch<bool>(FeatureStr)
1075 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) .Case(STR, true)
1076 #include "llvm/Support/X86TargetParser.def"
1077       .Default(false);
1078 }
1079
1080 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1081   return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1082 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY)                                \
1083   .Case(STR, llvm::X86::FEATURE_##ENUM)
1084
1085 #include "llvm/Support/X86TargetParser.def"
1086       ;
1087   // Note, this function should only be used after ensuring the value is
1088   // correct, so it asserts if the value is out of range.
1089 }
1090
1091 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const {
1092   // Valid CPUs have a 'key feature' that compares just better than its key
1093   // feature.
1094   using namespace llvm::X86;
1095   CPUKind Kind = parseArchX86(Name);
1096   if (Kind != CK_None) {
1097     ProcessorFeatures KeyFeature = getKeyFeature(Kind);
1098     return (getFeaturePriority(KeyFeature) << 1) + 1;
1099   }
1100
1101   // Now we know we have a feature, so get its priority and shift it a few so
1102   // that we have sufficient room for the CPUs (above).
1103   return getFeaturePriority(getFeature(Name)) << 1;
1104 }
1105
1106 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const {
1107   return llvm::StringSwitch<bool>(Name)
1108 #define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, true)
1109 #define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, true)
1110 #include "llvm/Support/X86TargetParser.def"
1111       .Default(false);
1112 }
1113
1114 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) {
1115   return llvm::StringSwitch<StringRef>(Name)
1116 #define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, NAME)
1117 #include "llvm/Support/X86TargetParser.def"
1118       .Default(Name);
1119 }
1120
1121 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const {
1122   return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name))
1123 #define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, MANGLING)
1124 #include "llvm/Support/X86TargetParser.def"
1125       .Default(0);
1126 }
1127
1128 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures(
1129     StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1130   StringRef WholeList =
1131       llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name))
1132 #define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, FEATURES)
1133 #include "llvm/Support/X86TargetParser.def"
1134           .Default("");
1135   WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false);
1136 }
1137
1138 StringRef X86TargetInfo::getCPUSpecificTuneName(StringRef Name) const {
1139   return llvm::StringSwitch<StringRef>(Name)
1140 #define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, TUNE_NAME)
1141 #define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, TUNE_NAME)
1142 #include "llvm/Support/X86TargetParser.def"
1143       .Default("");
1144 }
1145
1146 // We can't use a generic validation scheme for the cpus accepted here
1147 // versus subtarget cpus accepted in the target attribute because the
1148 // variables intitialized by the runtime only support the below currently
1149 // rather than the full range of cpus.
1150 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1151   return llvm::StringSwitch<bool>(FeatureStr)
1152 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1153 #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1154 #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true)
1155 #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true)
1156 #include "llvm/Support/X86TargetParser.def"
1157       .Default(false);
1158 }
1159
1160 static unsigned matchAsmCCConstraint(const char *&Name) {
1161   auto RV = llvm::StringSwitch<unsigned>(Name)
1162                 .Case("@cca", 4)
1163                 .Case("@ccae", 5)
1164                 .Case("@ccb", 4)
1165                 .Case("@ccbe", 5)
1166                 .Case("@ccc", 4)
1167                 .Case("@cce", 4)
1168                 .Case("@ccz", 4)
1169                 .Case("@ccg", 4)
1170                 .Case("@ccge", 5)
1171                 .Case("@ccl", 4)
1172                 .Case("@ccle", 5)
1173                 .Case("@ccna", 5)
1174                 .Case("@ccnae", 6)
1175                 .Case("@ccnb", 5)
1176                 .Case("@ccnbe", 6)
1177                 .Case("@ccnc", 5)
1178                 .Case("@ccne", 5)
1179                 .Case("@ccnz", 5)
1180                 .Case("@ccng", 5)
1181                 .Case("@ccnge", 6)
1182                 .Case("@ccnl", 5)
1183                 .Case("@ccnle", 6)
1184                 .Case("@ccno", 5)
1185                 .Case("@ccnp", 5)
1186                 .Case("@ccns", 5)
1187                 .Case("@cco", 4)
1188                 .Case("@ccp", 4)
1189                 .Case("@ccs", 4)
1190                 .Default(0);
1191   return RV;
1192 }
1193
1194 bool X86TargetInfo::validateAsmConstraint(
1195     const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1196   switch (*Name) {
1197   default:
1198     return false;
1199   // Constant constraints.
1200   case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1201             // instructions.
1202   case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1203             // x86_64 instructions.
1204   case 's':
1205     Info.setRequiresImmediate();
1206     return true;
1207   case 'I':
1208     Info.setRequiresImmediate(0, 31);
1209     return true;
1210   case 'J':
1211     Info.setRequiresImmediate(0, 63);
1212     return true;
1213   case 'K':
1214     Info.setRequiresImmediate(-128, 127);
1215     return true;
1216   case 'L':
1217     Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1218     return true;
1219   case 'M':
1220     Info.setRequiresImmediate(0, 3);
1221     return true;
1222   case 'N':
1223     Info.setRequiresImmediate(0, 255);
1224     return true;
1225   case 'O':
1226     Info.setRequiresImmediate(0, 127);
1227     return true;
1228   // Register constraints.
1229   case 'Y': // 'Y' is the first character for several 2-character constraints.
1230     // Shift the pointer to the second character of the constraint.
1231     Name++;
1232     switch (*Name) {
1233     default:
1234       return false;
1235     case 'z': // First SSE register.
1236     case '2':
1237     case 't': // Any SSE register, when SSE2 is enabled.
1238     case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1239     case 'm': // Any MMX register, when inter-unit moves enabled.
1240     case 'k': // AVX512 arch mask registers: k1-k7.
1241       Info.setAllowsRegister();
1242       return true;
1243     }
1244   case 'f': // Any x87 floating point stack register.
1245     // Constraint 'f' cannot be used for output operands.
1246     if (Info.ConstraintStr[0] == '=')
1247       return false;
1248     Info.setAllowsRegister();
1249     return true;
1250   case 'a': // eax.
1251   case 'b': // ebx.
1252   case 'c': // ecx.
1253   case 'd': // edx.
1254   case 'S': // esi.
1255   case 'D': // edi.
1256   case 'A': // edx:eax.
1257   case 't': // Top of floating point stack.
1258   case 'u': // Second from top of floating point stack.
1259   case 'q': // Any register accessible as [r]l: a, b, c, and d.
1260   case 'y': // Any MMX register.
1261   case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1262   case 'x': // Any SSE register.
1263   case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1264             // for intermideate k reg operations).
1265   case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1266   case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1267   case 'l': // "Index" registers: any general register that can be used as an
1268             // index in a base+index memory access.
1269     Info.setAllowsRegister();
1270     return true;
1271   // Floating point constant constraints.
1272   case 'C': // SSE floating point constant.
1273   case 'G': // x87 floating point constant.
1274     return true;
1275   case '@':
1276     // CC condition changes.
1277     if (auto Len = matchAsmCCConstraint(Name)) {
1278       Name += Len - 1;
1279       Info.setAllowsRegister();
1280       return true;
1281     }
1282     return false;
1283   }
1284 }
1285
1286 // Below is based on the following information:
1287 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1288 // |           Processor Name           | Cache Line Size (Bytes) |                                                                            Source                                                                            |
1289 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1290 // | i386                               |                      64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf                                          |
1291 // | i486                               |                      16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) |
1292 // | i586/Pentium MMX                   |                      32 | https://www.7-cpu.com/cpu/P-MMX.html                                                                                                                         |
1293 // | i686/Pentium                       |                      32 | https://www.7-cpu.com/cpu/P6.html                                                                                                                            |
1294 // | Netburst/Pentium4                  |                      64 | https://www.7-cpu.com/cpu/P4-180.html                                                                                                                        |
1295 // | Atom                               |                      64 | https://www.7-cpu.com/cpu/Atom.html                                                                                                                          |
1296 // | Westmere                           |                      64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture"                                                             |
1297 // | Sandy Bridge                       |                      64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html                                                                    |
1298 // | Ivy Bridge                         |                      64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html                                                      |
1299 // | Haswell                            |                      64 | https://www.7-cpu.com/cpu/Haswell.html                                                                                                                       |
1300 // | Boadwell                           |                      64 | https://www.7-cpu.com/cpu/Broadwell.html                                                                                                                     |
1301 // | Skylake (including skylake-avx512) |                      64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy"                                                                       |
1302 // | Cascade Lake                       |                      64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy"                                                                  |
1303 // | Skylake                            |                      64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy"                                                                           |
1304 // | Ice Lake                           |                      64 | https://www.7-cpu.com/cpu/Ice_Lake.html                                                                                                                      |
1305 // | Knights Landing                    |                      64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" |
1306 // | Knights Mill                       |                      64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache "       |
1307 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1308 Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
1309   using namespace llvm::X86;
1310   switch (CPU) {
1311     // i386
1312     case CK_i386:
1313     // i486
1314     case CK_i486:
1315     case CK_WinChipC6:
1316     case CK_WinChip2:
1317     case CK_C3:
1318     // Lakemont
1319     case CK_Lakemont:
1320       return 16;
1321
1322     // i586
1323     case CK_i586:
1324     case CK_Pentium:
1325     case CK_PentiumMMX:
1326     // i686
1327     case CK_PentiumPro:
1328     case CK_i686:
1329     case CK_Pentium2:
1330     case CK_Pentium3:
1331     case CK_PentiumM:
1332     case CK_C3_2:
1333     // K6
1334     case CK_K6:
1335     case CK_K6_2:
1336     case CK_K6_3:
1337     // Geode
1338     case CK_Geode:
1339       return 32;
1340
1341     // Netburst
1342     case CK_Pentium4:
1343     case CK_Prescott:
1344     case CK_Nocona:
1345     // Atom
1346     case CK_Bonnell:
1347     case CK_Silvermont:
1348     case CK_Goldmont:
1349     case CK_GoldmontPlus:
1350     case CK_Tremont:
1351
1352     case CK_Westmere:
1353     case CK_SandyBridge:
1354     case CK_IvyBridge:
1355     case CK_Haswell:
1356     case CK_Broadwell:
1357     case CK_SkylakeClient:
1358     case CK_SkylakeServer:
1359     case CK_Cascadelake:
1360     case CK_Nehalem:
1361     case CK_Cooperlake:
1362     case CK_Cannonlake:
1363     case CK_Tigerlake:
1364     case CK_SapphireRapids:
1365     case CK_IcelakeClient:
1366     case CK_Rocketlake:
1367     case CK_IcelakeServer:
1368     case CK_Alderlake:
1369     case CK_KNL:
1370     case CK_KNM:
1371     // K7
1372     case CK_Athlon:
1373     case CK_AthlonXP:
1374     // K8
1375     case CK_K8:
1376     case CK_K8SSE3:
1377     case CK_AMDFAM10:
1378     // Bobcat
1379     case CK_BTVER1:
1380     case CK_BTVER2:
1381     // Bulldozer
1382     case CK_BDVER1:
1383     case CK_BDVER2:
1384     case CK_BDVER3:
1385     case CK_BDVER4:
1386     // Zen
1387     case CK_ZNVER1:
1388     case CK_ZNVER2:
1389     case CK_ZNVER3:
1390     // Deprecated
1391     case CK_x86_64:
1392     case CK_x86_64_v2:
1393     case CK_x86_64_v3:
1394     case CK_x86_64_v4:
1395     case CK_Yonah:
1396     case CK_Penryn:
1397     case CK_Core2:
1398       return 64;
1399
1400     // The following currently have unknown cache line sizes (but they are probably all 64):
1401     // Core
1402     case CK_None:
1403       return None;
1404   }
1405   llvm_unreachable("Unknown CPU kind");
1406 }
1407
1408 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
1409                                        StringRef Constraint,
1410                                        unsigned Size) const {
1411   // Strip off constraint modifiers.
1412   while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
1413     Constraint = Constraint.substr(1);
1414
1415   return validateOperandSize(FeatureMap, Constraint, Size);
1416 }
1417
1418 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap,
1419                                       StringRef Constraint,
1420                                       unsigned Size) const {
1421   return validateOperandSize(FeatureMap, Constraint, Size);
1422 }
1423
1424 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
1425                                         StringRef Constraint,
1426                                         unsigned Size) const {
1427   switch (Constraint[0]) {
1428   default:
1429     break;
1430   case 'k':
1431   // Registers k0-k7 (AVX512) size limit is 64 bit.
1432   case 'y':
1433     return Size <= 64;
1434   case 'f':
1435   case 't':
1436   case 'u':
1437     return Size <= 128;
1438   case 'Y':
1439     // 'Y' is the first character for several 2-character constraints.
1440     switch (Constraint[1]) {
1441     default:
1442       return false;
1443     case 'm':
1444       // 'Ym' is synonymous with 'y'.
1445     case 'k':
1446       return Size <= 64;
1447     case 'z':
1448       // XMM0/YMM/ZMM0
1449       if (hasFeatureEnabled(FeatureMap, "avx512f"))
1450         // ZMM0 can be used if target supports AVX512F.
1451         return Size <= 512U;
1452       else if (hasFeatureEnabled(FeatureMap, "avx"))
1453         // YMM0 can be used if target supports AVX.
1454         return Size <= 256U;
1455       else if (hasFeatureEnabled(FeatureMap, "sse"))
1456         return Size <= 128U;
1457       return false;
1458     case 'i':
1459     case 't':
1460     case '2':
1461       // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1462       if (SSELevel < SSE2)
1463         return false;
1464       break;
1465     }
1466     break;
1467   case 'v':
1468   case 'x':
1469     if (hasFeatureEnabled(FeatureMap, "avx512f"))
1470       // 512-bit zmm registers can be used if target supports AVX512F.
1471       return Size <= 512U;
1472     else if (hasFeatureEnabled(FeatureMap, "avx"))
1473       // 256-bit ymm registers can be used if target supports AVX.
1474       return Size <= 256U;
1475     return Size <= 128U;
1476
1477   }
1478
1479   return true;
1480 }
1481
1482 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1483   switch (*Constraint) {
1484   case '@':
1485     if (auto Len = matchAsmCCConstraint(Constraint)) {
1486       std::string Converted = "{" + std::string(Constraint, Len) + "}";
1487       Constraint += Len - 1;
1488       return Converted;
1489     }
1490     return std::string(1, *Constraint);
1491   case 'a':
1492     return std::string("{ax}");
1493   case 'b':
1494     return std::string("{bx}");
1495   case 'c':
1496     return std::string("{cx}");
1497   case 'd':
1498     return std::string("{dx}");
1499   case 'S':
1500     return std::string("{si}");
1501   case 'D':
1502     return std::string("{di}");
1503   case 'p': // Keep 'p' constraint (address).
1504     return std::string("p");
1505   case 't': // top of floating point stack.
1506     return std::string("{st}");
1507   case 'u':                        // second from top of floating point stack.
1508     return std::string("{st(1)}"); // second from top of floating point stack.
1509   case 'Y':
1510     switch (Constraint[1]) {
1511     default:
1512       // Break from inner switch and fall through (copy single char),
1513       // continue parsing after copying the current constraint into
1514       // the return string.
1515       break;
1516     case 'k':
1517     case 'm':
1518     case 'i':
1519     case 't':
1520     case 'z':
1521     case '2':
1522       // "^" hints llvm that this is a 2 letter constraint.
1523       // "Constraint++" is used to promote the string iterator
1524       // to the next constraint.
1525       return std::string("^") + std::string(Constraint++, 2);
1526     }
1527     [[fallthrough]];
1528   default:
1529     return std::string(1, *Constraint);
1530   }
1531 }
1532
1533 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
1534   bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
1535   llvm::X86::fillValidCPUArchList(Values, Only64Bit);
1536 }
1537
1538 void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const {
1539   llvm::X86::fillValidTuneCPUList(Values);
1540 }
1541
1542 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const {
1543   return llvm::makeArrayRef(GCCRegNames);
1544 }
1545
1546 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const {
1547   return llvm::makeArrayRef(AddlRegNames);
1548 }
1549
1550 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const {
1551   return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
1552                                                 Builtin::FirstTSBuiltin + 1);
1553 }
1554
1555 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const {
1556   return llvm::makeArrayRef(BuiltinInfoX86,
1557                             X86::LastTSBuiltin - Builtin::FirstTSBuiltin);
1558 }