llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp

   1 //===- KnownBitsTest.cpp -------------------------------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 #include "GISelMITest.h"
  10 #include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
  11 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
  12
  13 TEST_F(AArch64GISelMITest, TestKnownBitsBuildVector) {
  14   StringRef MIRString = R"(
  15    %ptr:_(p0) = G_IMPLICIT_DEF
  16    %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
  17    %mask0:_(s8) = G_CONSTANT i8 24
  18    %mask1:_(s8) = G_CONSTANT i8 224
  19    %tmp0:_(s8) = G_AND %unknown, %mask0
  20    %val0:_(s8) = G_OR %tmp0, %mask1
  21    %mask2:_(s8) = G_CONSTANT i8 146
  22    %mask3:_(s8) = G_CONSTANT i8 36
  23    %tmp1:_(s8) = G_AND %unknown, %mask2
  24    %val1:_(s8) = G_OR %tmp1, %mask3
  25    %vector:_(<2 x s8>) = G_BUILD_VECTOR %val0, %val1
  26    %copy_vector:_(<2 x s8>) = COPY %vector
  27 )";
  28
  29   setUp(MIRString);
  30   if (!TM)
  31     return;
  32
  33   Register CopyReg = Copies[Copies.size() - 1];
  34   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
  35   Register SrcReg = FinalCopy->getOperand(1).getReg();
  36   GISelKnownBits Info(*MF);
  37   KnownBits Res = Info.getKnownBits(SrcReg);
  38   // BuildVector KnownBits takes common bits of all elements.
  39   //        111??000
  40   // common ?01?01?0
  41   //      = ??1????0
  42   EXPECT_EQ(0x20u, Res.One.getZExtValue());
  43   EXPECT_EQ(0x01u, Res.Zero.getZExtValue());
  44 }
  45
  46 // Vector KnownBits track bits that are common for all vector scalar elements.
  47 // For tests below KnownBits analysis is same as for scalar/pointer types, tests
  48 // are mostly copied from KnownBitsTest.cpp using splat vectors and have the
  49 // same result.
  50
  51 TEST_F(AArch64GISelMITest, TestKnownBitsVectorCstPHI) {
  52   StringRef MIRString = R"(
  53    bb.10:
  54    %10:_(s8) = G_CONSTANT i8 3
  55    %11:_(<2 x s8>) = G_BUILD_VECTOR %10:_(s8), %10:_(s8)
  56    %12:_(s1) = G_IMPLICIT_DEF
  57    G_BRCOND %12(s1), %bb.11
  58    G_BR %bb.12
  59
  60    bb.11:
  61    %13:_(s8) = G_CONSTANT i8 2
  62    %14:_(<2 x s8>) = G_BUILD_VECTOR %13:_(s8), %13:_(s8)
  63    G_BR %bb.12
  64
  65    bb.12:
  66    %15:_(<2 x s8>) = PHI %11(<2 x s8>), %bb.10, %14(<2 x s8>), %bb.11
  67    %16:_(<2 x s8>) = COPY %15
  68 )";
  69
  70   setUp(MIRString);
  71   if (!TM)
  72     return;
  73
  74   Register CopyReg = Copies[Copies.size() - 1];
  75   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
  76   Register SrcReg = FinalCopy->getOperand(1).getReg();
  77   Register DstReg = FinalCopy->getOperand(0).getReg();
  78   GISelKnownBits Info(*MF);
  79   KnownBits Res = Info.getKnownBits(SrcReg);
  80   EXPECT_EQ((uint64_t)2, Res.One.getZExtValue());
  81   EXPECT_EQ((uint64_t)0xfc, Res.Zero.getZExtValue());
  82
  83   KnownBits Res2 = Info.getKnownBits(DstReg);
  84   EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
  85   EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
  86 }
  87
  88 TEST_F(AArch64GISelMITest, TestKnownBitsVectorCstPHIToNonGenericReg) {
  89   StringRef MIRString = R"(
  90    bb.10:
  91    %10:gpr32 = MOVi32imm 771
  92    %11:_(s1) = G_IMPLICIT_DEF
  93    G_BRCOND %11(s1), %bb.11
  94    G_BR %bb.12
  95
  96    bb.11:
  97    %12:_(s16) = G_CONSTANT i16 2
  98    %13:_(<2 x s16>) = G_BUILD_VECTOR %12:_(s16), %12:_(s16)
  99    G_BR %bb.12
 100
 101    bb.12:
 102    %15:_(<2 x s16>) = PHI %10, %bb.10, %13(<2 x s16>), %bb.11
 103    %16:_(<2 x s16>) = COPY %15
 104 )";
 105
 106   setUp(MIRString);
 107   if (!TM)
 108     return;
 109
 110   Register CopyReg = Copies[Copies.size() - 1];
 111   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
 112   Register SrcReg = FinalCopy->getOperand(1).getReg();
 113   Register DstReg = FinalCopy->getOperand(0).getReg();
 114   GISelKnownBits Info(*MF);
 115   KnownBits Res = Info.getKnownBits(SrcReg);
 116   EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
 117   EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue());
 118
 119   KnownBits Res2 = Info.getKnownBits(DstReg);
 120   EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
 121   EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
 122 }
 123
 124 TEST_F(AArch64GISelMITest, TestKnownBitsVectorUnknownPHI) {
 125   StringRef MIRString = R"(
 126    bb.10:
 127    %10:_(<2 x s32>) = G_BITCAST %0
 128    %11:_(s1) = G_IMPLICIT_DEF
 129    G_BRCOND %11(s1), %bb.11
 130    G_BR %bb.12
 131
 132    bb.11:
 133    %12:_(s32) = G_CONSTANT i32 2
 134    %13:_(<2 x s32>) = G_BUILD_VECTOR %12:_(s32), %12:_(s32)
 135    G_BR %bb.12
 136
 137    bb.12:
 138    %14:_(<2 x s32>) = PHI %10(<2 x s32>), %bb.10, %13(<2 x s32>), %bb.11
 139    %15:_(<2 x s32>) = COPY %14
 140 )";
 141
 142   setUp(MIRString);
 143   if (!TM)
 144     return;
 145
 146   Register CopyReg = Copies[Copies.size() - 1];
 147   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
 148   Register SrcReg = FinalCopy->getOperand(1).getReg();
 149   Register DstReg = FinalCopy->getOperand(0).getReg();
 150   GISelKnownBits Info(*MF);
 151   KnownBits Res = Info.getKnownBits(SrcReg);
 152   EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
 153   EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue());
 154
 155   KnownBits Res2 = Info.getKnownBits(DstReg);
 156   EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
 157   EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
 158 }
 159
 160 TEST_F(AArch64GISelMITest, TestKnownBitsVectorCstPHIWithLoop) {
 161   StringRef MIRString = R"(
 162    bb.10:
 163    %10:_(s8) = G_CONSTANT i8 3
 164    %11:_(<2 x s8>) = G_BUILD_VECTOR %10:_(s8), %10:_(s8)
 165    %12:_(s1) = G_IMPLICIT_DEF
 166    G_BRCOND %12(s1), %bb.11
 167    G_BR %bb.12
 168
 169    bb.11:
 170    %13:_(s8) = G_CONSTANT i8 2
 171    %14:_(<2 x s8>) = G_BUILD_VECTOR %13:_(s8), %13:_(s8)
 172    G_BR %bb.12
 173
 174    bb.12:
 175    %15:_(<2 x s8>) = PHI %11(<2 x s8>), %bb.10, %14(<2 x s8>), %bb.11, %16(<2 x s8>), %bb.12
 176    %16:_(<2 x s8>) = COPY %15
 177    G_BR %bb.12
 178 )";
 179
 180   setUp(MIRString);
 181   if (!TM)
 182     return;
 183
 184   Register CopyReg = Copies[Copies.size() - 1];
 185   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
 186   Register SrcReg = FinalCopy->getOperand(1).getReg();
 187   Register DstReg = FinalCopy->getOperand(0).getReg();
 188   GISelKnownBits Info(*MF);
 189   KnownBits Res = Info.getKnownBits(SrcReg);
 190   EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
 191   EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue());
 192
 193   KnownBits Res2 = Info.getKnownBits(DstReg);
 194   EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
 195   EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
 196 }
 197
 198 TEST_F(AArch64GISelMITest, TestKnownBitsVectorDecreasingCstPHIWithLoop) {
 199   StringRef MIRString = R"(
 200    bb.10:
 201    %10:_(s8) = G_CONSTANT i8 5
 202    %11:_(<2 x s8>) = G_BUILD_VECTOR %10:_(s8), %10:_(s8)
 203    %12:_(s8) = G_CONSTANT i8 1
 204    %16:_(<2 x s8>) = G_BUILD_VECTOR %12:_(s8), %12:_(s8)
 205
 206    bb.12:
 207    %13:_(<2 x s8>) = PHI %11(<2 x s8>), %bb.10, %14(<2 x s8>), %bb.12
 208    %14:_(<2 x s8>) = G_LSHR %13, %16
 209    %15:_(<2 x s8>) = COPY %14
 210    G_BR %bb.12
 211 )";
 212
 213   setUp(MIRString);
 214   if (!TM)
 215     return;
 216   Register CopyReg = Copies[Copies.size() - 1];
 217   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
 218   Register SrcReg = FinalCopy->getOperand(1).getReg();
 219   Register DstReg = FinalCopy->getOperand(0).getReg();
 220   GISelKnownBits Info(*MF, /*MaxDepth=*/24);
 221   KnownBits Res = Info.getKnownBits(SrcReg);
 222   EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
 223   EXPECT_EQ((uint64_t)0xC0, Res.Zero.getZExtValue());
 224
 225   KnownBits Res2 = Info.getKnownBits(DstReg);
 226   EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
 227   EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
 228 }
 229
 230 TEST_F(AArch64GISelMITest, TestKnownBitsVectorAND) {
 231   StringRef MIRString = R"(
 232    %ptr:_(p0) = G_IMPLICIT_DEF
 233    %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>))
 234    %mask0:_(s8) = G_CONSTANT i8 52
 235    %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0
 236    %mask1:_(s8) = G_CONSTANT i8 10
 237    %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1
 238    %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat
 239    %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat
 240    %mask2:_(s8) = G_CONSTANT i8 32
 241    %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask2
 242    %mask3:_(s8) = G_CONSTANT i8 24
 243    %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3
 244    %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat
 245    %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat
 246    %and:_(<2 x s8>) = G_AND %val0, %val1
 247    %copy_and:_(<2 x s8>) = COPY %and
 248 )";
 249
 250   setUp(MIRString);
 251   if (!TM)
 252     return;
 253
 254   Register CopyReg = Copies[Copies.size() - 1];
 255   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
 256   Register SrcReg = FinalCopy->getOperand(1).getReg();
 257   GISelKnownBits Info(*MF);
 258   KnownBits Res = Info.getKnownBits(SrcReg);
 259   EXPECT_EQ(0x08u, Res.One.getZExtValue());
 260   EXPECT_EQ(0xC7u, Res.Zero.getZExtValue());
 261 }
 262
 263 TEST_F(AArch64GISelMITest, TestKnownBitsVectorOR) {
 264   StringRef MIRString = R"(
 265    %ptr:_(p0) = G_IMPLICIT_DEF
 266    %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>))
 267    %mask0:_(s8) = G_CONSTANT i8 52
 268    %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0
 269    %mask1:_(s8) = G_CONSTANT i8 10
 270    %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1
 271    %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat
 272    %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat
 273    %mask2:_(s8) = G_CONSTANT i8 32
 274    %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask2
 275    %mask3:_(s8) = G_CONSTANT i8 24
 276    %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3
 277    %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat
 278    %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat
 279    %or:_(<2 x s8>) = G_OR %val0, %val1
 280    %copy_or:_(<2 x s8>) = COPY %or
 281 )";
 282
 283   setUp(MIRString);
 284   if (!TM)
 285     return;
 286
 287   Register CopyReg = Copies[Copies.size() - 1];
 288   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
 289   Register SrcReg = FinalCopy->getOperand(1).getReg();
 290   GISelKnownBits Info(*MF);
 291   KnownBits Res = Info.getKnownBits(SrcReg);
 292   EXPECT_EQ(0x1Au, Res.One.getZExtValue());
 293   EXPECT_EQ(0xC1u, Res.Zero.getZExtValue());
 294 }
 295
 296 TEST_F(AArch64GISelMITest, TestKnownBitsVectorXOR) {
 297   StringRef MIRString = R"(
 298    %ptr:_(p0) = G_IMPLICIT_DEF
 299    %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>))
 300    %mask0:_(s8) = G_CONSTANT i8 52
 301    %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0
 302    %mask1:_(s8) = G_CONSTANT i8 10
 303    %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1
 304    %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat
 305    %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat
 306    %mask2:_(s8) = G_CONSTANT i8 32
 307    %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask2
 308    %mask3:_(s8) = G_CONSTANT i8 24
 309    %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3
 310    %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat
 311    %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat
 312    %xor:_(<2 x s8>) = G_XOR %val0, %val1
 313    %copy_xor:_(<2 x s8>) = COPY %xor
 314 )";
 315
 316   setUp(MIRString);
 317   if (!TM)
 318     return;
 319
 320   Register CopyReg = Copies[Copies.size() - 1];
 321   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
 322   Register SrcReg = FinalCopy->getOperand(1).getReg();
 323   GISelKnownBits Info(*MF);
 324   KnownBits Res = Info.getKnownBits(SrcReg);
 325   EXPECT_EQ(0x02u, Res.One.getZExtValue());
 326   EXPECT_EQ(0xC9u, Res.Zero.getZExtValue());
 327 }
 328
 329 TEST_F(AArch64GISelMITest, TestKnownBitsVectorXORConstant) {
 330   StringRef MIRString = R"(
 331    %3:_(s8) = G_CONSTANT i8 4
 332    %4:_(<2 x s8>) = G_BUILD_VECTOR %3:_(s8), %3:_(s8)
 333    %5:_(s8) = G_CONSTANT i8 7
 334    %6:_(<2 x s8>) = G_BUILD_VECTOR %5:_(s8), %5:_(s8)
 335    %7:_(<2 x s8>) = G_XOR %4, %6
 336    %8:_(<2 x s8>) = COPY %7
 337
 338    %9:_(s8) = G_CONSTANT i8 12
 339    %10:_(<2 x s8>) = G_BUILD_VECTOR %3:_(s8), %9:_(s8)
 340    %11:_(<2 x s8>) = G_XOR %10, %6
 341    %12:_(<2 x s8>) = COPY %11
 342 )";
 343
 344   setUp(MIRString);
 345   if (!TM)
 346     return;
 347
 348   GISelKnownBits Info(*MF);
 349   Register CopySplatReg = Copies[Copies.size() - 2];
 350   MachineInstr *FinalSplatCopy = MRI->getVRegDef(CopySplatReg);
 351   Register SrcSplatReg = FinalSplatCopy->getOperand(1).getReg();
 352   KnownBits ResNonSplat = Info.getKnownBits(SrcSplatReg);
 353   EXPECT_EQ(3u, ResNonSplat.One.getZExtValue());
 354   EXPECT_EQ(252u, ResNonSplat.Zero.getZExtValue());
 355
 356   Register CopyNonSplatReg = Copies[Copies.size() - 1];
 357   MachineInstr *FinalNonSplatCopy = MRI->getVRegDef(CopyNonSplatReg);
 358   Register SrcNonSplatReg = FinalNonSplatCopy->getOperand(1).getReg();
 359   KnownBits ResSplat = Info.getKnownBits(SrcNonSplatReg);
 360   EXPECT_EQ(3u, ResSplat.One.getZExtValue());
 361   EXPECT_EQ(244u, ResSplat.Zero.getZExtValue());
 362 }
 363
 364 TEST_F(AArch64GISelMITest, TestKnownBitsVectorASHR) {
 365   StringRef MIRString = R"(
 366    %ptr:_(p0) = G_IMPLICIT_DEF
 367    %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>))
 368    %mask0:_(s8) = G_CONSTANT i8 38
 369    %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0
 370    %mask1:_(s8) = G_CONSTANT i8 202
 371    %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1
 372    %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat
 373    %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat
 374    %cst0:_(s8) = G_CONSTANT i8 2
 375    %cst0_splat:_(<2 x s8>) = G_BUILD_VECTOR %cst0, %cst0
 376    %ashr0:_(<2 x s8>) = G_ASHR %val0, %cst0_splat
 377    %copy_ashr0:_(<2 x s8>) = COPY %ashr0
 378
 379    %mask2:_(s8) = G_CONSTANT i8 204
 380    %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask2
 381    %mask3:_(s8) = G_CONSTANT i8 18
 382    %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3
 383    %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat
 384    %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat
 385    %ashr1:_(<2 x s8>) = G_ASHR %val1, %cst0_splat
 386    %copy_ashr1:_(<2 x s8>) = COPY %ashr1
 387 )";
 388
 389   setUp(MIRString);
 390   if (!TM)
 391     return;
 392
 393   Register CopyReg0 = Copies[Copies.size() - 2];
 394   MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
 395   Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
 396   GISelKnownBits Info(*MF);
 397   KnownBits Res0 = Info.getKnownBits(SrcReg0);
 398   EXPECT_EQ(0xF2u, Res0.One.getZExtValue());
 399   EXPECT_EQ(0x04u, Res0.Zero.getZExtValue());
 400
 401   Register CopyReg1 = Copies[Copies.size() - 1];
 402   MachineInstr *FinalCopy1 = MRI->getVRegDef(CopyReg1);
 403   Register SrcReg1 = FinalCopy1->getOperand(1).getReg();
 404   KnownBits Res1 = Info.getKnownBits(SrcReg1);
 405   EXPECT_EQ(0x04u, Res1.One.getZExtValue());
 406   EXPECT_EQ(0x08u, Res1.Zero.getZExtValue());
 407 }
 408
 409 TEST_F(AArch64GISelMITest, TestKnownBitsVectorLSHR) {
 410   StringRef MIRString = R"(
 411    %ptr:_(p0) = G_IMPLICIT_DEF
 412    %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>))
 413    %mask0:_(s8) = G_CONSTANT i8 38
 414    %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0
 415    %mask1:_(s8) = G_CONSTANT i8 202
 416    %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1
 417    %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat
 418    %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat
 419    %cst0:_(s8) = G_CONSTANT i8 2
 420    %cst0_splat:_(<2 x s8>) = G_BUILD_VECTOR %cst0, %cst0
 421    %lshr0:_(<2 x s8>) = G_LSHR %val0, %cst0_splat
 422    %copy_lshr0:_(<2 x s8>) = COPY %lshr0
 423
 424    %mask2:_(s8) = G_CONSTANT i8 204
 425    %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask2
 426    %mask3:_(s8) = G_CONSTANT i8 18
 427    %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3
 428    %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat
 429    %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat
 430    %lshr1:_(<2 x s8>) = G_LSHR %val1, %cst0_splat
 431    %copy_lshr1:_(<2 x s8>) = COPY %lshr1
 432 )";
 433
 434   setUp(MIRString);
 435   if (!TM)
 436     return;
 437
 438   Register CopyReg0 = Copies[Copies.size() - 2];
 439   MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
 440   Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
 441   GISelKnownBits Info(*MF);
 442   KnownBits Res0 = Info.getKnownBits(SrcReg0);
 443   EXPECT_EQ(0x32u, Res0.One.getZExtValue());
 444   EXPECT_EQ(0xC4u, Res0.Zero.getZExtValue());
 445
 446   Register CopyReg1 = Copies[Copies.size() - 1];
 447   MachineInstr *FinalCopy1 = MRI->getVRegDef(CopyReg1);
 448   Register SrcReg1 = FinalCopy1->getOperand(1).getReg();
 449   KnownBits Res1 = Info.getKnownBits(SrcReg1);
 450   EXPECT_EQ(0x04u, Res1.One.getZExtValue());
 451   EXPECT_EQ(0xC8u, Res1.Zero.getZExtValue());
 452 }
 453
 454 TEST_F(AArch64GISelMITest, TestKnownBitsVectorSHL) {
 455   StringRef MIRString = R"(
 456    %ptr:_(p0) = G_IMPLICIT_DEF
 457    %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>))
 458    %mask0:_(s8) = G_CONSTANT i8 51
 459    %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0
 460    %mask1:_(s8) = G_CONSTANT i8 72
 461    %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1
 462    %tmp:_(<2 x s8>) = G_AND %unknown, %mask0_splat
 463    %val:_(<2 x s8>) = G_OR %tmp, %mask1_splat
 464    %cst:_(s8) = G_CONSTANT i8 3
 465    %cst_splat:_(<2 x s8>) = G_BUILD_VECTOR %cst, %cst
 466    %shl:_(<2 x s8>) = G_SHL %val, %cst_splat
 467    %copy_shl:_(<2 x s8>) = COPY %shl
 468 )";
 469
 470   setUp(MIRString);
 471   if (!TM)
 472     return;
 473
 474   Register CopyReg = Copies[Copies.size() - 1];
 475   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
 476   Register SrcReg = FinalCopy->getOperand(1).getReg();
 477   GISelKnownBits Info(*MF);
 478   KnownBits Res = Info.getKnownBits(SrcReg);
 479   EXPECT_EQ(0x40u, Res.One.getZExtValue());
 480   EXPECT_EQ(0x27u, Res.Zero.getZExtValue());
 481 }
 482
 483 TEST_F(AArch64GISelMITest, TestKnownBitsVectorADD) {
 484   StringRef MIRString = R"(
 485    %ptr:_(p0) = G_IMPLICIT_DEF
 486    %unknown:_(<2 x s16>) = G_LOAD %ptr(p0) :: (load (<2 x s16>))
 487    %mask0:_(s16) = G_CONSTANT i16 4642
 488    %mask0_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask0, %mask0
 489    %mask1:_(s16) = G_CONSTANT i16 9536
 490    %mask1_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask1, %mask1
 491    %tmp0:_(<2 x s16>) = G_AND %unknown, %mask0_splat
 492    %val0:_(<2 x s16>) = G_OR %tmp0, %mask1_splat
 493    %mask2:_(s16) = G_CONSTANT i16 4096
 494    %mask2_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask2, %mask2
 495    %mask3:_(s16) = G_CONSTANT i16 371
 496    %mask3_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask3, %mask3
 497    %tmp1:_(<2 x s16>) = G_AND %unknown, %mask2_splat
 498    %val1:_(<2 x s16>) = G_OR %tmp1, %mask3_splat
 499    %add:_(<2 x s16>) = G_ADD %val0, %val1
 500    %copy_add:_(<2 x s16>) = COPY %add
 501 )";
 502
 503   setUp(MIRString);
 504   if (!TM)
 505     return;
 506
 507   Register CopyReg = Copies[Copies.size() - 1];
 508   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
 509   Register SrcReg = FinalCopy->getOperand(1).getReg();
 510   GISelKnownBits Info(*MF);
 511   KnownBits Res = Info.getKnownBits(SrcReg);
 512   EXPECT_EQ(0x0091u, Res.One.getZExtValue());
 513   EXPECT_EQ(0x8108u, Res.Zero.getZExtValue());
 514 }
 515
 516 TEST_F(AArch64GISelMITest, TestKnownBitsVectorSUB) {
 517   StringRef MIRString = R"(
 518    %ptr:_(p0) = G_IMPLICIT_DEF
 519    %unknown:_(<2 x s16>) = G_LOAD %ptr(p0) :: (load (<2 x s16>))
 520    %mask0:_(s16) = G_CONSTANT i16 4642
 521    %mask0_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask0, %mask0
 522    %mask1:_(s16) = G_CONSTANT i16 9536
 523    %mask1_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask1, %mask1
 524    %tmp0:_(<2 x s16>) = G_AND %unknown, %mask0_splat
 525    %val0:_(<2 x s16>) = G_OR %tmp0, %mask1_splat
 526    %mask2:_(s16) = G_CONSTANT i16 4096
 527    %mask2_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask2, %mask2
 528    %mask3:_(s16) = G_CONSTANT i16 371
 529    %mask3_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask3, %mask3
 530    %tmp1:_(<2 x s16>) = G_AND %unknown, %mask2_splat
 531    %val1:_(<2 x s16>) = G_OR %tmp1, %mask3_splat
 532    %sub:_(<2 x s16>) = G_SUB %val0, %val1
 533    %copy_sub:_(<2 x s16>) = COPY %sub
 534 )";
 535
 536   setUp(MIRString);
 537   if (!TM)
 538     return;
 539
 540   Register CopyReg = Copies[Copies.size() - 1];
 541   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
 542   Register SrcReg = FinalCopy->getOperand(1).getReg();
 543   GISelKnownBits Info(*MF);
 544   KnownBits Res = Info.getKnownBits(SrcReg);
 545   EXPECT_EQ(0x01CDu, Res.One.getZExtValue());
 546   EXPECT_EQ(0xC810u, Res.Zero.getZExtValue());
 547 }
 548
 549 TEST_F(AArch64GISelMITest, TestKnownBitsVectorMUL) {
 550   StringRef MIRString = R"(
 551    %ptr:_(p0) = G_IMPLICIT_DEF
 552    %unknown:_(<2 x s16>) = G_LOAD %ptr(p0) :: (load (<2 x s16>))
 553    %mask0:_(s16) = G_CONSTANT i16 4
 554    %mask0_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask0, %mask0
 555    %mask1:_(s16) = G_CONSTANT i16 18
 556    %mask1_splat:_(<2 x s16>) = G_BUILD_VECTOR %mask1, %mask1
 557    %tmp:_(<2 x s16>) = G_AND %unknown, %mask0_splat
 558    %val0:_(<2 x s16>) = G_OR %tmp, %mask1_splat
 559    %cst:_(s16) = G_CONSTANT i16 12
 560    %cst_splat:_(<2 x s16>) = G_BUILD_VECTOR %cst, %cst
 561    %mul:_(<2 x s16>) = G_MUL %val0, %cst_splat
 562    %copy_mul:_(<2 x s16>) = COPY %mul
 563 )";
 564
 565   setUp(MIRString);
 566   if (!TM)
 567     return;
 568
 569   Register CopyReg = Copies[Copies.size() - 1];
 570   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
 571   Register SrcReg = FinalCopy->getOperand(1).getReg();
 572   GISelKnownBits Info(*MF);
 573   KnownBits Res = Info.getKnownBits(SrcReg);
 574   EXPECT_EQ(0x0008u, Res.One.getZExtValue());
 575   EXPECT_EQ(0xFE07u, Res.Zero.getZExtValue());
 576 }
 577
 578 TEST_F(AArch64GISelMITest, TestKnownBitsVectorSelect) {
 579   StringRef MIRString = R"(
 580    %ptr:_(p0) = G_IMPLICIT_DEF
 581    %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>))
 582    %mask0:_(s8) = G_CONSTANT i8 24
 583    %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0
 584    %mask1:_(s8) = G_CONSTANT i8 224
 585    %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1
 586    %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat
 587    %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat
 588    %mask2:_(s8) = G_CONSTANT i8 146
 589    %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask2
 590    %mask3:_(s8) = G_CONSTANT i8 36
 591    %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3
 592    %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat
 593    %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat
 594    %cond:_(s1) = G_CONSTANT i1 false
 595    %cond_splat:_(<2 x s1>) = G_BUILD_VECTOR %cond, %cond
 596    %select:_(<2 x s8>) = G_SELECT %cond_splat, %val0, %val1
 597    %copy_select:_(<2 x s8>) = COPY %select
 598 )";
 599
 600   setUp(MIRString);
 601   if (!TM)
 602     return;
 603
 604   Register CopyReg = Copies[Copies.size() - 1];
 605   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
 606   Register SrcReg = FinalCopy->getOperand(1).getReg();
 607   GISelKnownBits Info(*MF);
 608   KnownBits Res = Info.getKnownBits(SrcReg);
 609   EXPECT_EQ(0x20u, Res.One.getZExtValue());
 610   EXPECT_EQ(0x01u, Res.Zero.getZExtValue());
 611 }
 612
 613 TEST_F(AArch64GISelMITest, TestVectorSignBitIsZero) {
 614   setUp();
 615   if (!TM)
 616     return;
 617
 618   const LLT V2S32 = LLT::fixed_vector(2, 32);
 619   // Vector buildConstant makes splat G_BUILD_VECTOR instruction.
 620   auto SignBit = B.buildConstant(V2S32, 0x80000000);
 621   auto Zero = B.buildConstant(V2S32, 0);
 622
 623   const LLT S32 = LLT::scalar(32);
 624   auto NonSplat =
 625       B.buildBuildVector(V2S32, {B.buildConstant(S32, 1).getReg(0),
 626                                  B.buildConstant(S32, 2).getReg(0)});
 627   auto NonSplat2 =
 628       B.buildBuildVector(V2S32, {B.buildConstant(S32, 0x80000000).getReg(0),
 629                                  B.buildConstant(S32, 0x80000004).getReg(0)});
 630   // signBitIsZero is true for elt 0 and false for elt 1 GISelKnownBits takes
 631   // common bits so this is false.
 632   auto NonSplat3 =
 633       B.buildBuildVector(V2S32, {B.buildConstant(S32, 0x80000000).getReg(0),
 634                                  B.buildConstant(S32, 0x8).getReg(0)});
 635   GISelKnownBits KnownBits(*MF);
 636
 637   EXPECT_TRUE(KnownBits.signBitIsZero(Zero.getReg(0)));
 638   EXPECT_FALSE(KnownBits.signBitIsZero(SignBit.getReg(0)));
 639   EXPECT_TRUE(KnownBits.signBitIsZero(NonSplat.getReg(0)));
 640   EXPECT_FALSE(KnownBits.signBitIsZero(NonSplat2.getReg(0)));
 641   EXPECT_FALSE(KnownBits.signBitIsZero(NonSplat3.getReg(0)));
 642 }
 643
 644 TEST_F(AArch64GISelMITest, TestVectorNumSignBitsConstant) {
 645   StringRef MIRString = R"(
 646    %3:_(s8) = G_CONSTANT i8 1
 647    %4:_(<2 x s8>) = G_BUILD_VECTOR %3:_(s8), %3:_(s8)
 648    %5:_(<2 x s8>) = COPY %4
 649
 650    %6:_(s8) = G_CONSTANT i8 -1
 651    %7:_(<2 x s8>) = G_BUILD_VECTOR %6:_(s8), %6:_(s8)
 652    %8:_(<2 x s8>) = COPY %7
 653
 654    %9:_(s8) = G_CONSTANT i8 127
 655    %10:_(<2 x s8>) = G_BUILD_VECTOR %9:_(s8), %9:_(s8)
 656    %11:_(<2 x s8>) = COPY %10
 657
 658    %12:_(s8) = G_CONSTANT i8 32
 659    %13:_(<2 x s8>) = G_BUILD_VECTOR %12:_(s8), %12:_(s8)
 660    %14:_(<2 x s8>) = COPY %13
 661
 662    %15:_(s8) = G_CONSTANT i8 -32
 663    %16:_(<2 x s8>) = G_BUILD_VECTOR %15:_(s8), %15:_(s8)
 664    %17:_(<2 x s8>) = COPY %16
 665
 666    %18:_(<2 x s8>) = G_BUILD_VECTOR %6:_(s8), %15:_(s8)
 667    %19:_(<2 x s8>) = COPY %18
 668
 669    %20:_(<2 x s8>) = G_BUILD_VECTOR %12:_(s8), %15:_(s8)
 670    %21:_(<2 x s8>) = COPY %20
 671 )";
 672
 673   setUp(MIRString);
 674   if (!TM)
 675     return;
 676
 677   Register CopyReg1 = Copies[Copies.size() - 7];
 678   Register CopyRegNeg1 = Copies[Copies.size() - 6];
 679   Register CopyReg127 = Copies[Copies.size() - 5];
 680   Register CopyReg32 = Copies[Copies.size() - 4];
 681   Register CopyRegNeg32 = Copies[Copies.size() - 3];
 682   Register NonSplatSameSign = Copies[Copies.size() - 2];
 683   Register NonSplatDifferentSign = Copies[Copies.size() - 1];
 684
 685   GISelKnownBits Info(*MF);
 686   // If it is known that all elts have same sign looks at common bits and
 687   // effectively returns smallest NumSignBits of all the elts. Otherwise returns
 688   // default value 1.
 689   EXPECT_EQ(7u, Info.computeNumSignBits(CopyReg1));
 690   EXPECT_EQ(8u, Info.computeNumSignBits(CopyRegNeg1));
 691   EXPECT_EQ(1u, Info.computeNumSignBits(CopyReg127));
 692   EXPECT_EQ(2u, Info.computeNumSignBits(CopyReg32));
 693   EXPECT_EQ(3u, Info.computeNumSignBits(CopyRegNeg32));
 694   EXPECT_EQ(3u, Info.computeNumSignBits(NonSplatSameSign));
 695   EXPECT_EQ(1u, Info.computeNumSignBits(NonSplatDifferentSign));
 696 }
 697
 698 TEST_F(AArch64GISelMITest, TestVectorNumSignBitsSext) {
 699   StringRef MIRString = R"(
 700    %3:_(p0) = G_IMPLICIT_DEF
 701    %4:_(<2 x s8>) = G_LOAD %3 :: (load (<2 x s8>))
 702    %5:_(<2 x s32>) = G_SEXT %4
 703    %6:_(<2 x s32>) = COPY %5
 704
 705    %7:_(s8) = G_CONSTANT i8 -1
 706    %8:_(<2 x s8>) = G_BUILD_VECTOR %7:_(s8), %7:_(s8)
 707    %9:_(<2 x s32>) = G_SEXT %8
 708    %10:_(<2 x s32>) = COPY %9
 709
 710    %11:_(s8) = G_CONSTANT i8 -10
 711    %12:_(<2 x s8>) = G_BUILD_VECTOR %7:_(s8), %11:_(s8)
 712    %13:_(<2 x s32>) = G_SEXT %12
 713    %14:_(<2 x s32>) = COPY %13
 714 )";
 715
 716   setUp(MIRString);
 717   if (!TM)
 718     return;
 719   Register CopySextLoad = Copies[Copies.size() - 3];
 720   Register CopySextNeg1 = Copies[Copies.size() - 2];
 721   Register CopySextNonSplat = Copies[Copies.size() - 1];
 722
 723   GISelKnownBits Info(*MF);
 724   EXPECT_EQ(25u, Info.computeNumSignBits(CopySextLoad));
 725   EXPECT_EQ(32u, Info.computeNumSignBits(CopySextNeg1));
 726   EXPECT_EQ(28u, Info.computeNumSignBits(CopySextNonSplat));
 727 }
 728
 729 TEST_F(AArch64GISelMITest, TestVectorNumSignBitsSextInReg) {
 730   StringRef MIRString = R"(
 731    %ptr:_(p0) = G_IMPLICIT_DEF
 732    %load2x4:_(<2 x s32>) = G_LOAD %ptr :: (load (<2 x s32>))
 733
 734    %inreg7:_(<2 x s32>) = G_SEXT_INREG %load2x4, 7
 735    %copy_inreg7:_(<2 x s32>) = COPY %inreg7
 736
 737    %inreg8:_(<2 x s32>) = G_SEXT_INREG %load2x4, 8
 738    %copy_inreg8:_(<2 x s32>) = COPY %inreg8
 739
 740    %inreg9:_(<2 x s32>) = G_SEXT_INREG %load2x4, 9
 741    %copy_inreg9:_(<2 x s32>) = COPY %inreg9
 742
 743    %inreg31:_(<2 x s32>) = G_SEXT_INREG %load2x4, 31
 744    %copy_inreg31:_(<2 x s32>) = COPY %inreg31
 745
 746    %load2x1:_(<2 x s8>) = G_LOAD %ptr :: (load (<2 x s8>))
 747    %sext_load2x1:_(<2 x s32>) = G_SEXT %load2x1
 748
 749    %inreg6_sext:_(<2 x s32>) = G_SEXT_INREG %sext_load2x1, 6
 750    %copy_inreg6_sext:_(<2 x s32>) = COPY %inreg6_sext
 751
 752    %inreg7_sext:_(<2 x s32>) = G_SEXT_INREG %sext_load2x1, 7
 753    %copy_inreg7_sext:_(<2 x s32>) = COPY %inreg7_sext
 754
 755    %inreg8_sext:_(<2 x s32>) = G_SEXT_INREG %sext_load2x1, 8
 756    %copy_inreg8_sext:_(<2 x s32>) = COPY %inreg8_sext
 757
 758    %inreg9_sext:_(<2 x s32>) = G_SEXT_INREG %sext_load2x1, 9
 759    %copy_inreg9_sext:_(<2 x s32>) = COPY %inreg9_sext
 760
 761    %inreg31_sext:_(<2 x s32>) = G_SEXT_INREG %sext_load2x1, 31
 762    %copy_inreg31_sext:_(<2 x s32>) = COPY %inreg31_sext
 763 )";
 764
 765   setUp(MIRString);
 766   if (!TM)
 767     return;
 768
 769   Register CopyInReg7 = Copies[Copies.size() - 9];
 770   Register CopyInReg8 = Copies[Copies.size() - 8];
 771   Register CopyInReg9 = Copies[Copies.size() - 7];
 772   Register CopyInReg31 = Copies[Copies.size() - 6];
 773
 774   Register CopyInReg6Sext = Copies[Copies.size() - 5];
 775   Register CopyInReg7Sext = Copies[Copies.size() - 4];
 776   Register CopyInReg8Sext = Copies[Copies.size() - 3];
 777   Register CopyInReg9Sext = Copies[Copies.size() - 2];
 778   Register CopyInReg31Sext = Copies[Copies.size() - 1];
 779
 780   GISelKnownBits Info(*MF);
 781   EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7));
 782   EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8));
 783   EXPECT_EQ(24u, Info.computeNumSignBits(CopyInReg9));
 784   EXPECT_EQ(2u, Info.computeNumSignBits(CopyInReg31));
 785
 786   EXPECT_EQ(27u, Info.computeNumSignBits(CopyInReg6Sext));
 787   EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7Sext));
 788   EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8Sext));
 789   EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg9Sext));
 790   EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg31Sext));
 791 }
 792
 793 TEST_F(AArch64GISelMITest, TestNumSignBitsVectorAssertSext) {
 794   StringRef MIRString = R"(
 795    %ptr:_(p0) = G_IMPLICIT_DEF
 796    %load2x4:_(<2 x s32>) = G_LOAD %ptr :: (load (<2 x s32>))
 797
 798    %assert_sext1:_(<2 x s32>) = G_ASSERT_SEXT %load2x4, 1
 799    %copy_assert_sext1:_(<2 x s32>) = COPY %assert_sext1
 800
 801    %assert_sext7:_(<2 x s32>) = G_ASSERT_SEXT %load2x4, 7
 802    %copy_assert_sext7:_(<2 x s32>) = COPY %assert_sext7
 803
 804    %assert_sext8:_(<2 x s32>) = G_ASSERT_SEXT %load2x4, 8
 805    %copy_assert_sext8:_(<2 x s32>) = COPY %assert_sext8
 806
 807    %assert_sext9:_(<2 x s32>) = G_ASSERT_SEXT %load2x4, 9
 808    %copy_assert_sext9:_(<2 x s32>) = COPY %assert_sext9
 809
 810    %assert_sext31:_(<2 x s32>) = G_ASSERT_SEXT %load2x4, 31
 811    %copy_assert_sext31:_(<2 x s32>) = COPY %assert_sext31
 812
 813    %load2x1:_(<2 x s8>) = G_LOAD %ptr :: (load (<2 x s8>))
 814    %sext_load2x1:_(<2 x s32>) = G_SEXT %load2x1
 815
 816    %assert_sext6_sext:_(<2 x s32>) = G_ASSERT_SEXT %sext_load2x1, 6
 817    %copy_assert_sext6_sext:_(<2 x s32>) = COPY %assert_sext6_sext
 818
 819    %assert_sext7_sext:_(<2 x s32>) = G_ASSERT_SEXT %sext_load2x1, 7
 820    %copy_assert_sext7_sext:_(<2 x s32>) = COPY %assert_sext7_sext
 821
 822    %assert_sext8_sext:_(<2 x s32>) = G_ASSERT_SEXT %sext_load2x1, 8
 823    %copy_assert_sext8_sext:_(<2 x s32>) = COPY %assert_sext8_sext
 824
 825    %assert_sext9_sext:_(<2 x s32>) = G_ASSERT_SEXT %sext_load2x1, 9
 826    %copy_assert_sext9_sext:_(<2 x s32>) = COPY %assert_sext9_sext
 827
 828    %assert_sext31_sext:_(<2 x s32>) = G_ASSERT_SEXT %sext_load2x1, 31
 829    %copy_assert_sext31_sext:_(<2 x s32>) = COPY %assert_sext31_sext
 830 )";
 831
 832   setUp(MIRString);
 833   if (!TM)
 834     return;
 835
 836   Register CopyInReg1 = Copies[Copies.size() - 10];
 837   Register CopyInReg7 = Copies[Copies.size() - 9];
 838   Register CopyInReg8 = Copies[Copies.size() - 8];
 839   Register CopyInReg9 = Copies[Copies.size() - 7];
 840   Register CopyInReg31 = Copies[Copies.size() - 6];
 841
 842   Register CopyInReg6Sext = Copies[Copies.size() - 5];
 843   Register CopyInReg7Sext = Copies[Copies.size() - 4];
 844   Register CopyInReg8Sext = Copies[Copies.size() - 3];
 845   Register CopyInReg9Sext = Copies[Copies.size() - 2];
 846   Register CopyInReg31Sext = Copies[Copies.size() - 1];
 847
 848   GISelKnownBits Info(*MF);
 849   EXPECT_EQ(32u, Info.computeNumSignBits(CopyInReg1));
 850   EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7));
 851   EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8));
 852   EXPECT_EQ(24u, Info.computeNumSignBits(CopyInReg9));
 853   EXPECT_EQ(2u, Info.computeNumSignBits(CopyInReg31));
 854
 855   EXPECT_EQ(27u, Info.computeNumSignBits(CopyInReg6Sext));
 856   EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7Sext));
 857   EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8Sext));
 858   EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg9Sext));
 859   EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg31Sext));
 860 }
 861
 862 TEST_F(AArch64GISelMITest, TestVectorNumSignBitsTrunc) {
 863   StringRef MIRString = R"(
 864    %3:_(p0) = G_IMPLICIT_DEF
 865    %4:_(<2 x s32>) = G_LOAD %3 :: (load (<2 x s32>))
 866    %5:_(<2 x s8>) = G_TRUNC %4
 867    %6:_(<2 x s8>) = COPY %5
 868
 869    %7:_(s32) = G_CONSTANT i32 -1
 870    %8:_(<2 x s32>) = G_BUILD_VECTOR %7:_(s32), %7:_(s32)
 871    %9:_(<2 x s8>) = G_TRUNC %8
 872    %10:_(<2 x s8>) = COPY %9
 873
 874    %11:_(s32) = G_CONSTANT i32 7
 875    %12:_(<2 x s32>) = G_BUILD_VECTOR %11:_(s32), %11:_(s32)
 876    %13:_(<2 x s8>) = G_TRUNC %12
 877    %14:_(<2 x s8>) = COPY %13
 878 )";
 879
 880   setUp(MIRString);
 881   if (!TM)
 882     return;
 883
 884   Register CopyTruncLoad = Copies[Copies.size() - 3];
 885   Register CopyTruncNeg1 = Copies[Copies.size() - 2];
 886   Register CopyTrunc7 = Copies[Copies.size() - 1];
 887
 888   GISelKnownBits Info(*MF);
 889   EXPECT_EQ(1u, Info.computeNumSignBits(CopyTruncLoad));
 890   EXPECT_EQ(8u, Info.computeNumSignBits(CopyTruncNeg1));
 891   EXPECT_EQ(5u, Info.computeNumSignBits(CopyTrunc7));
 892 }
 893
 894 TEST_F(AMDGPUGISelMITest, TestVectorIsKnownToBeAPowerOfTwo) {
 895
 896   StringRef MIRString = R"(
 897   %zero:_(s32) = G_CONSTANT i32 0
 898   %zero_splat:_(<2 x s32>) = G_BUILD_VECTOR %zero:_(s32), %zero:_(s32)
 899   %one:_(s32) = G_CONSTANT i32 1
 900   %one_splat:_(<2 x s32>) = G_BUILD_VECTOR %one:_(s32), %one:_(s32)
 901   %two:_(s32) = G_CONSTANT i32 2
 902   %two_splat:_(<2 x s32>) = G_BUILD_VECTOR %two:_(s32), %two:_(s32)
 903   %three:_(s32) = G_CONSTANT i32 3
 904   %three_splat:_(<2 x s32>) = G_BUILD_VECTOR %three:_(s32), %three:_(s32)
 905   %five:_(s32) = G_CONSTANT i32 5
 906   %five_splat:_(<2 x s32>) = G_BUILD_VECTOR %five:_(s32), %five:_(s32)
 907   %copy_zero_splat:_(<2 x s32>) = COPY %zero_splat
 908   %copy_one_splat:_(<2 x s32>) = COPY %one_splat
 909   %copy_two_splat:_(<2 x s32>) = COPY %two_splat
 910   %copy_three_splat:_(<2 x s32>) = COPY %three_splat
 911
 912   %trunc_two_splat:_(<2 x s1>) = G_TRUNC %two_splat
 913   %trunc_three_splat:_(<2 x s1>) = G_TRUNC %three_splat
 914   %trunc_five_splat:_(<2 x s1>) = G_TRUNC %five_splat
 915
 916   %copy_trunc_two_splat:_(<2 x s1>) = COPY %trunc_two_splat
 917   %copy_trunc_three_splat:_(<2 x s1>) = COPY %trunc_three_splat
 918   %copy_trunc_five_splat:_(<2 x s1>) = COPY %trunc_five_splat
 919
 920   %ptr:_(p1) = G_IMPLICIT_DEF
 921   %shift_amt:_(<2 x s32>) = G_LOAD %ptr :: (load (<2 x s32>), addrspace 1)
 922
 923   %shl_1:_(<2 x s32>) = G_SHL %one_splat, %shift_amt
 924   %copy_shl_1:_(<2 x s32>) = COPY %shl_1
 925
 926   %shl_2:_(<2 x s32>) = G_SHL %two_splat, %shift_amt
 927   %copy_shl_2:_(<2 x s32>) = COPY %shl_2
 928
 929   %not_sign_mask:_(<2 x s32>) = G_LOAD %ptr :: (load (<2 x s32>), addrspace 1)
 930   %sign_mask:_(s32) = G_CONSTANT i32 -2147483648
 931   %sign_mask_splat:_(<2 x s32>) = G_BUILD_VECTOR %sign_mask:_(s32), %sign_mask:_(s32)
 932
 933   %lshr_not_sign_mask:_(<2 x s32>) = G_LSHR %not_sign_mask, %shift_amt
 934   %copy_lshr_not_sign_mask:_(<2 x s32>) = COPY %lshr_not_sign_mask
 935
 936   %lshr_sign_mask:_(<2 x s32>) = G_LSHR %sign_mask_splat, %shift_amt
 937   %copy_lshr_sign_mask:_(<2 x s32>) = COPY %lshr_sign_mask
 938
 939   %or_pow2:_(<2 x s32>) = G_OR %zero_splat, %two_splat
 940   %copy_or_pow2:_(<2 x s32>) = COPY %or_pow2
 941 )";
 942
 943   setUp(MIRString);
 944   if (!TM)
 945     return;
 946
 947   GISelKnownBits KB(*MF);
 948
 949   Register CopyZero = Copies[Copies.size() - 12];
 950   Register CopyOne = Copies[Copies.size() - 11];
 951   Register CopyTwo = Copies[Copies.size() - 10];
 952   Register CopyThree = Copies[Copies.size() - 9];
 953   Register CopyTruncTwo = Copies[Copies.size() - 8];
 954   Register CopyTruncThree = Copies[Copies.size() - 7];
 955   Register CopyTruncFive = Copies[Copies.size() - 6];
 956
 957   Register CopyShl1 = Copies[Copies.size() - 5];
 958   Register CopyShl2 = Copies[Copies.size() - 4];
 959
 960   Register CopyLShrNotSignMask = Copies[Copies.size() - 3];
 961   Register CopyLShrSignMask = Copies[Copies.size() - 2];
 962   Register CopyOrPow2 = Copies[Copies.size() - 1];
 963
 964   EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyZero, *MRI, &KB));
 965   EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyOne, *MRI, &KB));
 966   EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyTwo, *MRI, &KB));
 967   EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyThree, *MRI, &KB));
 968
 969   EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyTruncTwo, *MRI, &KB));
 970   EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyTruncThree, *MRI, &KB));
 971   EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyTruncFive, *MRI, &KB));
 972   // TODO: check for vector(splat) shift amount.
 973   EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyShl1, *MRI, &KB));
 974   EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyShl2, *MRI, &KB));
 975
 976   EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyLShrNotSignMask, *MRI, &KB));
 977   EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyLShrSignMask, *MRI, &KB));
 978   EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyOrPow2, *MRI, &KB));
 979 }
 980
 981 TEST_F(AArch64GISelMITest, TestVectorMetadata) {
 982   StringRef MIRString = R"(
 983    %imp:_(p0) = G_IMPLICIT_DEF
 984    %load:_(<2 x s8>) = G_LOAD %imp(p0) :: (load (<2 x s8>))
 985    %ext:_(<2 x s32>) = G_ZEXT %load(<2 x s8>)
 986    %cst_elt:_(s32) = G_CONSTANT i32 1
 987    %cst:_(<2 x s32>) = G_BUILD_VECTOR %cst_elt:_(s32), %cst_elt:_(s32)
 988    %and:_(<2 x s32>) = G_AND %ext, %cst
 989    %copy:_(<2 x s32>) = COPY %and(<2 x s32>)
 990 )";
 991
 992   setUp(MIRString);
 993   if (!TM)
 994     return;
 995
 996   Register CopyReg = Copies[Copies.size() - 1];
 997   MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
 998   Register SrcReg = FinalCopy->getOperand(1).getReg();
 999
1000   MachineInstr *And = MRI->getVRegDef(SrcReg);
1001   MachineInstr *Ext = MRI->getVRegDef(And->getOperand(1).getReg());
1002   MachineInstr *Load = MRI->getVRegDef(Ext->getOperand(1).getReg());
1003   IntegerType *Int8Ty = Type::getInt8Ty(Context);
1004
1005   Metadata *LowAndHigh[] = {
1006       ConstantAsMetadata::get(ConstantInt::get(Int8Ty, 0)),
1007       ConstantAsMetadata::get(ConstantInt::get(Int8Ty, 2))};
1008   auto *NewMDNode = MDNode::get(Context, LowAndHigh);
1009   const MachineMemOperand *OldMMO = *Load->memoperands_begin();
1010   MachineMemOperand NewMMO(OldMMO->getPointerInfo(), OldMMO->getFlags(),
1011                            OldMMO->getSizeInBits(), OldMMO->getAlign(),
1012                            OldMMO->getAAInfo(), NewMDNode);
1013   MachineIRBuilder MIB(*Load);
1014   MIB.buildLoad(Load->getOperand(0), Load->getOperand(1), NewMMO);
1015   Load->eraseFromParent();
1016
1017   GISelKnownBits Info(*MF);
1018   KnownBits Res = Info.getKnownBits(And->getOperand(1).getReg());
1019
1020   EXPECT_TRUE(Res.One.isZero());
1021
1022   APInt Mask(Res.getBitWidth(), 1);
1023   Mask.flipAllBits();
1024   EXPECT_EQ(Mask.getZExtValue(), Res.Zero.getZExtValue());
1025 }
1026
1027 TEST_F(AArch64GISelMITest, TestVectorKnownBitsExt) {
1028   StringRef MIRString = R"(
1029    %c1:_(s16) = G_CONSTANT i16 1
1030    %c1_splat:_(<2 x s16>) = G_BUILD_VECTOR %c1:_(s16), %c1:_(s16)
1031    %x:_(<2 x s16>) = G_IMPLICIT_DEF
1032    %y:_(<2 x s16>) = G_AND %x, %c1_splat
1033    %anyext:_(<2 x s32>) = G_ANYEXT %y(<2 x s16>)
1034    %r1:_(<2 x s32>) = COPY %anyext
1035    %zext:_(<2 x s32>) = G_ZEXT %y(<2 x s16>)
1036    %r2:_(<2 x s32>) = COPY %zext
1037    %sext:_(<2 x s32>) = G_SEXT %y(<2 x s16>)
1038    %r3:_(<2 x s32>) = COPY %sext
1039 )";
1040
1041   setUp(MIRString);
1042   if (!TM)
1043     return;
1044   Register CopyRegAny = Copies[Copies.size() - 3];
1045   Register CopyRegZ = Copies[Copies.size() - 2];
1046   Register CopyRegS = Copies[Copies.size() - 1];
1047
1048   GISelKnownBits Info(*MF);
1049   MachineInstr *Copy;
1050   Register SrcReg;
1051   KnownBits Res;
1052
1053   Copy = MRI->getVRegDef(CopyRegAny);
1054   SrcReg = Copy->getOperand(1).getReg();
1055   Res = Info.getKnownBits(SrcReg);
1056   EXPECT_EQ((uint64_t)32, Res.getBitWidth());
1057   EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
1058   EXPECT_EQ((uint64_t)0x0000fffe, Res.Zero.getZExtValue());
1059
1060   Copy = MRI->getVRegDef(CopyRegZ);
1061   SrcReg = Copy->getOperand(1).getReg();
1062   Res = Info.getKnownBits(SrcReg);
1063   EXPECT_EQ((uint64_t)32, Res.getBitWidth());
1064   EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
1065   EXPECT_EQ((uint64_t)0xfffffffe, Res.Zero.getZExtValue());
1066
1067   Copy = MRI->getVRegDef(CopyRegS);
1068   SrcReg = Copy->getOperand(1).getReg();
1069   Res = Info.getKnownBits(SrcReg);
1070   EXPECT_EQ((uint64_t)32, Res.getBitWidth());
1071   EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
1072   EXPECT_EQ((uint64_t)0xfffffffe, Res.Zero.getZExtValue());
1073 }
1074
1075 TEST_F(AArch64GISelMITest, TestKnownBitsVectorSextInReg) {
1076   StringRef MIRString = R"(
1077    ; 000...0001
1078    %one:_(s32) = G_CONSTANT i32 1
1079    %one_splat:_(<2 x s32>) = G_BUILD_VECTOR %one:_(s32), %one:_(s32)
1080
1081    ; 000...0010
1082    %two:_(s32) = G_CONSTANT i32 2
1083    %two_splat:_(<2 x s32>) = G_BUILD_VECTOR %two:_(s32), %two:_(s32)
1084
1085    ; 000...1010
1086    %ten:_(s32) = G_CONSTANT i32 10
1087    %ten_splat:_(<2 x s32>) = G_BUILD_VECTOR %ten:_(s32), %ten:_(s32)
1088
1089    ; ???...????
1090    %x0:_(<2 x s32>) = COPY $x0
1091
1092    ; ???...?1?
1093    %or:_(<2 x s32>) = G_OR %x0, %two_splat
1094
1095    ; All bits are known.
1096    %inreg1:_(<2 x s32>) = G_SEXT_INREG %one_splat, 1
1097    %copy_inreg1:_(<2 x s32>) = COPY %inreg1
1098
1099    ; All bits unknown
1100    %inreg2:_(<2 x s32>) = G_SEXT_INREG %or, 1
1101    %copy_inreg2:_(<2 x s32>) = COPY %inreg2
1102
1103    ; Extending from the only (known) set bit
1104    ; 111...11?
1105    %inreg3:_(<2 x s32>) = G_SEXT_INREG %or, 2
1106    %copy_inreg3:_(<2 x s32>) = COPY %inreg3
1107
1108    ; Extending from a known set bit, overwriting all of the high set bits.
1109    ; 111...1110
1110    %inreg4:_(<2 x s32>) = G_SEXT_INREG %ten_splat, 2
1111    %copy_inreg4:_(<2 x s32>) = COPY %inreg4
1112
1113 )";
1114   setUp(MIRString);
1115   if (!TM)
1116     return;
1117   GISelKnownBits Info(*MF);
1118   KnownBits Res;
1119   auto GetKB = [&](unsigned Idx) {
1120     Register CopyReg = Copies[Idx];
1121     auto *Copy = MRI->getVRegDef(CopyReg);
1122     return Info.getKnownBits(Copy->getOperand(1).getReg());
1123   };
1124
1125   Res = GetKB(Copies.size() - 4);
1126   EXPECT_EQ(32u, Res.getBitWidth());
1127   EXPECT_TRUE(Res.isAllOnes());
1128
1129   Res = GetKB(Copies.size() - 3);
1130   EXPECT_EQ(32u, Res.getBitWidth());
1131   EXPECT_TRUE(Res.isUnknown());
1132
1133   Res = GetKB(Copies.size() - 2);
1134   EXPECT_EQ(32u, Res.getBitWidth());
1135   EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue());
1136   EXPECT_EQ(0u, Res.Zero.getZExtValue());
1137
1138   Res = GetKB(Copies.size() - 1);
1139   EXPECT_EQ(32u, Res.getBitWidth());
1140   EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue());
1141   EXPECT_EQ(1u, Res.Zero.getZExtValue());
1142 }
1143
1144 TEST_F(AArch64GISelMITest, TestKnownBitsVectorAssertSext) {
1145   StringRef MIRString = R"(
1146    ; 000...0001
1147    %one:_(s32) = G_CONSTANT i32 1
1148    %one_splat:_(<2 x s32>) = G_BUILD_VECTOR %one, %one
1149
1150    ; 000...0010
1151    %two:_(s32) = G_CONSTANT i32 2
1152    %two_splat:_(<2 x s32>) = G_BUILD_VECTOR %two, %two
1153
1154    ; 000...1010
1155    %ten:_(s32) = G_CONSTANT i32 10
1156    %ten_splat:_(<2 x s32>) = G_BUILD_VECTOR %ten, %ten
1157
1158    ; ???...????
1159    %x0:_(<2 x s32>) = COPY $x0
1160
1161    ; ???...?1?
1162    %or:_(<2 x s32>) = G_OR %x0, %two_splat
1163
1164    ; All bits are known.
1165    %assert_sext1:_(<2 x s32>) = G_ASSERT_SEXT %one_splat, 1
1166    %copy_assert_sext1:_(<2 x s32>) = COPY %assert_sext1
1167
1168    ; All bits unknown
1169    %assert_sext2:_(<2 x s32>) = G_ASSERT_SEXT %or, 1
1170    %copy_assert_sext2:_(<2 x s32>) = COPY %assert_sext2
1171
1172    ; Extending from the only (known) set bit
1173    ; 111...11?
1174    %assert_sext3:_(<2 x s32>) = G_ASSERT_SEXT %or, 2
1175    %copy_assert_sext3:_(<2 x s32>) = COPY %assert_sext3
1176
1177    ; Extending from a known set bit, overwriting all of the high set bits.
1178    ; 111...1110
1179    %assert_sext4:_(<2 x s32>) = G_ASSERT_SEXT %ten_splat, 2
1180    %copy_assert_sext4:_(<2 x s32>) = COPY %assert_sext4
1181 )";
1182   setUp(MIRString);
1183   if (!TM)
1184     return;
1185   GISelKnownBits Info(*MF);
1186   KnownBits Res;
1187   auto GetKB = [&](unsigned Idx) {
1188     Register CopyReg = Copies[Idx];
1189     auto *Copy = MRI->getVRegDef(CopyReg);
1190     return Info.getKnownBits(Copy->getOperand(1).getReg());
1191   };
1192
1193   // Every bit is known to be a 1.
1194   Res = GetKB(Copies.size() - 4);
1195   EXPECT_EQ(32u, Res.getBitWidth());
1196   EXPECT_TRUE(Res.isAllOnes());
1197
1198   // All bits are unknown
1199   Res = GetKB(Copies.size() - 3);
1200   EXPECT_EQ(32u, Res.getBitWidth());
1201   EXPECT_TRUE(Res.isUnknown());
1202
1203   // Extending from the only known set bit
1204   // 111...11?
1205   Res = GetKB(Copies.size() - 2);
1206   EXPECT_EQ(32u, Res.getBitWidth());
1207   EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue());
1208   EXPECT_EQ(0u, Res.Zero.getZExtValue());
1209
1210   // Extending from a known set bit, overwriting all of the high set bits.
1211   // 111...1110
1212   Res = GetKB(Copies.size() - 1);
1213   EXPECT_EQ(32u, Res.getBitWidth());
1214   EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue());
1215   EXPECT_EQ(1u, Res.Zero.getZExtValue());
1216 }
1217
1218 TEST_F(AArch64GISelMITest, TestVectorKnownBitsBSwapBitReverse) {
1219   StringRef MIRString = R"(
1220    %const:_(s32) = G_CONSTANT i32 287454020
1221    %const_splat:_(<2 x s32>) = G_BUILD_VECTOR %const:_(s32), %const:_(s32)
1222    %bswap:_(<2 x s32>) = G_BSWAP %const_splat
1223    %bitreverse:_(<2 x s32>) = G_BITREVERSE %const_splat
1224    %copy_bswap:_(<2 x s32>) = COPY %bswap
1225    %copy_bitreverse:_(<2 x s32>) = COPY %bitreverse
1226 )";
1227   setUp(MIRString);
1228   if (!TM)
1229     return;
1230
1231   const uint32_t ByteSwappedVal = 0x44332211;
1232   const uint32_t BitSwappedVal = 0x22cc4488;
1233
1234   Register CopyBSwap = Copies[Copies.size() - 2];
1235   Register CopyBitReverse = Copies[Copies.size() - 1];
1236
1237   GISelKnownBits Info(*MF);
1238
1239   KnownBits BSwapKnown = Info.getKnownBits(CopyBSwap);
1240   EXPECT_EQ(32u, BSwapKnown.getBitWidth());
1241   EXPECT_EQ(ByteSwappedVal, BSwapKnown.One.getZExtValue());
1242   EXPECT_EQ(~ByteSwappedVal, BSwapKnown.Zero.getZExtValue());
1243
1244   KnownBits BitReverseKnown = Info.getKnownBits(CopyBitReverse);
1245   EXPECT_EQ(32u, BitReverseKnown.getBitWidth());
1246   EXPECT_EQ(BitSwappedVal, BitReverseKnown.One.getZExtValue());
1247   EXPECT_EQ(~BitSwappedVal, BitReverseKnown.Zero.getZExtValue());
1248 }
1249
1250 TEST_F(AArch64GISelMITest, TestKnownBitsVectorUMAX) {
1251   StringRef MIRString = R"(
1252    %ptr:_(p0) = G_IMPLICIT_DEF
1253    %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>))
1254    %mask0:_(s8) = G_CONSTANT i8 10
1255    %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0
1256    %mask1:_(s8) = G_CONSTANT i8 1
1257    %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1
1258    %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat
1259    %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat
1260    %mask2:_(s8) = G_CONSTANT i8 3
1261    %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask2
1262    %mask3:_(s8) = G_CONSTANT i8 12
1263    %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3
1264    %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat
1265    %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat
1266    %umax0:_(<2 x s8>) = G_UMAX %val0, %val1
1267    %copy_umax0:_(<2 x s8>) = COPY %umax0
1268
1269    %mask4:_(s8) = G_CONSTANT i8 14
1270    %mask4_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask4, %mask4
1271    %mask5:_(s8) = G_CONSTANT i8 2
1272    %mask5_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask5, %mask5
1273    %tmp3:_(<2 x s8>) = G_AND %unknown, %mask4_splat
1274    %val3:_(<2 x s8>) = G_OR %tmp3, %mask5_splat
1275    %mask6:_(s8) = G_CONSTANT i8 4
1276    %mask6_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask6, %mask6
1277    %mask7:_(s8) = G_CONSTANT i8 11
1278    %mask7_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask7, %mask7
1279    %tmp4:_(<2 x s8>) = G_AND %unknown, %mask6_splat
1280    %val4:_(<2 x s8>) = G_OR %tmp4, %mask7_splat
1281    %umax1:_(<2 x s8>) = G_UMAX %val3, %val4
1282    %copy_umax1:_(<2 x s8>) = COPY %umax1
1283 )";
1284
1285   setUp(MIRString);
1286   if (!TM)
1287     return;
1288
1289   Register CopyReg0 = Copies[Copies.size() - 2];
1290   MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
1291   Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
1292   GISelKnownBits Info(*MF);
1293   KnownBits Res0 = Info.getKnownBits(SrcReg0);
1294   EXPECT_EQ(0x0Cu, Res0.One.getZExtValue());
1295   EXPECT_EQ(0xF0u, Res0.Zero.getZExtValue());
1296
1297   Register CopyReg1 = Copies[Copies.size() - 1];
1298   MachineInstr *FinalCopy1 = MRI->getVRegDef(CopyReg1);
1299   Register SrcReg1 = FinalCopy1->getOperand(1).getReg();
1300   KnownBits Res1 = Info.getKnownBits(SrcReg1);
1301   EXPECT_EQ(0x0Au, Res1.One.getZExtValue());
1302   EXPECT_EQ(0xF0u, Res1.Zero.getZExtValue());
1303 }
1304
1305 TEST_F(AArch64GISelMITest, TestVectorKnownBitsUMax) {
1306   StringRef MIRString = R"(
1307    %val:_(<2 x s32>) = COPY $x0
1308    %zext:_(<2 x s64>) = G_ZEXT %val
1309    %const:_(s64) = G_CONSTANT i64 -256
1310    %const_splat:_(<2 x s64>) = G_BUILD_VECTOR %const:_(s64), %const:_(s64)
1311    %umax:_(<2 x s64>) = G_UMAX %zext, %const_splat
1312    %copy_umax:_(<2 x s64>) = COPY %umax
1313 )";
1314
1315   setUp(MIRString);
1316   if (!TM)
1317     return;
1318
1319   Register CopyUMax = Copies[Copies.size() - 1];
1320   GISelKnownBits Info(*MF);
1321
1322   KnownBits KnownUmax = Info.getKnownBits(CopyUMax);
1323   EXPECT_EQ(64u, KnownUmax.getBitWidth());
1324   EXPECT_EQ(0xffu, KnownUmax.Zero.getZExtValue());
1325   EXPECT_EQ(0xffffffffffffff00, KnownUmax.One.getZExtValue());
1326
1327   EXPECT_EQ(0xffu, KnownUmax.Zero.getZExtValue());
1328   EXPECT_EQ(0xffffffffffffff00, KnownUmax.One.getZExtValue());
1329 }
1330
1331 TEST_F(AArch64GISelMITest, TestKnownBitsVectorUMIN) {
1332   StringRef MIRString = R"(
1333    %ptr:_(p0) = G_IMPLICIT_DEF
1334    %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>))
1335    %mask0:_(s8) = G_CONSTANT i8 10
1336    %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0
1337    %mask1:_(s8) = G_CONSTANT i8 1
1338    %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1
1339    %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat
1340    %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat
1341    %mask2:_(s8) = G_CONSTANT i8 3
1342    %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask2
1343    %mask3:_(s8) = G_CONSTANT i8 12
1344    %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3
1345    %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat
1346    %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat
1347    %umin:_(<2 x s8>) = G_UMIN %val0, %val1
1348    %copy_umin:_(<2 x s8>) = COPY %umin
1349 )";
1350
1351   setUp(MIRString);
1352   if (!TM)
1353     return;
1354
1355   Register CopyReg0 = Copies[Copies.size() - 1];
1356   MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
1357   Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
1358   GISelKnownBits Info(*MF);
1359   KnownBits Res0 = Info.getKnownBits(SrcReg0);
1360   EXPECT_EQ(0x01u, Res0.One.getZExtValue());
1361   EXPECT_EQ(0xF4u, Res0.Zero.getZExtValue());
1362 }
1363
1364 TEST_F(AArch64GISelMITest, TestKnownBitsVectorSMAX) {
1365   StringRef MIRString = R"(
1366    %ptr:_(p0) = G_IMPLICIT_DEF
1367    %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>))
1368    %mask0:_(s8) = G_CONSTANT i8 128
1369    %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0
1370    %mask1:_(s8) = G_CONSTANT i8 64
1371    %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1
1372    %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat
1373    %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat
1374    %mask2:_(s8) = G_CONSTANT i8 1
1375    %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask2
1376    %mask3:_(s8) = G_CONSTANT i8 128
1377    %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3
1378    %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat
1379    %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat
1380    %smax:_(<2 x s8>) = G_SMAX %val0, %val1
1381    %copy_smax:_(<2 x s8>) = COPY %smax
1382 )";
1383
1384   setUp(MIRString);
1385   if (!TM)
1386     return;
1387
1388   Register CopyReg0 = Copies[Copies.size() - 1];
1389   MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
1390   Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
1391   GISelKnownBits Info(*MF);
1392   KnownBits Res0 = Info.getKnownBits(SrcReg0);
1393   EXPECT_EQ(0x40u, Res0.One.getZExtValue());
1394   EXPECT_EQ(0x3Fu, Res0.Zero.getZExtValue());
1395 }
1396
1397 TEST_F(AArch64GISelMITest, TestKnownBitsVectorSMIN) {
1398   StringRef MIRString = R"(
1399    %ptr:_(p0) = G_IMPLICIT_DEF
1400    %unknown:_(<2 x s8>) = G_LOAD %ptr(p0) :: (load (<2 x s8>))
1401    %mask0:_(s8) = G_CONSTANT i8 128
1402    %mask0_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask0, %mask0
1403    %mask1:_(s8) = G_CONSTANT i8 64
1404    %mask1_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask1, %mask1
1405    %tmp0:_(<2 x s8>) = G_AND %unknown, %mask0_splat
1406    %val0:_(<2 x s8>) = G_OR %tmp0, %mask1_splat
1407    %mask2:_(s8) = G_CONSTANT i8 1
1408    %mask2_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask2, %mask2
1409    %mask3:_(s8) = G_CONSTANT i8 128
1410    %mask3_splat:_(<2 x s8>) = G_BUILD_VECTOR %mask3, %mask3
1411    %tmp1:_(<2 x s8>) = G_AND %unknown, %mask2_splat
1412    %val1:_(<2 x s8>) = G_OR %tmp1, %mask3_splat
1413    %smin:_(<2 x s8>) = G_SMIN %val0, %val1
1414    %copy_smin:_(<2 x s8>) = COPY %smin
1415 )";
1416
1417   setUp(MIRString);
1418   if (!TM)
1419     return;
1420
1421   Register CopyReg0 = Copies[Copies.size() - 1];
1422   MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
1423   Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
1424   GISelKnownBits Info(*MF);
1425   KnownBits Res0 = Info.getKnownBits(SrcReg0);
1426   EXPECT_EQ(0x80u, Res0.One.getZExtValue());
1427   EXPECT_EQ(0x7Eu, Res0.Zero.getZExtValue());
1428 }
1429
1430 TEST_F(AArch64GISelMITest, TestVectorInvalidQueries) {
1431   StringRef MIRString = R"(
1432    %src:_(<2 x s32>) = COPY $x0
1433    %thirty2:_(s32) = G_CONSTANT i32 32
1434    %thirty2_splat:_(<2 x s32>) = G_BUILD_VECTOR %thirty2:_(s32), %thirty2:_(s32)
1435    %equalSized:_(<2 x s32>) = G_SHL %src, %thirty2_splat
1436    %copy1:_(<2 x s32>) = COPY %equalSized
1437    %thirty3:_(s32) = G_CONSTANT i32 33
1438    %thirty3_splat:_(<2 x s32>) = G_BUILD_VECTOR %thirty3:_(s32), %thirty3:_(s32)
1439    %biggerSized:_(<2 x s32>) = G_SHL %src, %thirty3_splat
1440    %copy2:_(<2 x s32>) = COPY %biggerSized
1441 )";
1442   setUp(MIRString);
1443   if (!TM)
1444     return;
1445
1446   Register EqSizedCopyReg = Copies[Copies.size() - 2];
1447   MachineInstr *EqSizedCopy = MRI->getVRegDef(EqSizedCopyReg);
1448   Register EqSizedShl = EqSizedCopy->getOperand(1).getReg();
1449
1450   Register BiggerSizedCopyReg = Copies[Copies.size() - 1];
1451   MachineInstr *BiggerSizedCopy = MRI->getVRegDef(BiggerSizedCopyReg);
1452   Register BiggerSizedShl = BiggerSizedCopy->getOperand(1).getReg();
1453
1454   GISelKnownBits Info(*MF);
1455   KnownBits EqSizeRes = Info.getKnownBits(EqSizedShl);
1456   KnownBits BiggerSizeRes = Info.getKnownBits(BiggerSizedShl);
1457
1458   EXPECT_TRUE(EqSizeRes.One.isZero());
1459   EXPECT_TRUE(EqSizeRes.Zero.isZero());
1460
1461   EXPECT_TRUE(BiggerSizeRes.One.isZero());
1462   EXPECT_TRUE(BiggerSizeRes.Zero.isZero());
1463 }
1464
1465 TEST_F(AArch64GISelMITest, TestKnownBitsVectorAssertZext) {
1466   StringRef MIRString = R"(
1467    %copy_x0:_(s64) = COPY $x0
1468    %copy_x1:_(s64) = COPY $x1
1469    %x0_x1:_(<2 x s64>) = G_BUILD_VECTOR %copy_x0, %copy_x1
1470
1471    %assert8:_(<2 x s64>) = G_ASSERT_ZEXT %x0_x1, 8
1472    %copy_assert8:_(<2 x s64>) = COPY %assert8
1473
1474    %assert1:_(<2 x s64>) = G_ASSERT_ZEXT %x0_x1, 1
1475    %copy_assert1:_(<2 x s64>) = COPY %assert1
1476
1477    %assert63:_(<2 x s64>) = G_ASSERT_ZEXT %x0_x1, 63
1478    %copy_assert63:_(<2 x s64>) = COPY %assert63
1479
1480    %assert3:_(<2 x s64>) = G_ASSERT_ZEXT %x0_x1, 3
1481    %copy_assert3:_(<2 x s64>) = COPY %assert3
1482 )";
1483
1484   setUp(MIRString);
1485   if (!TM)
1486     return;
1487
1488   Register CopyAssert8 = Copies[Copies.size() - 4];
1489   Register CopyAssert1 = Copies[Copies.size() - 3];
1490   Register CopyAssert63 = Copies[Copies.size() - 2];
1491   Register CopyAssert3 = Copies[Copies.size() - 1];
1492
1493   GISelKnownBits Info(*MF);
1494   MachineInstr *Copy;
1495   Register SrcReg;
1496   KnownBits Res;
1497
1498   // Assert zero-extension from an 8-bit value.
1499   Copy = MRI->getVRegDef(CopyAssert8);
1500   SrcReg = Copy->getOperand(1).getReg();
1501   Res = Info.getKnownBits(SrcReg);
1502   EXPECT_EQ(64u, Res.getBitWidth());
1503   EXPECT_EQ(0u, Res.One.getZExtValue());
1504   EXPECT_EQ(0xFFFFFFFFFFFFFF00u, Res.Zero.getZExtValue());
1505
1506   // Assert zero-extension from a 1-bit value.
1507   Copy = MRI->getVRegDef(CopyAssert1);
1508   SrcReg = Copy->getOperand(1).getReg();
1509   Res = Info.getKnownBits(SrcReg);
1510   EXPECT_EQ(64u, Res.getBitWidth());
1511   EXPECT_EQ(0u, Res.One.getZExtValue());
1512   EXPECT_EQ(0xFFFFFFFFFFFFFFFE, Res.Zero.getZExtValue());
1513
1514   // Assert zero-extension from a 63-bit value.
1515   Copy = MRI->getVRegDef(CopyAssert63);
1516   SrcReg = Copy->getOperand(1).getReg();
1517   Res = Info.getKnownBits(SrcReg);
1518   EXPECT_EQ(64u, Res.getBitWidth());
1519   EXPECT_EQ(0u, Res.One.getZExtValue());
1520   EXPECT_EQ(0x8000000000000000u, Res.Zero.getZExtValue());
1521
1522   // Assert zero-extension from a 3-bit value.
1523   Copy = MRI->getVRegDef(CopyAssert3);
1524   SrcReg = Copy->getOperand(1).getReg();
1525   Res = Info.getKnownBits(SrcReg);
1526   EXPECT_EQ(64u, Res.getBitWidth());
1527   EXPECT_EQ(0u, Res.One.getZExtValue());
1528   EXPECT_EQ(0xFFFFFFFFFFFFFFF8u, Res.Zero.getZExtValue());
1529 }
1530
1531 TEST_F(AArch64GISelMITest, TestNumSignBitsUAddoOverflow) {
1532   StringRef MIRString = R"(
1533    %copy_x0:_(s64) = COPY $x0
1534    %copy_x1:_(s64) = COPY $x1
1535    %x0_x1:_(<2 x s64>) = G_BUILD_VECTOR %copy_x0, %copy_x1
1536    %uaddo:_(<2 x s64>), %overflow:_(<2 x s32>) = G_UADDO %x0_x1, %x0_x1
1537    %result:_(<2 x s32>) = COPY %overflow
1538 )";
1539
1540   setUp(MIRString);
1541   if (!TM)
1542     return;
1543
1544   Register CopyOverflow = Copies[Copies.size() - 1];
1545
1546   GISelKnownBits Info(*MF);
1547
1548   // Assert sign-extension from vector boolean
1549   EXPECT_EQ(32u, Info.computeNumSignBits(CopyOverflow));
1550 }