llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp

   1 //===-- SnippetGeneratorTest.cpp --------------------------------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 #include "../Common/AssemblerUtils.h"
  10 #include "LlvmState.h"
  11 #include "MCInstrDescView.h"
  12 #include "ParallelSnippetGenerator.h"
  13 #include "RegisterAliasing.h"
  14 #include "SerialSnippetGenerator.h"
  15 #include "TestBase.h"
  16 #include "X86InstrInfo.h"
  17
  18 #include <unordered_set>
  19
  20 namespace llvm {
  21 namespace exegesis {
  22
  23 void InitializeX86ExegesisTarget();
  24
  25 namespace {
  26
  27 using testing::AnyOf;
  28 using testing::ElementsAre;
  29 using testing::Gt;
  30 using testing::HasSubstr;
  31 using testing::Not;
  32 using testing::SizeIs;
  33 using testing::UnorderedElementsAre;
  34
  35 MATCHER(IsInvalid, "") { return !arg.isValid(); }
  36 MATCHER(IsReg, "") { return arg.isReg(); }
  37
  38 template <typename SnippetGeneratorT>
  39 class X86SnippetGeneratorTest : public X86TestBase {
  40 protected:
  41   X86SnippetGeneratorTest() : Generator(State, SnippetGenerator::Options()),
  42                               InstrInfo(State.getInstrInfo()) {}
  43
  44   std::vector<CodeTemplate> checkAndGetCodeTemplates(unsigned Opcode) {
  45     randomGenerator().seed(0); // Initialize seed.
  46     const Instruction &Instr = State.getIC().getInstr(Opcode);
  47     auto CodeTemplateOrError = Generator.generateCodeTemplates(
  48         &Instr, State.getRATC().emptyRegisters());
  49     EXPECT_FALSE(CodeTemplateOrError.takeError()); // Valid configuration.
  50     return std::move(CodeTemplateOrError.get());
  51   }
  52
  53   SnippetGeneratorT Generator;
  54   const MCInstrInfo &InstrInfo;
  55 };
  56
  57 using X86SerialSnippetGeneratorTest = X86SnippetGeneratorTest<SerialSnippetGenerator>;
  58
  59 using X86ParallelSnippetGeneratorTest =
  60     X86SnippetGeneratorTest<ParallelSnippetGenerator>;
  61
  62 TEST_F(X86SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughImplicitReg) {
  63   // - ADC16i16
  64   // - Op0 Explicit Use Immediate
  65   // - Op1 Implicit Def Reg(AX)
  66   // - Op2 Implicit Def Reg(EFLAGS)
  67   // - Op3 Implicit Use Reg(AX)
  68   // - Op4 Implicit Use Reg(EFLAGS)
  69   // - Var0 [Op0]
  70   // - hasAliasingImplicitRegisters (execution is always serial)
  71   // - hasAliasingRegisters
  72   const unsigned Opcode = X86::ADC16i16;
  73   EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[0], X86::AX);
  74   EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[1], X86::EFLAGS);
  75   EXPECT_THAT(InstrInfo.get(Opcode).getImplicitUses()[0], X86::AX);
  76   EXPECT_THAT(InstrInfo.get(Opcode).getImplicitUses()[1], X86::EFLAGS);
  77   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
  78   ASSERT_THAT(CodeTemplates, SizeIs(1));
  79   const auto &CT = CodeTemplates[0];
  80   EXPECT_THAT(CT.Execution, ExecutionMode::ALWAYS_SERIAL_IMPLICIT_REGS_ALIAS);
  81   ASSERT_THAT(CT.Instructions, SizeIs(1));
  82   const InstructionTemplate &IT = CT.Instructions[0];
  83   EXPECT_THAT(IT.getOpcode(), Opcode);
  84   ASSERT_THAT(IT.getVariableValues(), SizeIs(1)); // Imm.
  85   EXPECT_THAT(IT.getVariableValues()[0], IsInvalid()) << "Immediate is not set";
  86 }
  87
  88 TEST_F(X86SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughTiedRegs) {
  89   // - ADD16ri
  90   // - Op0 Explicit Def RegClass(GR16)
  91   // - Op1 Explicit Use RegClass(GR16) TiedToOp0
  92   // - Op2 Explicit Use Immediate
  93   // - Op3 Implicit Def Reg(EFLAGS)
  94   // - Var0 [Op0,Op1]
  95   // - Var1 [Op2]
  96   // - hasTiedRegisters (execution is always serial)
  97   // - hasAliasingRegisters
  98   const unsigned Opcode = X86::ADD16ri;
  99   EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[0], X86::EFLAGS);
 100   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
 101   ASSERT_THAT(CodeTemplates, SizeIs(1));
 102   const auto &CT = CodeTemplates[0];
 103   EXPECT_THAT(CT.Execution, ExecutionMode::ALWAYS_SERIAL_TIED_REGS_ALIAS);
 104   ASSERT_THAT(CT.Instructions, SizeIs(1));
 105   const InstructionTemplate &IT = CT.Instructions[0];
 106   EXPECT_THAT(IT.getOpcode(), Opcode);
 107   ASSERT_THAT(IT.getVariableValues(), SizeIs(2));
 108   EXPECT_THAT(IT.getVariableValues()[0], IsInvalid()) << "Operand 1 is not set";
 109   EXPECT_THAT(IT.getVariableValues()[1], IsInvalid()) << "Operand 2 is not set";
 110 }
 111
 112 TEST_F(X86SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) {
 113   // - VXORPSrr
 114   // - Op0 Explicit Def RegClass(VR128)
 115   // - Op1 Explicit Use RegClass(VR128)
 116   // - Op2 Explicit Use RegClass(VR128)
 117   // - Var0 [Op0]
 118   // - Var1 [Op1]
 119   // - Var2 [Op2]
 120   // - hasAliasingRegisters
 121   const unsigned Opcode = X86::VXORPSrr;
 122   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
 123   ASSERT_THAT(CodeTemplates, SizeIs(1));
 124   const auto &CT = CodeTemplates[0];
 125   EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_EXPLICIT_REGS);
 126   ASSERT_THAT(CT.Instructions, SizeIs(1));
 127   const InstructionTemplate &IT = CT.Instructions[0];
 128   EXPECT_THAT(IT.getOpcode(), Opcode);
 129   ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
 130   EXPECT_THAT(IT.getVariableValues(),
 131               AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()),
 132                     ElementsAre(IsReg(), IsReg(), IsInvalid())))
 133       << "Op0 is either set to Op1 or to Op2";
 134 }
 135
 136 TEST_F(X86SerialSnippetGeneratorTest,
 137        ImplicitSelfDependencyThroughExplicitRegsForbidAll) {
 138   // - VXORPSrr
 139   // - Op0 Explicit Def RegClass(VR128)
 140   // - Op1 Explicit Use RegClass(VR128)
 141   // - Op2 Explicit Use RegClass(VR128)
 142   // - Var0 [Op0]
 143   // - Var1 [Op1]
 144   // - Var2 [Op2]
 145   // - hasAliasingRegisters
 146   const unsigned Opcode = X86::VXORPSrr;
 147   randomGenerator().seed(0); // Initialize seed.
 148   const Instruction &Instr = State.getIC().getInstr(Opcode);
 149   auto AllRegisters = State.getRATC().emptyRegisters();
 150   AllRegisters.flip();
 151   auto Error =
 152       Generator.generateCodeTemplates(&Instr, AllRegisters).takeError();
 153   EXPECT_TRUE((bool)Error);
 154   consumeError(std::move(Error));
 155 }
 156
 157 TEST_F(X86SerialSnippetGeneratorTest, DependencyThroughOtherOpcode) {
 158   // - CMP64rr
 159   // - Op0 Explicit Use RegClass(GR64)
 160   // - Op1 Explicit Use RegClass(GR64)
 161   // - Op2 Implicit Def Reg(EFLAGS)
 162   // - Var0 [Op0]
 163   // - Var1 [Op1]
 164   const unsigned Opcode = X86::CMP64rr;
 165   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
 166   ASSERT_THAT(CodeTemplates, SizeIs(Gt(1U))) << "Many templates are available";
 167   for (const auto &CT : CodeTemplates) {
 168     EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR);
 169     ASSERT_THAT(CT.Instructions, SizeIs(2));
 170     const InstructionTemplate &IT = CT.Instructions[0];
 171     EXPECT_THAT(IT.getOpcode(), Opcode);
 172     ASSERT_THAT(IT.getVariableValues(), SizeIs(2));
 173     EXPECT_THAT(IT.getVariableValues(),
 174                 AnyOf(ElementsAre(IsReg(), IsInvalid()),
 175                       ElementsAre(IsInvalid(), IsReg())));
 176     EXPECT_THAT(CT.Instructions[1].getOpcode(), Not(Opcode));
 177     // TODO: check that the two instructions alias each other.
 178   }
 179 }
 180
 181 TEST_F(X86SerialSnippetGeneratorTest, LAHF) {
 182   // - LAHF
 183   // - Op0 Implicit Def Reg(AH)
 184   // - Op1 Implicit Use Reg(EFLAGS)
 185   const unsigned Opcode = X86::LAHF;
 186   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
 187   ASSERT_THAT(CodeTemplates, SizeIs(Gt(1U))) << "Many templates are available";
 188   for (const auto &CT : CodeTemplates) {
 189     EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR);
 190     ASSERT_THAT(CT.Instructions, SizeIs(2));
 191     const InstructionTemplate &IT = CT.Instructions[0];
 192     EXPECT_THAT(IT.getOpcode(), Opcode);
 193     ASSERT_THAT(IT.getVariableValues(), SizeIs(0));
 194   }
 195 }
 196
 197 TEST_F(X86SerialSnippetGeneratorTest, VCVTUSI642SDZrrb_Int) {
 198   // - VCVTUSI642SDZrrb_Int
 199   // - Op0 Explicit Def RegClass(VR128X)
 200   // - Op1 Explicit Use RegClass(VR128X)
 201   // - Op2 Explicit Use STATIC_ROUNDING
 202   // - Op2 Explicit Use RegClass(GR64)
 203   // - Op4 Implicit Use Reg(MXSCR)
 204   const unsigned Opcode = X86::VCVTUSI642SDZrrb_Int;
 205   const Instruction &Instr = State.getIC().getInstr(Opcode);
 206   std::vector<BenchmarkCode> Configs;
 207   auto Error = Generator.generateConfigurations(
 208       &Instr, Configs, State.getRATC().emptyRegisters());
 209   ASSERT_FALSE(Error);
 210   ASSERT_THAT(Configs, SizeIs(1));
 211   const BenchmarkCode &BC = Configs[0];
 212   ASSERT_THAT(BC.Key.Instructions, SizeIs(1));
 213   ASSERT_TRUE(BC.Key.Instructions[0].getOperand(3).isImm());
 214 }
 215
 216 TEST_F(X86ParallelSnippetGeneratorTest, SerialInstruction) {
 217   // - CDQ
 218   // - Op0 Implicit Def Reg(EAX)
 219   // - Op1 Implicit Def Reg(EDX)
 220   // - Op2 Implicit Use Reg(EAX)
 221   // - hasAliasingImplicitRegisters (execution is always serial)
 222   // - hasAliasingRegisters
 223   const unsigned Opcode = X86::CDQ;
 224   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
 225   ASSERT_THAT(CodeTemplates, SizeIs(1));
 226   const auto &CT = CodeTemplates[0];
 227   EXPECT_THAT(CT.Info, HasSubstr("serial"));
 228   EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
 229   ASSERT_THAT(CT.Instructions, SizeIs(1));
 230   const InstructionTemplate &IT = CT.Instructions[0];
 231   EXPECT_THAT(IT.getOpcode(), Opcode);
 232   ASSERT_THAT(IT.getVariableValues(), SizeIs(0));
 233 }
 234
 235 TEST_F(X86ParallelSnippetGeneratorTest, StaticRenaming) {
 236   // CMOV32rr has tied variables, we enumerate the possible values to execute
 237   // as many in parallel as possible.
 238
 239   // - CMOV32rr
 240   // - Op0 Explicit Def RegClass(GR32)
 241   // - Op1 Explicit Use RegClass(GR32) TiedToOp0
 242   // - Op2 Explicit Use RegClass(GR32)
 243   // - Op3 Explicit Use Immediate
 244   // - Op3 Implicit Use Reg(EFLAGS)
 245   // - Var0 [Op0,Op1]
 246   // - Var1 [Op2]
 247   // - hasTiedRegisters (execution is always serial)
 248   // - hasAliasingRegisters
 249   const unsigned Opcode = X86::CMOV32rr;
 250   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
 251   ASSERT_THAT(CodeTemplates, SizeIs(1));
 252   const auto &CT = CodeTemplates[0];
 253   EXPECT_THAT(CT.Info, HasSubstr("static renaming"));
 254   EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
 255   constexpr const unsigned kInstructionCount = 15;
 256   ASSERT_THAT(CT.Instructions, SizeIs(kInstructionCount));
 257   std::unordered_set<unsigned> AllDefRegisters;
 258   for (const auto &IT : CT.Instructions) {
 259     ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
 260     AllDefRegisters.insert(IT.getVariableValues()[0].getReg());
 261   }
 262   EXPECT_THAT(AllDefRegisters, SizeIs(kInstructionCount))
 263       << "Each instruction writes to a different register";
 264 }
 265
 266 TEST_F(X86ParallelSnippetGeneratorTest, NoTiedVariables) {
 267   // CMOV_GR32 has no tied variables, we make sure def and use are different
 268   // from each other.
 269
 270   // - CMOV_GR32
 271   // - Op0 Explicit Def RegClass(GR32)
 272   // - Op1 Explicit Use RegClass(GR32)
 273   // - Op2 Explicit Use RegClass(GR32)
 274   // - Op3 Explicit Use Immediate
 275   // - Op4 Implicit Use Reg(EFLAGS)
 276   // - Var0 [Op0]
 277   // - Var1 [Op1]
 278   // - Var2 [Op2]
 279   // - Var3 [Op3]
 280   // - hasAliasingRegisters
 281   const unsigned Opcode = X86::CMOV_GR32;
 282   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
 283   ASSERT_THAT(CodeTemplates, SizeIs(1));
 284   const auto &CT = CodeTemplates[0];
 285   EXPECT_THAT(CT.Info, HasSubstr("no tied variables"));
 286   EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
 287   ASSERT_THAT(CT.Instructions, SizeIs(1));
 288   const InstructionTemplate &IT = CT.Instructions[0];
 289   EXPECT_THAT(IT.getOpcode(), Opcode);
 290   ASSERT_THAT(IT.getVariableValues(), SizeIs(4));
 291   EXPECT_THAT(IT.getVariableValues()[0].getReg(),
 292               Not(IT.getVariableValues()[1].getReg()))
 293       << "Def is different from first Use";
 294   EXPECT_THAT(IT.getVariableValues()[0].getReg(),
 295               Not(IT.getVariableValues()[2].getReg()))
 296       << "Def is different from second Use";
 297   EXPECT_THAT(IT.getVariableValues()[3], IsInvalid());
 298 }
 299
 300 TEST_F(X86ParallelSnippetGeneratorTest, MemoryUse) {
 301   // Mov32rm reads from memory.
 302   // - MOV32rm
 303   // - Op0 Explicit Def RegClass(GR32)
 304   // - Op1 Explicit Use Memory RegClass(GR8)
 305   // - Op2 Explicit Use Memory
 306   // - Op3 Explicit Use Memory RegClass(GRH8)
 307   // - Op4 Explicit Use Memory
 308   // - Op5 Explicit Use Memory RegClass(SEGMENT_REG)
 309   // - Var0 [Op0]
 310   // - Var1 [Op1]
 311   // - Var2 [Op2]
 312   // - Var3 [Op3]
 313   // - Var4 [Op4]
 314   // - Var5 [Op5]
 315   // - hasMemoryOperands
 316   // - hasAliasingRegisters
 317   const unsigned Opcode = X86::MOV32rm;
 318   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
 319   ASSERT_THAT(CodeTemplates, SizeIs(1));
 320   const auto &CT = CodeTemplates[0];
 321   EXPECT_THAT(CT.Info, HasSubstr("no tied variables"));
 322   EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
 323   ASSERT_THAT(CT.Instructions,
 324               SizeIs(ParallelSnippetGenerator::kMinNumDifferentAddresses));
 325   const InstructionTemplate &IT = CT.Instructions[0];
 326   EXPECT_THAT(IT.getOpcode(), Opcode);
 327   ASSERT_THAT(IT.getVariableValues(), SizeIs(6));
 328   EXPECT_EQ(IT.getVariableValues()[2].getImm(), 1);
 329   EXPECT_EQ(IT.getVariableValues()[3].getReg(), 0u);
 330   EXPECT_EQ(IT.getVariableValues()[4].getImm(), 0);
 331   EXPECT_EQ(IT.getVariableValues()[5].getReg(), 0u);
 332 }
 333
 334 TEST_F(X86ParallelSnippetGeneratorTest, MOV16ms) {
 335   const unsigned Opcode = X86::MOV16ms;
 336   const Instruction &Instr = State.getIC().getInstr(Opcode);
 337   std::vector<BenchmarkCode> Benchmarks;
 338   auto Err = Generator.generateConfigurations(&Instr, Benchmarks,
 339                                               State.getRATC().emptyRegisters());
 340   EXPECT_TRUE((bool)Err);
 341   EXPECT_THAT(toString(std::move(Err)),
 342               testing::HasSubstr("no available registers"));
 343 }
 344
 345 TEST_F(X86ParallelSnippetGeneratorTest,
 346        AvoidSerializingThroughImplicitRegisters) {
 347   // MULX32rr implicitly uses EDX. We should not select that register to avoid
 348   // serialization.
 349   const unsigned Opcode = X86::MULX32rr;
 350   randomGenerator().seed(0); // Initialize seed.
 351   const Instruction &Instr = State.getIC().getInstr(Opcode);
 352   // Forbid all registers but RDX/EDX/DX/DH/DL. The only option would be to
 353   // choose that register, but that would serialize the instruction, so we
 354   // should be returning an error.
 355   auto AllRegisters = State.getRATC().emptyRegisters();
 356   AllRegisters.flip();
 357   AllRegisters.reset(X86::RDX);
 358   AllRegisters.reset(X86::EDX);
 359   AllRegisters.reset(X86::DX);
 360   AllRegisters.reset(X86::DH);
 361   AllRegisters.reset(X86::DL);
 362   auto Err = Generator.generateCodeTemplates(&Instr, AllRegisters);
 363   EXPECT_FALSE((bool)Err);
 364   EXPECT_THAT(toString(Err.takeError()),
 365               testing::HasSubstr("no available registers"));
 366 }
 367
 368 class X86FakeSnippetGenerator : public SnippetGenerator {
 369 public:
 370   X86FakeSnippetGenerator(const LLVMState &State, const Options &Opts)
 371       : SnippetGenerator(State, Opts) {}
 372
 373   const Instruction &getInstr(unsigned Opcode) {
 374     return State.getIC().getInstr(Opcode);
 375   }
 376
 377   InstructionTemplate getInstructionTemplate(unsigned Opcode) {
 378     return {&getInstr(Opcode)};
 379   }
 380
 381 private:
 382   Expected<std::vector<CodeTemplate>>
 383   generateCodeTemplates(InstructionTemplate, const BitVector &) const override {
 384     return make_error<StringError>("not implemented", inconvertibleErrorCode());
 385   }
 386 };
 387
 388 using X86FakeSnippetGeneratorTest = X86SnippetGeneratorTest<X86FakeSnippetGenerator>;
 389
 390 testing::Matcher<const RegisterValue &> IsRegisterValue(unsigned Reg,
 391                                                         APInt Value) {
 392   return testing::AllOf(testing::Field(&RegisterValue::Register, Reg),
 393                         testing::Field(&RegisterValue::Value, Value));
 394 }
 395
 396 TEST_F(X86FakeSnippetGeneratorTest, MemoryUse_Movsb) {
 397   // MOVSB writes to scratch memory register.
 398   // - MOVSB
 399   // - Op0 Explicit Use Memory RegClass(GR8)
 400   // - Op1 Explicit Use Memory RegClass(GR8)
 401   // - Op2 Explicit Use Memory RegClass(SEGMENT_REG)
 402   // - Op3 Implicit Def Reg(EDI)
 403   // - Op4 Implicit Def Reg(ESI)
 404   // - Op5 Implicit Use Reg(EDI)
 405   // - Op6 Implicit Use Reg(ESI)
 406   // - Op7 Implicit Use Reg(DF)
 407   // - Var0 [Op0]
 408   // - Var1 [Op1]
 409   // - Var2 [Op2]
 410   // - hasMemoryOperands
 411   // - hasAliasingImplicitRegisters (execution is always serial)
 412   // - hasAliasingRegisters
 413   const unsigned Opcode = X86::MOVSB;
 414   const Instruction &Instr = State.getIC().getInstr(Opcode);
 415   std::vector<BenchmarkCode> Benchmarks;
 416   auto Error = Generator.generateConfigurations(
 417       &Instr, Benchmarks, State.getRATC().emptyRegisters());
 418   EXPECT_TRUE((bool)Error);
 419   consumeError(std::move(Error));
 420 }
 421
 422 TEST_F(X86FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd16ri) {
 423   // ADD16ri:
 424   // explicit def 0       : reg RegClass=GR16
 425   // explicit use 1       : reg RegClass=GR16 | TIED_TO:0
 426   // explicit use 2       : imm
 427   // implicit def         : EFLAGS
 428   InstructionTemplate IT = Generator.getInstructionTemplate(X86::ADD16ri);
 429   IT.getValueFor(IT.getInstr().Variables[0]) = MCOperand::createReg(X86::AX);
 430   std::vector<InstructionTemplate> Snippet;
 431   Snippet.push_back(std::move(IT));
 432   const auto RIV = Generator.computeRegisterInitialValues(Snippet);
 433   EXPECT_THAT(RIV, ElementsAre(IsRegisterValue(X86::AX, APInt())));
 434 }
 435
 436 TEST_F(X86FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd64rr) {
 437   // ADD64rr:
 438   //  mov64ri rax, 42
 439   //  add64rr rax, rax, rbx
 440   // -> only rbx needs defining.
 441   std::vector<InstructionTemplate> Snippet;
 442   {
 443     InstructionTemplate Mov = Generator.getInstructionTemplate(X86::MOV64ri);
 444     Mov.getValueFor(Mov.getInstr().Variables[0]) =
 445         MCOperand::createReg(X86::RAX);
 446     Mov.getValueFor(Mov.getInstr().Variables[1]) = MCOperand::createImm(42);
 447     Snippet.push_back(std::move(Mov));
 448   }
 449   {
 450     InstructionTemplate Add = Generator.getInstructionTemplate(X86::ADD64rr);
 451     Add.getValueFor(Add.getInstr().Variables[0]) =
 452         MCOperand::createReg(X86::RAX);
 453     Add.getValueFor(Add.getInstr().Variables[1]) =
 454         MCOperand::createReg(X86::RBX);
 455     Snippet.push_back(std::move(Add));
 456   }
 457
 458   const auto RIV = Generator.computeRegisterInitialValues(Snippet);
 459   EXPECT_THAT(RIV, ElementsAre(IsRegisterValue(X86::RBX, APInt())));
 460 }
 461
 462 } // namespace
 463 } // namespace exegesis
 464 } // namespace llvm