1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=armv7a--none-eabi -float-abi soft -mattr=+fp16 < %s | FileCheck %s --check-prefix=SOFT
3 ; RUN: llc -mtriple=armv7a--none-eabi -float-abi hard -mattr=+fp16 < %s | FileCheck %s --check-prefix=HARD
4 ; RUN: llc -mtriple=armv7a--none-eabi -float-abi soft -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=FULL-SOFT --check-prefix=FULL-SOFT-LE
5 ; RUN: llc -mtriple=armv7a--none-eabi -float-abi hard -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=FULL-HARD --check-prefix=FULL-HARD-LE
6 ; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi soft -mattr=+fp16 < %s | FileCheck %s --check-prefix=SOFT
7 ; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi hard -mattr=+fp16 < %s | FileCheck %s --check-prefix=HARD
8 ; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi soft -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=FULL-SOFT --check-prefix=FULL-SOFT-BE
9 ; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi hard -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=FULL-HARD --check-prefix=FULL-HARD-BE
11 define half @foo(half %a, half %b) {
13 ; SOFT: @ %bb.0: @ %entry
14 ; SOFT-NEXT: vmov s0, r0
15 ; SOFT-NEXT: vmov s2, r1
16 ; SOFT-NEXT: vcvtb.f32.f16 s0, s0
17 ; SOFT-NEXT: vcvtb.f32.f16 s2, s2
18 ; SOFT-NEXT: vadd.f32 s0, s0, s2
19 ; SOFT-NEXT: vcvtb.f16.f32 s0, s0
20 ; SOFT-NEXT: vmov r0, s0
24 ; HARD: @ %bb.0: @ %entry
25 ; HARD-NEXT: vcvtb.f32.f16 s2, s1
26 ; HARD-NEXT: vcvtb.f32.f16 s0, s0
27 ; HARD-NEXT: vadd.f32 s0, s0, s2
28 ; HARD-NEXT: vcvtb.f16.f32 s0, s0
31 ; FULL-SOFT-LABEL: foo:
32 ; FULL-SOFT: @ %bb.0: @ %entry
33 ; FULL-SOFT-NEXT: vmov.f16 s0, r1
34 ; FULL-SOFT-NEXT: vmov.f16 s2, r0
35 ; FULL-SOFT-NEXT: vadd.f16 s0, s2, s0
36 ; FULL-SOFT-NEXT: vmov r0, s0
37 ; FULL-SOFT-NEXT: bx lr
39 ; FULL-HARD-LABEL: foo:
40 ; FULL-HARD: @ %bb.0: @ %entry
41 ; FULL-HARD-NEXT: vadd.f16 s0, s0, s1
42 ; FULL-HARD-NEXT: bx lr
48 define <4 x half> @foo_vec(<4 x half> %a) {
49 ; SOFT-LABEL: foo_vec:
50 ; SOFT: @ %bb.0: @ %entry
51 ; SOFT-NEXT: vmov s0, r3
52 ; SOFT-NEXT: vmov s2, r1
53 ; SOFT-NEXT: vcvtb.f32.f16 s0, s0
54 ; SOFT-NEXT: vmov s4, r0
55 ; SOFT-NEXT: vcvtb.f32.f16 s2, s2
56 ; SOFT-NEXT: vmov s6, r2
57 ; SOFT-NEXT: vcvtb.f32.f16 s4, s4
58 ; SOFT-NEXT: vcvtb.f32.f16 s6, s6
59 ; SOFT-NEXT: vadd.f32 s0, s0, s0
60 ; SOFT-NEXT: vadd.f32 s2, s2, s2
61 ; SOFT-NEXT: vcvtb.f16.f32 s0, s0
62 ; SOFT-NEXT: vadd.f32 s4, s4, s4
63 ; SOFT-NEXT: vcvtb.f16.f32 s2, s2
64 ; SOFT-NEXT: vadd.f32 s6, s6, s6
65 ; SOFT-NEXT: vcvtb.f16.f32 s4, s4
66 ; SOFT-NEXT: vcvtb.f16.f32 s6, s6
67 ; SOFT-NEXT: vmov r0, s4
68 ; SOFT-NEXT: vmov r1, s2
69 ; SOFT-NEXT: vmov r2, s6
70 ; SOFT-NEXT: vmov r3, s0
73 ; HARD-LABEL: foo_vec:
74 ; HARD: @ %bb.0: @ %entry
75 ; HARD-NEXT: vcvtb.f32.f16 s4, s3
76 ; HARD-NEXT: vcvtb.f32.f16 s2, s2
77 ; HARD-NEXT: vcvtb.f32.f16 s6, s1
78 ; HARD-NEXT: vcvtb.f32.f16 s0, s0
79 ; HARD-NEXT: vadd.f32 s2, s2, s2
80 ; HARD-NEXT: vadd.f32 s0, s0, s0
81 ; HARD-NEXT: vcvtb.f16.f32 s2, s2
82 ; HARD-NEXT: vadd.f32 s4, s4, s4
83 ; HARD-NEXT: vcvtb.f16.f32 s0, s0
84 ; HARD-NEXT: vadd.f32 s6, s6, s6
85 ; HARD-NEXT: vcvtb.f16.f32 s3, s4
86 ; HARD-NEXT: vcvtb.f16.f32 s1, s6
89 ; FULL-SOFT-LE-LABEL: foo_vec:
90 ; FULL-SOFT-LE: @ %bb.0: @ %entry
91 ; FULL-SOFT-LE-NEXT: vmov d16, r0, r1
92 ; FULL-SOFT-LE-NEXT: vadd.f16 d16, d16, d16
93 ; FULL-SOFT-LE-NEXT: vmov r0, r1, d16
94 ; FULL-SOFT-LE-NEXT: bx lr
96 ; FULL-HARD-LE-LABEL: foo_vec:
97 ; FULL-HARD-LE: @ %bb.0: @ %entry
98 ; FULL-HARD-LE-NEXT: vadd.f16 d0, d0, d0
99 ; FULL-HARD-LE-NEXT: bx lr
101 ; FULL-SOFT-BE-LABEL: foo_vec:
102 ; FULL-SOFT-BE: @ %bb.0: @ %entry
103 ; FULL-SOFT-BE-NEXT: vmov d16, r1, r0
104 ; FULL-SOFT-BE-NEXT: vrev64.16 d16, d16
105 ; FULL-SOFT-BE-NEXT: vadd.f16 d16, d16, d16
106 ; FULL-SOFT-BE-NEXT: vrev64.16 d16, d16
107 ; FULL-SOFT-BE-NEXT: vmov r1, r0, d16
108 ; FULL-SOFT-BE-NEXT: bx lr
110 ; FULL-HARD-BE-LABEL: foo_vec:
111 ; FULL-HARD-BE: @ %bb.0: @ %entry
112 ; FULL-HARD-BE-NEXT: vrev64.16 d16, d0
113 ; FULL-HARD-BE-NEXT: vadd.f16 d16, d16, d16
114 ; FULL-HARD-BE-NEXT: vrev64.16 d0, d16
115 ; FULL-HARD-BE-NEXT: bx lr
117 %0 = fadd <4 x half> %a, %a