| blob | 8900d5f541e8aa182d6329d03ab61fc5a8adbf83 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=armv5-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=ARM5
3 ; RUN: llc -mtriple=armv6-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=ARM6
4 ; RUN: llc -mtriple=armv7-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=ARM7
5 ; RUN: llc -mtriple=armv8-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=ARM8
6 ; RUN: llc -mtriple=armv7-unknown-linux-gnu -mattr=+neon < %s | FileCheck %s --check-prefixes=NEON7
7 ; RUN: llc -mtriple=armv8-unknown-linux-gnu -mattr=+neon < %s | FileCheck %s --check-prefixes=NEON8
9 define i1 @test_urem_odd(i13 %X) nounwind {
10 ; ARM5-LABEL: test_urem_odd:
11 ; ARM5: @ %bb.0:
12 ; ARM5-NEXT: mov r1, #205
13 ; ARM5-NEXT: orr r1, r1, #3072
14 ; ARM5-NEXT: mul r2, r0, r1
15 ; ARM5-NEXT: mov r0, #255
16 ; ARM5-NEXT: orr r0, r0, #7936
17 ; ARM5-NEXT: and r1, r2, r0
18 ; ARM5-NEXT: mov r2, #103
19 ; ARM5-NEXT: orr r2, r2, #1536
20 ; ARM5-NEXT: mov r0, #0
21 ; ARM5-NEXT: cmp r1, r2
22 ; ARM5-NEXT: movlo r0, #1
23 ; ARM5-NEXT: bx lr
24 ;
25 ; ARM6-LABEL: test_urem_odd:
26 ; ARM6: @ %bb.0:
27 ; ARM6-NEXT: mov r1, #205
28 ; ARM6-NEXT: mov r2, #103
29 ; ARM6-NEXT: orr r1, r1, #3072
30 ; ARM6-NEXT: orr r2, r2, #1536
31 ; ARM6-NEXT: mul r0, r0, r1
32 ; ARM6-NEXT: mov r1, #255
33 ; ARM6-NEXT: orr r1, r1, #7936
34 ; ARM6-NEXT: and r1, r0, r1
35 ; ARM6-NEXT: mov r0, #0
36 ; ARM6-NEXT: cmp r1, r2
37 ; ARM6-NEXT: movlo r0, #1
38 ; ARM6-NEXT: bx lr
39 ;
40 ; ARM7-LABEL: test_urem_odd:
41 ; ARM7: @ %bb.0:
42 ; ARM7-NEXT: movw r1, #3277
43 ; ARM7-NEXT: movw r2, #1639
44 ; ARM7-NEXT: mul r1, r0, r1
45 ; ARM7-NEXT: mov r0, #0
46 ; ARM7-NEXT: bfc r1, #13, #19
47 ; ARM7-NEXT: cmp r1, r2
48 ; ARM7-NEXT: movwlo r0, #1
49 ; ARM7-NEXT: bx lr
50 ;
51 ; ARM8-LABEL: test_urem_odd:
52 ; ARM8: @ %bb.0:
53 ; ARM8-NEXT: movw r1, #3277
54 ; ARM8-NEXT: movw r2, #1639
55 ; ARM8-NEXT: mul r1, r0, r1
56 ; ARM8-NEXT: mov r0, #0
57 ; ARM8-NEXT: bfc r1, #13, #19
58 ; ARM8-NEXT: cmp r1, r2
59 ; ARM8-NEXT: movwlo r0, #1
60 ; ARM8-NEXT: bx lr
61 ;
62 ; NEON7-LABEL: test_urem_odd:
63 ; NEON7: @ %bb.0:
64 ; NEON7-NEXT: movw r1, #3277
65 ; NEON7-NEXT: movw r2, #1639
66 ; NEON7-NEXT: mul r1, r0, r1
67 ; NEON7-NEXT: mov r0, #0
68 ; NEON7-NEXT: bfc r1, #13, #19
69 ; NEON7-NEXT: cmp r1, r2
70 ; NEON7-NEXT: movwlo r0, #1
71 ; NEON7-NEXT: bx lr
72 ;
73 ; NEON8-LABEL: test_urem_odd:
74 ; NEON8: @ %bb.0:
75 ; NEON8-NEXT: movw r1, #3277
76 ; NEON8-NEXT: movw r2, #1639
77 ; NEON8-NEXT: mul r1, r0, r1
78 ; NEON8-NEXT: mov r0, #0
79 ; NEON8-NEXT: bfc r1, #13, #19
80 ; NEON8-NEXT: cmp r1, r2
81 ; NEON8-NEXT: movwlo r0, #1
82 ; NEON8-NEXT: bx lr
83 %urem = urem i13 %X, 5
84 %cmp = icmp eq i13 %urem, 0
85 ret i1 %cmp
86 }
88 define i1 @test_urem_even(i27 %X) nounwind {
89 ; ARM5-LABEL: test_urem_even:
90 ; ARM5: @ %bb.0:
91 ; ARM5-NEXT: ldr r1, .LCPI1_0
92 ; ARM5-NEXT: mul r2, r0, r1
93 ; ARM5-NEXT: bic r0, r2, #-134217727
94 ; ARM5-NEXT: lsr r0, r0, #1
95 ; ARM5-NEXT: orr r0, r0, r2, lsl #26
96 ; ARM5-NEXT: ldr r2, .LCPI1_1
97 ; ARM5-NEXT: bic r1, r0, #-134217728
98 ; ARM5-NEXT: mov r0, #0
99 ; ARM5-NEXT: cmp r1, r2
100 ; ARM5-NEXT: movlo r0, #1
101 ; ARM5-NEXT: bx lr
102 ; ARM5-NEXT: .p2align 2
103 ; ARM5-NEXT: @ %bb.1:
104 ; ARM5-NEXT: .LCPI1_0:
105 ; ARM5-NEXT: .long 115043767 @ 0x6db6db7
106 ; ARM5-NEXT: .LCPI1_1:
107 ; ARM5-NEXT: .long 9586981 @ 0x924925
108 ;
109 ; ARM6-LABEL: test_urem_even:
110 ; ARM6: @ %bb.0:
111 ; ARM6-NEXT: ldr r1, .LCPI1_0
112 ; ARM6-NEXT: ldr r2, .LCPI1_1
113 ; ARM6-NEXT: mul r0, r0, r1
114 ; ARM6-NEXT: bic r1, r0, #-134217727
115 ; ARM6-NEXT: lsr r1, r1, #1
116 ; ARM6-NEXT: orr r0, r1, r0, lsl #26
117 ; ARM6-NEXT: bic r1, r0, #-134217728
118 ; ARM6-NEXT: mov r0, #0
119 ; ARM6-NEXT: cmp r1, r2
120 ; ARM6-NEXT: movlo r0, #1
121 ; ARM6-NEXT: bx lr
122 ; ARM6-NEXT: .p2align 2
123 ; ARM6-NEXT: @ %bb.1:
124 ; ARM6-NEXT: .LCPI1_0:
125 ; ARM6-NEXT: .long 115043767 @ 0x6db6db7
126 ; ARM6-NEXT: .LCPI1_1:
127 ; ARM6-NEXT: .long 9586981 @ 0x924925
128 ;
129 ; ARM7-LABEL: test_urem_even:
130 ; ARM7: @ %bb.0:
131 ; ARM7-NEXT: movw r1, #28087
132 ; ARM7-NEXT: movw r2, #18725
133 ; ARM7-NEXT: movt r1, #1755
134 ; ARM7-NEXT: movt r2, #146
135 ; ARM7-NEXT: mul r0, r0, r1
136 ; ARM7-NEXT: ubfx r1, r0, #1, #26
137 ; ARM7-NEXT: orr r0, r1, r0, lsl #26
138 ; ARM7-NEXT: bic r1, r0, #-134217728
139 ; ARM7-NEXT: mov r0, #0
140 ; ARM7-NEXT: cmp r1, r2
141 ; ARM7-NEXT: movwlo r0, #1
142 ; ARM7-NEXT: bx lr
143 ;
144 ; ARM8-LABEL: test_urem_even:
145 ; ARM8: @ %bb.0:
146 ; ARM8-NEXT: movw r1, #28087
147 ; ARM8-NEXT: movw r2, #18725
148 ; ARM8-NEXT: movt r1, #1755
149 ; ARM8-NEXT: movt r2, #146
150 ; ARM8-NEXT: mul r0, r0, r1
151 ; ARM8-NEXT: ubfx r1, r0, #1, #26
152 ; ARM8-NEXT: orr r0, r1, r0, lsl #26
153 ; ARM8-NEXT: bic r1, r0, #-134217728
154 ; ARM8-NEXT: mov r0, #0
155 ; ARM8-NEXT: cmp r1, r2
156 ; ARM8-NEXT: movwlo r0, #1
157 ; ARM8-NEXT: bx lr
158 ;
159 ; NEON7-LABEL: test_urem_even:
160 ; NEON7: @ %bb.0:
161 ; NEON7-NEXT: movw r1, #28087
162 ; NEON7-NEXT: movw r2, #18725
163 ; NEON7-NEXT: movt r1, #1755
164 ; NEON7-NEXT: movt r2, #146
165 ; NEON7-NEXT: mul r0, r0, r1
166 ; NEON7-NEXT: ubfx r1, r0, #1, #26
167 ; NEON7-NEXT: orr r0, r1, r0, lsl #26
168 ; NEON7-NEXT: bic r1, r0, #-134217728
169 ; NEON7-NEXT: mov r0, #0
170 ; NEON7-NEXT: cmp r1, r2
171 ; NEON7-NEXT: movwlo r0, #1
172 ; NEON7-NEXT: bx lr
173 ;
174 ; NEON8-LABEL: test_urem_even:
175 ; NEON8: @ %bb.0:
176 ; NEON8-NEXT: movw r1, #28087
177 ; NEON8-NEXT: movw r2, #18725
178 ; NEON8-NEXT: movt r1, #1755
179 ; NEON8-NEXT: movt r2, #146
180 ; NEON8-NEXT: mul r0, r0, r1
181 ; NEON8-NEXT: ubfx r1, r0, #1, #26
182 ; NEON8-NEXT: orr r0, r1, r0, lsl #26
183 ; NEON8-NEXT: bic r1, r0, #-134217728
184 ; NEON8-NEXT: mov r0, #0
185 ; NEON8-NEXT: cmp r1, r2
186 ; NEON8-NEXT: movwlo r0, #1
187 ; NEON8-NEXT: bx lr
188 %urem = urem i27 %X, 14
189 %cmp = icmp eq i27 %urem, 0
190 ret i1 %cmp
191 }
193 define i1 @test_urem_odd_setne(i4 %X) nounwind {
194 ; ARM5-LABEL: test_urem_odd_setne:
195 ; ARM5: @ %bb.0:
196 ; ARM5-NEXT: mov r1, #13
197 ; ARM5-NEXT: mul r2, r0, r1
198 ; ARM5-NEXT: mov r0, #0
199 ; ARM5-NEXT: and r1, r2, #15
200 ; ARM5-NEXT: cmp r1, #3
201 ; ARM5-NEXT: movhi r0, #1
202 ; ARM5-NEXT: bx lr
203 ;
204 ; ARM6-LABEL: test_urem_odd_setne:
205 ; ARM6: @ %bb.0:
206 ; ARM6-NEXT: mov r1, #13
207 ; ARM6-NEXT: mul r0, r0, r1
208 ; ARM6-NEXT: and r1, r0, #15
209 ; ARM6-NEXT: mov r0, #0
210 ; ARM6-NEXT: cmp r1, #3
211 ; ARM6-NEXT: movhi r0, #1
212 ; ARM6-NEXT: bx lr
213 ;
214 ; ARM7-LABEL: test_urem_odd_setne:
215 ; ARM7: @ %bb.0:
216 ; ARM7-NEXT: mov r1, #13
217 ; ARM7-NEXT: mul r0, r0, r1
218 ; ARM7-NEXT: and r1, r0, #15
219 ; ARM7-NEXT: mov r0, #0
220 ; ARM7-NEXT: cmp r1, #3
221 ; ARM7-NEXT: movwhi r0, #1
222 ; ARM7-NEXT: bx lr
223 ;
224 ; ARM8-LABEL: test_urem_odd_setne:
225 ; ARM8: @ %bb.0:
226 ; ARM8-NEXT: mov r1, #13
227 ; ARM8-NEXT: mul r0, r0, r1
228 ; ARM8-NEXT: and r1, r0, #15
229 ; ARM8-NEXT: mov r0, #0
230 ; ARM8-NEXT: cmp r1, #3
231 ; ARM8-NEXT: movwhi r0, #1
232 ; ARM8-NEXT: bx lr
233 ;
234 ; NEON7-LABEL: test_urem_odd_setne:
235 ; NEON7: @ %bb.0:
236 ; NEON7-NEXT: mov r1, #13
237 ; NEON7-NEXT: mul r0, r0, r1
238 ; NEON7-NEXT: and r1, r0, #15
239 ; NEON7-NEXT: mov r0, #0
240 ; NEON7-NEXT: cmp r1, #3
241 ; NEON7-NEXT: movwhi r0, #1
242 ; NEON7-NEXT: bx lr
243 ;
244 ; NEON8-LABEL: test_urem_odd_setne:
245 ; NEON8: @ %bb.0:
246 ; NEON8-NEXT: mov r1, #13
247 ; NEON8-NEXT: mul r0, r0, r1
248 ; NEON8-NEXT: and r1, r0, #15
249 ; NEON8-NEXT: mov r0, #0
250 ; NEON8-NEXT: cmp r1, #3
251 ; NEON8-NEXT: movwhi r0, #1
252 ; NEON8-NEXT: bx lr
253 %urem = urem i4 %X, 5
254 %cmp = icmp ne i4 %urem, 0
255 ret i1 %cmp
256 }
258 define i1 @test_urem_negative_odd(i9 %X) nounwind {
259 ; ARM5-LABEL: test_urem_negative_odd:
260 ; ARM5: @ %bb.0:
261 ; ARM5-NEXT: mov r1, #51
262 ; ARM5-NEXT: orr r1, r1, #256
263 ; ARM5-NEXT: mul r2, r0, r1
264 ; ARM5-NEXT: mov r0, #255
265 ; ARM5-NEXT: orr r0, r0, #256
266 ; ARM5-NEXT: and r1, r2, r0
267 ; ARM5-NEXT: mov r0, #0
268 ; ARM5-NEXT: cmp r1, #1
269 ; ARM5-NEXT: movhi r0, #1
270 ; ARM5-NEXT: bx lr
271 ;
272 ; ARM6-LABEL: test_urem_negative_odd:
273 ; ARM6: @ %bb.0:
274 ; ARM6-NEXT: mov r1, #51
275 ; ARM6-NEXT: orr r1, r1, #256
276 ; ARM6-NEXT: mul r0, r0, r1
277 ; ARM6-NEXT: mov r1, #255
278 ; ARM6-NEXT: orr r1, r1, #256
279 ; ARM6-NEXT: and r1, r0, r1
280 ; ARM6-NEXT: mov r0, #0
281 ; ARM6-NEXT: cmp r1, #1
282 ; ARM6-NEXT: movhi r0, #1
283 ; ARM6-NEXT: bx lr
284 ;
285 ; ARM7-LABEL: test_urem_negative_odd:
286 ; ARM7: @ %bb.0:
287 ; ARM7-NEXT: movw r1, #307
288 ; ARM7-NEXT: mul r1, r0, r1
289 ; ARM7-NEXT: mov r0, #0
290 ; ARM7-NEXT: bfc r1, #9, #23
291 ; ARM7-NEXT: cmp r1, #1
292 ; ARM7-NEXT: movwhi r0, #1
293 ; ARM7-NEXT: bx lr
294 ;
295 ; ARM8-LABEL: test_urem_negative_odd:
296 ; ARM8: @ %bb.0:
297 ; ARM8-NEXT: movw r1, #307
298 ; ARM8-NEXT: mul r1, r0, r1
299 ; ARM8-NEXT: mov r0, #0
300 ; ARM8-NEXT: bfc r1, #9, #23
301 ; ARM8-NEXT: cmp r1, #1
302 ; ARM8-NEXT: movwhi r0, #1
303 ; ARM8-NEXT: bx lr
304 ;
305 ; NEON7-LABEL: test_urem_negative_odd:
306 ; NEON7: @ %bb.0:
307 ; NEON7-NEXT: movw r1, #307
308 ; NEON7-NEXT: mul r1, r0, r1
309 ; NEON7-NEXT: mov r0, #0
310 ; NEON7-NEXT: bfc r1, #9, #23
311 ; NEON7-NEXT: cmp r1, #1
312 ; NEON7-NEXT: movwhi r0, #1
313 ; NEON7-NEXT: bx lr
314 ;
315 ; NEON8-LABEL: test_urem_negative_odd:
316 ; NEON8: @ %bb.0:
317 ; NEON8-NEXT: movw r1, #307
318 ; NEON8-NEXT: mul r1, r0, r1
319 ; NEON8-NEXT: mov r0, #0
320 ; NEON8-NEXT: bfc r1, #9, #23
321 ; NEON8-NEXT: cmp r1, #1
322 ; NEON8-NEXT: movwhi r0, #1
323 ; NEON8-NEXT: bx lr
324 %urem = urem i9 %X, -5
325 %cmp = icmp ne i9 %urem, 0
326 ret i1 %cmp
327 }
329 define <3 x i1> @test_urem_vec(<3 x i11> %X) nounwind {
330 ; ARM5-LABEL: test_urem_vec:
331 ; ARM5: @ %bb.0:
332 ; ARM5-NEXT: push {r4, lr}
333 ; ARM5-NEXT: mov r3, #171
334 ; ARM5-NEXT: orr r3, r3, #512
335 ; ARM5-NEXT: mul r12, r0, r3
336 ; ARM5-NEXT: mov r0, #1020
337 ; ARM5-NEXT: orr r0, r0, #1024
338 ; ARM5-NEXT: mov r3, #254
339 ; ARM5-NEXT: orr r3, r3, #1792
340 ; ARM5-NEXT: and r0, r12, r0
341 ; ARM5-NEXT: lsr r0, r0, #1
342 ; ARM5-NEXT: orr r0, r0, r12, lsl #10
343 ; ARM5-NEXT: sub r12, r1, #1
344 ; ARM5-NEXT: mov r1, #183
345 ; ARM5-NEXT: and r0, r0, r3
346 ; ARM5-NEXT: orr r1, r1, #1280
347 ; ARM5-NEXT: mov r3, #0
348 ; ARM5-NEXT: lsr r0, r0, #1
349 ; ARM5-NEXT: cmp r0, #170
350 ; ARM5-NEXT: mul lr, r12, r1
351 ; ARM5-NEXT: mov r12, #255
352 ; ARM5-NEXT: orr r12, r12, #1792
353 ; ARM5-NEXT: mov r0, #0
354 ; ARM5-NEXT: movhi r0, #1
355 ; ARM5-NEXT: and r1, lr, r12
356 ; ARM5-NEXT: sub lr, r2, #2
357 ; ARM5-NEXT: mov r2, #51
358 ; ARM5-NEXT: cmp r1, #292
359 ; ARM5-NEXT: orr r2, r2, #768
360 ; ARM5-NEXT: mov r1, #0
361 ; ARM5-NEXT: movhi r1, #1
362 ; ARM5-NEXT: mul r4, lr, r2
363 ; ARM5-NEXT: and r2, r4, r12
364 ; ARM5-NEXT: cmp r2, #1
365 ; ARM5-NEXT: movhi r3, #1
366 ; ARM5-NEXT: mov r2, r3
367 ; ARM5-NEXT: pop {r4, pc}
368 ;
369 ; ARM6-LABEL: test_urem_vec:
370 ; ARM6: @ %bb.0:
371 ; ARM6-NEXT: push {r11, lr}
372 ; ARM6-NEXT: mov r3, #171
373 ; ARM6-NEXT: sub r12, r1, #1
374 ; ARM6-NEXT: orr r3, r3, #512
375 ; ARM6-NEXT: mov r1, #183
376 ; ARM6-NEXT: orr r1, r1, #1280
377 ; ARM6-NEXT: sub lr, r2, #2
378 ; ARM6-NEXT: mul r0, r0, r3
379 ; ARM6-NEXT: mov r3, #1020
380 ; ARM6-NEXT: orr r3, r3, #1024
381 ; ARM6-NEXT: mov r2, #51
382 ; ARM6-NEXT: mul r1, r12, r1
383 ; ARM6-NEXT: orr r2, r2, #768
384 ; ARM6-NEXT: mov r12, #255
385 ; ARM6-NEXT: and r3, r0, r3
386 ; ARM6-NEXT: mul r2, lr, r2
387 ; ARM6-NEXT: orr r12, r12, #1792
388 ; ARM6-NEXT: lsr r3, r3, #1
389 ; ARM6-NEXT: orr r0, r3, r0, lsl #10
390 ; ARM6-NEXT: mov r3, #254
391 ; ARM6-NEXT: and r1, r1, r12
392 ; ARM6-NEXT: orr r3, r3, #1792
393 ; ARM6-NEXT: and r0, r0, r3
394 ; ARM6-NEXT: and r2, r2, r12
395 ; ARM6-NEXT: mov r3, #0
396 ; ARM6-NEXT: lsr r0, r0, #1
397 ; ARM6-NEXT: cmp r0, #170
398 ; ARM6-NEXT: mov r0, #0
399 ; ARM6-NEXT: movhi r0, #1
400 ; ARM6-NEXT: cmp r1, #292
401 ; ARM6-NEXT: mov r1, #0
402 ; ARM6-NEXT: movhi r1, #1
403 ; ARM6-NEXT: cmp r2, #1
404 ; ARM6-NEXT: movhi r3, #1
405 ; ARM6-NEXT: mov r2, r3
406 ; ARM6-NEXT: pop {r11, pc}
407 ;
408 ; ARM7-LABEL: test_urem_vec:
409 ; ARM7: @ %bb.0:
410 ; ARM7-NEXT: vmov.16 d16[0], r0
411 ; ARM7-NEXT: vldr d17, .LCPI4_0
412 ; ARM7-NEXT: vmov.16 d16[1], r1
413 ; ARM7-NEXT: vldr d19, .LCPI4_3
414 ; ARM7-NEXT: vmov.16 d16[2], r2
415 ; ARM7-NEXT: vsub.i16 d16, d16, d17
416 ; ARM7-NEXT: vldr d17, .LCPI4_1
417 ; ARM7-NEXT: vmul.i16 d16, d16, d17
418 ; ARM7-NEXT: vldr d17, .LCPI4_2
419 ; ARM7-NEXT: vneg.s16 d17, d17
420 ; ARM7-NEXT: vshl.i16 d18, d16, #1
421 ; ARM7-NEXT: vbic.i16 d16, #0xf800
422 ; ARM7-NEXT: vshl.u16 d16, d16, d17
423 ; ARM7-NEXT: vshl.u16 d17, d18, d19
424 ; ARM7-NEXT: vorr d16, d16, d17
425 ; ARM7-NEXT: vldr d17, .LCPI4_4
426 ; ARM7-NEXT: vbic.i16 d16, #0xf800
427 ; ARM7-NEXT: vcgt.u16 d16, d16, d17
428 ; ARM7-NEXT: vmov.u16 r0, d16[0]
429 ; ARM7-NEXT: vmov.u16 r1, d16[1]
430 ; ARM7-NEXT: vmov.u16 r2, d16[2]
431 ; ARM7-NEXT: bx lr
432 ; ARM7-NEXT: .p2align 3
433 ; ARM7-NEXT: @ %bb.1:
434 ; ARM7-NEXT: .LCPI4_0:
435 ; ARM7-NEXT: .short 0 @ 0x0
436 ; ARM7-NEXT: .short 1 @ 0x1
437 ; ARM7-NEXT: .short 2 @ 0x2
438 ; ARM7-NEXT: .zero 2
439 ; ARM7-NEXT: .LCPI4_1:
440 ; ARM7-NEXT: .short 683 @ 0x2ab
441 ; ARM7-NEXT: .short 1463 @ 0x5b7
442 ; ARM7-NEXT: .short 819 @ 0x333
443 ; ARM7-NEXT: .zero 2
444 ; ARM7-NEXT: .LCPI4_2:
445 ; ARM7-NEXT: .short 1 @ 0x1
446 ; ARM7-NEXT: .short 0 @ 0x0
447 ; ARM7-NEXT: .short 0 @ 0x0
448 ; ARM7-NEXT: .short 0 @ 0x0
449 ; ARM7-NEXT: .LCPI4_3:
450 ; ARM7-NEXT: .short 9 @ 0x9
451 ; ARM7-NEXT: .short 10 @ 0xa
452 ; ARM7-NEXT: .short 10 @ 0xa
453 ; ARM7-NEXT: .short 10 @ 0xa
454 ; ARM7-NEXT: .LCPI4_4:
455 ; ARM7-NEXT: .short 341 @ 0x155
456 ; ARM7-NEXT: .short 292 @ 0x124
457 ; ARM7-NEXT: .short 1 @ 0x1
458 ; ARM7-NEXT: .short 0 @ 0x0
459 ;
460 ; ARM8-LABEL: test_urem_vec:
461 ; ARM8: @ %bb.0:
462 ; ARM8-NEXT: vmov.16 d16[0], r0
463 ; ARM8-NEXT: vldr d17, .LCPI4_0
464 ; ARM8-NEXT: vmov.16 d16[1], r1
465 ; ARM8-NEXT: vldr d19, .LCPI4_3
466 ; ARM8-NEXT: vmov.16 d16[2], r2
467 ; ARM8-NEXT: vsub.i16 d16, d16, d17
468 ; ARM8-NEXT: vldr d17, .LCPI4_1
469 ; ARM8-NEXT: vmul.i16 d16, d16, d17
470 ; ARM8-NEXT: vldr d17, .LCPI4_2
471 ; ARM8-NEXT: vneg.s16 d17, d17
472 ; ARM8-NEXT: vshl.i16 d18, d16, #1
473 ; ARM8-NEXT: vbic.i16 d16, #0xf800
474 ; ARM8-NEXT: vshl.u16 d16, d16, d17
475 ; ARM8-NEXT: vshl.u16 d17, d18, d19
476 ; ARM8-NEXT: vorr d16, d16, d17
477 ; ARM8-NEXT: vldr d17, .LCPI4_4
478 ; ARM8-NEXT: vbic.i16 d16, #0xf800
479 ; ARM8-NEXT: vcgt.u16 d16, d16, d17
480 ; ARM8-NEXT: vmov.u16 r0, d16[0]
481 ; ARM8-NEXT: vmov.u16 r1, d16[1]
482 ; ARM8-NEXT: vmov.u16 r2, d16[2]
483 ; ARM8-NEXT: bx lr
484 ; ARM8-NEXT: .p2align 3
485 ; ARM8-NEXT: @ %bb.1:
486 ; ARM8-NEXT: .LCPI4_0:
487 ; ARM8-NEXT: .short 0 @ 0x0
488 ; ARM8-NEXT: .short 1 @ 0x1
489 ; ARM8-NEXT: .short 2 @ 0x2
490 ; ARM8-NEXT: .zero 2
491 ; ARM8-NEXT: .LCPI4_1:
492 ; ARM8-NEXT: .short 683 @ 0x2ab
493 ; ARM8-NEXT: .short 1463 @ 0x5b7
494 ; ARM8-NEXT: .short 819 @ 0x333
495 ; ARM8-NEXT: .zero 2
496 ; ARM8-NEXT: .LCPI4_2:
497 ; ARM8-NEXT: .short 1 @ 0x1
498 ; ARM8-NEXT: .short 0 @ 0x0
499 ; ARM8-NEXT: .short 0 @ 0x0
500 ; ARM8-NEXT: .short 0 @ 0x0
501 ; ARM8-NEXT: .LCPI4_3:
502 ; ARM8-NEXT: .short 9 @ 0x9
503 ; ARM8-NEXT: .short 10 @ 0xa
504 ; ARM8-NEXT: .short 10 @ 0xa
505 ; ARM8-NEXT: .short 10 @ 0xa
506 ; ARM8-NEXT: .LCPI4_4:
507 ; ARM8-NEXT: .short 341 @ 0x155
508 ; ARM8-NEXT: .short 292 @ 0x124
509 ; ARM8-NEXT: .short 1 @ 0x1
510 ; ARM8-NEXT: .short 0 @ 0x0
511 ;
512 ; NEON7-LABEL: test_urem_vec:
513 ; NEON7: @ %bb.0:
514 ; NEON7-NEXT: vmov.16 d16[0], r0
515 ; NEON7-NEXT: vldr d17, .LCPI4_0
516 ; NEON7-NEXT: vmov.16 d16[1], r1
517 ; NEON7-NEXT: vldr d19, .LCPI4_3
518 ; NEON7-NEXT: vmov.16 d16[2], r2
519 ; NEON7-NEXT: vsub.i16 d16, d16, d17
520 ; NEON7-NEXT: vldr d17, .LCPI4_1
521 ; NEON7-NEXT: vmul.i16 d16, d16, d17
522 ; NEON7-NEXT: vldr d17, .LCPI4_2
523 ; NEON7-NEXT: vneg.s16 d17, d17
524 ; NEON7-NEXT: vshl.i16 d18, d16, #1
525 ; NEON7-NEXT: vbic.i16 d16, #0xf800
526 ; NEON7-NEXT: vshl.u16 d16, d16, d17
527 ; NEON7-NEXT: vshl.u16 d17, d18, d19
528 ; NEON7-NEXT: vorr d16, d16, d17
529 ; NEON7-NEXT: vldr d17, .LCPI4_4
530 ; NEON7-NEXT: vbic.i16 d16, #0xf800
531 ; NEON7-NEXT: vcgt.u16 d16, d16, d17
532 ; NEON7-NEXT: vmov.u16 r0, d16[0]
533 ; NEON7-NEXT: vmov.u16 r1, d16[1]
534 ; NEON7-NEXT: vmov.u16 r2, d16[2]
535 ; NEON7-NEXT: bx lr
536 ; NEON7-NEXT: .p2align 3
537 ; NEON7-NEXT: @ %bb.1:
538 ; NEON7-NEXT: .LCPI4_0:
539 ; NEON7-NEXT: .short 0 @ 0x0
540 ; NEON7-NEXT: .short 1 @ 0x1
541 ; NEON7-NEXT: .short 2 @ 0x2
542 ; NEON7-NEXT: .zero 2
543 ; NEON7-NEXT: .LCPI4_1:
544 ; NEON7-NEXT: .short 683 @ 0x2ab
545 ; NEON7-NEXT: .short 1463 @ 0x5b7
546 ; NEON7-NEXT: .short 819 @ 0x333
547 ; NEON7-NEXT: .zero 2
548 ; NEON7-NEXT: .LCPI4_2:
549 ; NEON7-NEXT: .short 1 @ 0x1
550 ; NEON7-NEXT: .short 0 @ 0x0
551 ; NEON7-NEXT: .short 0 @ 0x0
552 ; NEON7-NEXT: .short 0 @ 0x0
553 ; NEON7-NEXT: .LCPI4_3:
554 ; NEON7-NEXT: .short 9 @ 0x9
555 ; NEON7-NEXT: .short 10 @ 0xa
556 ; NEON7-NEXT: .short 10 @ 0xa
557 ; NEON7-NEXT: .short 10 @ 0xa
558 ; NEON7-NEXT: .LCPI4_4:
559 ; NEON7-NEXT: .short 341 @ 0x155
560 ; NEON7-NEXT: .short 292 @ 0x124
561 ; NEON7-NEXT: .short 1 @ 0x1
562 ; NEON7-NEXT: .short 0 @ 0x0
563 ;
564 ; NEON8-LABEL: test_urem_vec:
565 ; NEON8: @ %bb.0:
566 ; NEON8-NEXT: vmov.16 d16[0], r0
567 ; NEON8-NEXT: vldr d17, .LCPI4_0
568 ; NEON8-NEXT: vmov.16 d16[1], r1
569 ; NEON8-NEXT: vldr d19, .LCPI4_3
570 ; NEON8-NEXT: vmov.16 d16[2], r2
571 ; NEON8-NEXT: vsub.i16 d16, d16, d17
572 ; NEON8-NEXT: vldr d17, .LCPI4_1
573 ; NEON8-NEXT: vmul.i16 d16, d16, d17
574 ; NEON8-NEXT: vldr d17, .LCPI4_2
575 ; NEON8-NEXT: vneg.s16 d17, d17
576 ; NEON8-NEXT: vshl.i16 d18, d16, #1
577 ; NEON8-NEXT: vbic.i16 d16, #0xf800
578 ; NEON8-NEXT: vshl.u16 d16, d16, d17
579 ; NEON8-NEXT: vshl.u16 d17, d18, d19
580 ; NEON8-NEXT: vorr d16, d16, d17
581 ; NEON8-NEXT: vldr d17, .LCPI4_4
582 ; NEON8-NEXT: vbic.i16 d16, #0xf800
583 ; NEON8-NEXT: vcgt.u16 d16, d16, d17
584 ; NEON8-NEXT: vmov.u16 r0, d16[0]
585 ; NEON8-NEXT: vmov.u16 r1, d16[1]
586 ; NEON8-NEXT: vmov.u16 r2, d16[2]
587 ; NEON8-NEXT: bx lr
588 ; NEON8-NEXT: .p2align 3
589 ; NEON8-NEXT: @ %bb.1:
590 ; NEON8-NEXT: .LCPI4_0:
591 ; NEON8-NEXT: .short 0 @ 0x0
592 ; NEON8-NEXT: .short 1 @ 0x1
593 ; NEON8-NEXT: .short 2 @ 0x2
594 ; NEON8-NEXT: .zero 2
595 ; NEON8-NEXT: .LCPI4_1:
596 ; NEON8-NEXT: .short 683 @ 0x2ab
597 ; NEON8-NEXT: .short 1463 @ 0x5b7
598 ; NEON8-NEXT: .short 819 @ 0x333
599 ; NEON8-NEXT: .zero 2
600 ; NEON8-NEXT: .LCPI4_2:
601 ; NEON8-NEXT: .short 1 @ 0x1
602 ; NEON8-NEXT: .short 0 @ 0x0
603 ; NEON8-NEXT: .short 0 @ 0x0
604 ; NEON8-NEXT: .short 0 @ 0x0
605 ; NEON8-NEXT: .LCPI4_3:
606 ; NEON8-NEXT: .short 9 @ 0x9
607 ; NEON8-NEXT: .short 10 @ 0xa
608 ; NEON8-NEXT: .short 10 @ 0xa
609 ; NEON8-NEXT: .short 10 @ 0xa
610 ; NEON8-NEXT: .LCPI4_4:
611 ; NEON8-NEXT: .short 341 @ 0x155
612 ; NEON8-NEXT: .short 292 @ 0x124
613 ; NEON8-NEXT: .short 1 @ 0x1
614 ; NEON8-NEXT: .short 0 @ 0x0
615 %urem = urem <3 x i11> %X, <i11 6, i11 7, i11 -5>
616 %cmp = icmp ne <3 x i11> %urem, <i11 0, i11 1, i11 2>
617 ret <3 x i1> %cmp
618 }
620 define i1 @test_urem_larger(i63 %X) nounwind {
621 ; ARM5-LABEL: test_urem_larger:
622 ; ARM5: @ %bb.0:
623 ; ARM5-NEXT: push {r4, lr}
624 ; ARM5-NEXT: ldr r12, .LCPI5_0
625 ; ARM5-NEXT: ldr r2, .LCPI5_1
626 ; ARM5-NEXT: umull r3, lr, r0, r12
627 ; ARM5-NEXT: mla r4, r0, r2, lr
628 ; ARM5-NEXT: mla r0, r1, r12, r4
629 ; ARM5-NEXT: bic r0, r0, #-2147483648
630 ; ARM5-NEXT: lsrs r0, r0, #1
631 ; ARM5-NEXT: rrx r1, r3
632 ; ARM5-NEXT: orr r0, r0, r3, lsl #30
633 ; ARM5-NEXT: ldr r3, .LCPI5_2
634 ; ARM5-NEXT: bic r2, r0, #-2147483648
635 ; ARM5-NEXT: mov r0, #0
636 ; ARM5-NEXT: subs r1, r1, r3
637 ; ARM5-NEXT: sbcs r1, r2, #1
638 ; ARM5-NEXT: movlo r0, #1
639 ; ARM5-NEXT: pop {r4, pc}
640 ; ARM5-NEXT: .p2align 2
641 ; ARM5-NEXT: @ %bb.1:
642 ; ARM5-NEXT: .LCPI5_0:
643 ; ARM5-NEXT: .long 3456474841 @ 0xce059ed9
644 ; ARM5-NEXT: .LCPI5_1:
645 ; ARM5-NEXT: .long 790204738 @ 0x2f199142
646 ; ARM5-NEXT: .LCPI5_2:
647 ; ARM5-NEXT: .long 3175964122 @ 0xbd4d5dda
648 ;
649 ; ARM6-LABEL: test_urem_larger:
650 ; ARM6: @ %bb.0:
651 ; ARM6-NEXT: push {r11, lr}
652 ; ARM6-NEXT: ldr r12, .LCPI5_0
653 ; ARM6-NEXT: ldr r2, .LCPI5_1
654 ; ARM6-NEXT: umull r3, lr, r0, r12
655 ; ARM6-NEXT: mla r0, r0, r2, lr
656 ; ARM6-NEXT: mla r0, r1, r12, r0
657 ; ARM6-NEXT: bic r0, r0, #-2147483648
658 ; ARM6-NEXT: lsrs r0, r0, #1
659 ; ARM6-NEXT: rrx r1, r3
660 ; ARM6-NEXT: orr r0, r0, r3, lsl #30
661 ; ARM6-NEXT: ldr r3, .LCPI5_2
662 ; ARM6-NEXT: bic r2, r0, #-2147483648
663 ; ARM6-NEXT: mov r0, #0
664 ; ARM6-NEXT: subs r1, r1, r3
665 ; ARM6-NEXT: sbcs r1, r2, #1
666 ; ARM6-NEXT: movlo r0, #1
667 ; ARM6-NEXT: pop {r11, pc}
668 ; ARM6-NEXT: .p2align 2
669 ; ARM6-NEXT: @ %bb.1:
670 ; ARM6-NEXT: .LCPI5_0:
671 ; ARM6-NEXT: .long 3456474841 @ 0xce059ed9
672 ; ARM6-NEXT: .LCPI5_1:
673 ; ARM6-NEXT: .long 790204738 @ 0x2f199142
674 ; ARM6-NEXT: .LCPI5_2:
675 ; ARM6-NEXT: .long 3175964122 @ 0xbd4d5dda
676 ;
677 ; ARM7-LABEL: test_urem_larger:
678 ; ARM7: @ %bb.0:
679 ; ARM7-NEXT: push {r11, lr}
680 ; ARM7-NEXT: movw r12, #40665
681 ; ARM7-NEXT: movw r2, #37186
682 ; ARM7-NEXT: movt r12, #52741
683 ; ARM7-NEXT: movt r2, #12057
684 ; ARM7-NEXT: umull r3, lr, r0, r12
685 ; ARM7-NEXT: mla r0, r0, r2, lr
686 ; ARM7-NEXT: mla r0, r1, r12, r0
687 ; ARM7-NEXT: bic r0, r0, #-2147483648
688 ; ARM7-NEXT: lsrs r0, r0, #1
689 ; ARM7-NEXT: rrx r1, r3
690 ; ARM7-NEXT: orr r0, r0, r3, lsl #30
691 ; ARM7-NEXT: movw r3, #24026
692 ; ARM7-NEXT: bic r2, r0, #-2147483648
693 ; ARM7-NEXT: movt r3, #48461
694 ; ARM7-NEXT: subs r1, r1, r3
695 ; ARM7-NEXT: mov r0, #0
696 ; ARM7-NEXT: sbcs r1, r2, #1
697 ; ARM7-NEXT: movwlo r0, #1
698 ; ARM7-NEXT: pop {r11, pc}
699 ;
700 ; ARM8-LABEL: test_urem_larger:
701 ; ARM8: @ %bb.0:
702 ; ARM8-NEXT: push {r11, lr}
703 ; ARM8-NEXT: movw r12, #40665
704 ; ARM8-NEXT: movw r2, #37186
705 ; ARM8-NEXT: movt r12, #52741
706 ; ARM8-NEXT: movt r2, #12057
707 ; ARM8-NEXT: umull r3, lr, r0, r12
708 ; ARM8-NEXT: mla r0, r0, r2, lr
709 ; ARM8-NEXT: mla r0, r1, r12, r0
710 ; ARM8-NEXT: bic r0, r0, #-2147483648
711 ; ARM8-NEXT: lsrs r0, r0, #1
712 ; ARM8-NEXT: rrx r1, r3
713 ; ARM8-NEXT: orr r0, r0, r3, lsl #30
714 ; ARM8-NEXT: movw r3, #24026
715 ; ARM8-NEXT: bic r2, r0, #-2147483648
716 ; ARM8-NEXT: movt r3, #48461
717 ; ARM8-NEXT: subs r1, r1, r3
718 ; ARM8-NEXT: mov r0, #0
719 ; ARM8-NEXT: sbcs r1, r2, #1
720 ; ARM8-NEXT: movwlo r0, #1
721 ; ARM8-NEXT: pop {r11, pc}
722 ;
723 ; NEON7-LABEL: test_urem_larger:
724 ; NEON7: @ %bb.0:
725 ; NEON7-NEXT: push {r11, lr}
726 ; NEON7-NEXT: movw r12, #40665
727 ; NEON7-NEXT: movw r2, #37186
728 ; NEON7-NEXT: movt r12, #52741
729 ; NEON7-NEXT: movt r2, #12057
730 ; NEON7-NEXT: umull r3, lr, r0, r12
731 ; NEON7-NEXT: mla r0, r0, r2, lr
732 ; NEON7-NEXT: mla r0, r1, r12, r0
733 ; NEON7-NEXT: bic r0, r0, #-2147483648
734 ; NEON7-NEXT: lsrs r0, r0, #1
735 ; NEON7-NEXT: rrx r1, r3
736 ; NEON7-NEXT: orr r0, r0, r3, lsl #30
737 ; NEON7-NEXT: movw r3, #24026
738 ; NEON7-NEXT: bic r2, r0, #-2147483648
739 ; NEON7-NEXT: movt r3, #48461
740 ; NEON7-NEXT: subs r1, r1, r3
741 ; NEON7-NEXT: mov r0, #0
742 ; NEON7-NEXT: sbcs r1, r2, #1
743 ; NEON7-NEXT: movwlo r0, #1
744 ; NEON7-NEXT: pop {r11, pc}
745 ;
746 ; NEON8-LABEL: test_urem_larger:
747 ; NEON8: @ %bb.0:
748 ; NEON8-NEXT: push {r11, lr}
749 ; NEON8-NEXT: movw r12, #40665
750 ; NEON8-NEXT: movw r2, #37186
751 ; NEON8-NEXT: movt r12, #52741
752 ; NEON8-NEXT: movt r2, #12057
753 ; NEON8-NEXT: umull r3, lr, r0, r12
754 ; NEON8-NEXT: mla r0, r0, r2, lr
755 ; NEON8-NEXT: mla r0, r1, r12, r0
756 ; NEON8-NEXT: bic r0, r0, #-2147483648
757 ; NEON8-NEXT: lsrs r0, r0, #1
758 ; NEON8-NEXT: rrx r1, r3
759 ; NEON8-NEXT: orr r0, r0, r3, lsl #30
760 ; NEON8-NEXT: movw r3, #24026
761 ; NEON8-NEXT: bic r2, r0, #-2147483648
762 ; NEON8-NEXT: movt r3, #48461
763 ; NEON8-NEXT: subs r1, r1, r3
764 ; NEON8-NEXT: mov r0, #0
765 ; NEON8-NEXT: sbcs r1, r2, #1
766 ; NEON8-NEXT: movwlo r0, #1
767 ; NEON8-NEXT: pop {r11, pc}
768 %urem = urem i63 %X, 1234567890
769 %cmp = icmp eq i63 %urem, 0
770 ret i1 %cmp
771 }