| blob | 70c569e4f4781a15fd249f0e8a40449e40d49582 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=arm-none-eabi -mattr=-neon | FileCheck %s --check-prefix=CHECK
4 declare half @llvm.vector.reduce.fmin.v4f16(<4 x half>)
5 declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)
6 declare double @llvm.vector.reduce.fmin.v2f64(<2 x double>)
7 declare fp128 @llvm.vector.reduce.fmin.v2f128(<2 x fp128>)
9 define half @test_v4f16(<4 x half> %a) nounwind {
10 ; CHECK-LABEL: test_v4f16:
11 ; CHECK: @ %bb.0:
12 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
13 ; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
14 ; CHECK-NEXT: mov r9, #255
15 ; CHECK-NEXT: mov r8, r3
16 ; CHECK-NEXT: orr r9, r9, #65280
17 ; CHECK-NEXT: mov r6, r2
18 ; CHECK-NEXT: and r0, r0, r9
19 ; CHECK-NEXT: mov r5, r1
20 ; CHECK-NEXT: bl __aeabi_h2f
21 ; CHECK-NEXT: mov r7, r0
22 ; CHECK-NEXT: and r0, r5, r9
23 ; CHECK-NEXT: bl __aeabi_h2f
24 ; CHECK-NEXT: mov r5, r0
25 ; CHECK-NEXT: mov r0, r7
26 ; CHECK-NEXT: mov r1, r5
27 ; CHECK-NEXT: bl __aeabi_fcmplt
28 ; CHECK-NEXT: mov r4, r0
29 ; CHECK-NEXT: and r0, r6, r9
30 ; CHECK-NEXT: bl __aeabi_h2f
31 ; CHECK-NEXT: cmp r4, #0
32 ; CHECK-NEXT: mov r6, r0
33 ; CHECK-NEXT: movne r5, r7
34 ; CHECK-NEXT: mov r1, r6
35 ; CHECK-NEXT: mov r0, r5
36 ; CHECK-NEXT: bl __aeabi_fcmplt
37 ; CHECK-NEXT: cmp r0, #0
38 ; CHECK-NEXT: and r0, r8, r9
39 ; CHECK-NEXT: moveq r5, r6
40 ; CHECK-NEXT: bl __aeabi_h2f
41 ; CHECK-NEXT: mov r4, r0
42 ; CHECK-NEXT: mov r0, r5
43 ; CHECK-NEXT: mov r1, r4
44 ; CHECK-NEXT: bl __aeabi_fcmplt
45 ; CHECK-NEXT: cmp r0, #0
46 ; CHECK-NEXT: moveq r5, r4
47 ; CHECK-NEXT: mov r0, r5
48 ; CHECK-NEXT: bl __aeabi_f2h
49 ; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, lr}
50 ; CHECK-NEXT: mov pc, lr
51 %b = call fast half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a)
52 ret half %b
53 }
55 define float @test_v4f32(<4 x float> %a) nounwind {
56 ; CHECK-LABEL: test_v4f32:
57 ; CHECK: @ %bb.0:
58 ; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
59 ; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
60 ; CHECK-NEXT: mov r4, r3
61 ; CHECK-NEXT: mov r6, r2
62 ; CHECK-NEXT: mov r5, r1
63 ; CHECK-NEXT: mov r7, r0
64 ; CHECK-NEXT: bl __aeabi_fcmplt
65 ; CHECK-NEXT: cmp r0, #0
66 ; CHECK-NEXT: mov r1, r6
67 ; CHECK-NEXT: movne r5, r7
68 ; CHECK-NEXT: mov r0, r5
69 ; CHECK-NEXT: bl __aeabi_fcmplt
70 ; CHECK-NEXT: cmp r0, #0
71 ; CHECK-NEXT: mov r1, r4
72 ; CHECK-NEXT: moveq r5, r6
73 ; CHECK-NEXT: mov r0, r5
74 ; CHECK-NEXT: bl __aeabi_fcmplt
75 ; CHECK-NEXT: cmp r0, #0
76 ; CHECK-NEXT: moveq r5, r4
77 ; CHECK-NEXT: mov r0, r5
78 ; CHECK-NEXT: pop {r4, r5, r6, r7, r11, lr}
79 ; CHECK-NEXT: mov pc, lr
80 %b = call fast float @llvm.vector.reduce.fmin.v4f32(<4 x float> %a)
81 ret float %b
82 }
84 define double @test_v2f64(<2 x double> %a) nounwind {
85 ; CHECK-LABEL: test_v2f64:
86 ; CHECK: @ %bb.0:
87 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
88 ; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
89 ; CHECK-NEXT: mov r4, r3
90 ; CHECK-NEXT: mov r6, r2
91 ; CHECK-NEXT: mov r8, r1
92 ; CHECK-NEXT: mov r7, r0
93 ; CHECK-NEXT: bl __aeabi_dcmplt
94 ; CHECK-NEXT: cmp r0, #0
95 ; CHECK-NEXT: mov r5, r6
96 ; CHECK-NEXT: mov r0, r7
97 ; CHECK-NEXT: mov r1, r8
98 ; CHECK-NEXT: mov r2, r6
99 ; CHECK-NEXT: mov r3, r4
100 ; CHECK-NEXT: movne r5, r7
101 ; CHECK-NEXT: bl __aeabi_dcmplt
102 ; CHECK-NEXT: cmp r0, #0
103 ; CHECK-NEXT: mov r0, r5
104 ; CHECK-NEXT: movne r4, r8
105 ; CHECK-NEXT: mov r1, r4
106 ; CHECK-NEXT: pop {r4, r5, r6, r7, r8, lr}
107 ; CHECK-NEXT: mov pc, lr
108 %b = call fast double @llvm.vector.reduce.fmin.v2f64(<2 x double> %a)
109 ret double %b
110 }
112 define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
113 ; CHECK-LABEL: test_v2f128:
114 ; CHECK: @ %bb.0:
115 ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
116 ; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
117 ; CHECK-NEXT: .pad #28
118 ; CHECK-NEXT: sub sp, sp, #28
119 ; CHECK-NEXT: ldr r5, [sp, #76]
120 ; CHECK-NEXT: mov r8, r3
121 ; CHECK-NEXT: ldr r6, [sp, #72]
122 ; CHECK-NEXT: mov r9, r2
123 ; CHECK-NEXT: ldr r4, [sp, #68]
124 ; CHECK-NEXT: mov r10, r1
125 ; CHECK-NEXT: ldr r7, [sp, #64]
126 ; CHECK-NEXT: mov r11, r0
127 ; CHECK-NEXT: str r5, [sp, #12]
128 ; CHECK-NEXT: str r6, [sp, #8]
129 ; CHECK-NEXT: str r4, [sp, #4]
130 ; CHECK-NEXT: str r7, [sp]
131 ; CHECK-NEXT: bl __lttf2
132 ; CHECK-NEXT: str r0, [sp, #24] @ 4-byte Spill
133 ; CHECK-NEXT: mov r0, r11
134 ; CHECK-NEXT: mov r1, r10
135 ; CHECK-NEXT: mov r2, r9
136 ; CHECK-NEXT: mov r3, r8
137 ; CHECK-NEXT: str r7, [sp]
138 ; CHECK-NEXT: stmib sp, {r4, r6}
139 ; CHECK-NEXT: str r5, [sp, #12]
140 ; CHECK-NEXT: bl __lttf2
141 ; CHECK-NEXT: str r0, [sp, #20] @ 4-byte Spill
142 ; CHECK-NEXT: mov r0, r11
143 ; CHECK-NEXT: mov r1, r10
144 ; CHECK-NEXT: mov r2, r9
145 ; CHECK-NEXT: mov r3, r8
146 ; CHECK-NEXT: str r7, [sp]
147 ; CHECK-NEXT: stmib sp, {r4, r6}
148 ; CHECK-NEXT: str r5, [sp, #12]
149 ; CHECK-NEXT: bl __lttf2
150 ; CHECK-NEXT: cmp r0, #0
151 ; CHECK-NEXT: ldr r0, [sp, #20] @ 4-byte Reload
152 ; CHECK-NEXT: str r7, [sp]
153 ; CHECK-NEXT: movmi r7, r11
154 ; CHECK-NEXT: cmp r0, #0
155 ; CHECK-NEXT: ldr r0, [sp, #24] @ 4-byte Reload
156 ; CHECK-NEXT: stmib sp, {r4, r6}
157 ; CHECK-NEXT: movmi r4, r10
158 ; CHECK-NEXT: cmp r0, #0
159 ; CHECK-NEXT: mov r0, r11
160 ; CHECK-NEXT: mov r1, r10
161 ; CHECK-NEXT: mov r2, r9
162 ; CHECK-NEXT: mov r3, r8
163 ; CHECK-NEXT: str r5, [sp, #12]
164 ; CHECK-NEXT: movmi r6, r9
165 ; CHECK-NEXT: bl __lttf2
166 ; CHECK-NEXT: cmp r0, #0
167 ; CHECK-NEXT: mov r0, r7
168 ; CHECK-NEXT: movmi r5, r8
169 ; CHECK-NEXT: mov r1, r4
170 ; CHECK-NEXT: mov r2, r6
171 ; CHECK-NEXT: mov r3, r5
172 ; CHECK-NEXT: add sp, sp, #28
173 ; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, lr}
174 ; CHECK-NEXT: mov pc, lr
175 %b = call fast fp128 @llvm.vector.reduce.fmin.v2f128(<2 x fp128> %a)
176 ret fp128 %b
177 }