1 # RUN: llc -mtriple=ppc64-- -run-pass scavenger-test -verify-machineinstrs -o - %s | FileCheck %s
3 # CHECK-LABEL: name: noscav0
5 tracksRegLiveness: true
8 ; CHECK: [[REG0:\$r[0-9]+]] = LI 42
9 ; CHECK-NEXT: NOP implicit killed [[REG0]]
13 ; CHECK: [[REG1:\$r[0-9]+]] = LI 42
15 ; CHECK-NEXT: NOP implicit [[REG1]]
17 ; CHECK-NEXT: NOP implicit killed [[REG1]]
24 ; CHECK: [[REG2:\$r[0-9]+]] = LI 42
25 ; CHECK-NEXT: NOP implicit [[REG2]]
39 ; CHECK-NOT: $x0 = LI 42
40 ; CHECK-NOT: $x1 = LI 42
41 ; CHECK-NOT: $x2 = LI 42
42 ; CHECK-NOT: $x3 = LI 42
43 ; CHECK-NOT: $x4 = LI 42
44 ; CHECK-NOT: $x5 = LI 42
45 ; CHECK-NOT: $x27 = LI 42
46 ; CHECK-NOT: $x28 = LI 42
47 ; CHECK-NOT: $x29 = LI 42
48 ; CHECK-NOT: $x30 = LI 42
49 ; CHECK: [[REG3:\$r[0-9]+]] = LI 42
50 ; CHECK-NEXT: $x5 = IMPLICIT_DEF
51 ; CHECK-NEXT: NOP implicit killed [[REG2]]
52 ; CHECK-NEXT: NOP implicit killed [[REG3]]
70 # CHECK-LABEL: name: scav0
72 tracksRegLiveness: true
74 # variable-sized object should be a reason to reserve an emergency spillslot
76 - { id: 0, type: variable-sized, offset: -32, alignment: 1 }
111 ; CHECK: STD killed [[SPILLEDREG:\$x[0-9]+]]
112 ; CHECK: [[SPILLEDREG]] = LI8 42
113 ; CHECK: NOP implicit killed [[SPILLEDREG]]
114 ; CHECK: [[SPILLEDREG]] = LD
151 # Check for bug where we would refuse to spill before the first instruction in a
153 # CHECK-LABEL: name: spill_at_begin
156 # CHECK: STD killed [[REG:\$x[0-9]+]]{{.*}}(store (s64) into %stack.{{[0-9]+}})
157 # CHECK: [[REG]] = LIS8 0
158 # CHECK: [[REG]] = ORI8 killed [[REG]], 48
159 # CHECK: NOP implicit killed [[REG]]
160 # CHECK: [[REG]] = LD{{.*}}(load (s64) from %stack.{{[0-9]+}})
162 tracksRegLiveness: true
164 # variable-sized object should be a reason to reserve an emergency spillslot
165 # in the RegScavenger
166 - { id: 0, type: variable-sized, offset: -32, alignment: 1 }
169 liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $x29, $x30, $x31
171 %1 : g8rc = ORI8 %0, 48