llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-wave-address.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -march=amdgcn -mcpu=gfx1031 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE32 %s
   3 # RUN: llc -march=amdgcn -mcpu=gfx1031 -mattr=+wavefrontsize64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE64 %s
   4
   5 ---
   6 name: wave_address_s
   7 legalized: true
   8 regBankSelected: true
   9 tracksRegLiveness: true
  10 machineFunctionInfo:
  11   stackPtrOffsetReg: $sgpr32
  12 body: |
  13   bb.0:
  14     ; WAVE32-LABEL: name: wave_address_s
  15     ; WAVE32: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 $sgpr32, 5, implicit-def $scc
  16     ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_LSHR_B32_]]
  17     ; WAVE64-LABEL: name: wave_address_s
  18     ; WAVE64: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 $sgpr32, 6, implicit-def $scc
  19     ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_LSHR_B32_]]
  20     %0:sgpr(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr32
  21     S_ENDPGM 0, implicit %0
  22 ...
  23
  24 ---
  25 name: wave_address_v
  26 legalized: true
  27 regBankSelected: true
  28 tracksRegLiveness: true
  29 machineFunctionInfo:
  30   stackPtrOffsetReg: $sgpr32
  31 body: |
  32   bb.0:
  33     ; WAVE32-LABEL: name: wave_address_v
  34     ; WAVE32: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 5, $sgpr32, implicit $exec
  35     ; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_LSHRREV_B32_e64_]]
  36     ; WAVE64-LABEL: name: wave_address_v
  37     ; WAVE64: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec
  38     ; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_LSHRREV_B32_e64_]]
  39     %0:vgpr(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr32
  40     S_ENDPGM 0, implicit %0
  41 ...