llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=SI %s
   3 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=VI %s
   4 # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
   5 # RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
   6
   7 ---
   8 name: fabs_s32_ss
   9 legalized: true
  10 regBankSelected: true
  11 tracksRegLiveness: true
  12
  13 body: |
  14   bb.0:
  15     liveins: $sgpr0
  16     ; GCN-LABEL: name: fabs_s32_ss
  17     ; GCN: liveins: $sgpr0
  18     ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  19     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
  20     ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
  21     ; GCN: $sgpr0 = COPY [[S_AND_B32_]]
  22     ; SI-LABEL: name: fabs_s32_ss
  23     ; SI: liveins: $sgpr0
  24     ; SI-NEXT: {{  $}}
  25     ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  26     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
  27     ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
  28     ; SI-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
  29     ; VI-LABEL: name: fabs_s32_ss
  30     ; VI: liveins: $sgpr0
  31     ; VI-NEXT: {{  $}}
  32     ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  33     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
  34     ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
  35     ; VI-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
  36     ; GFX9-LABEL: name: fabs_s32_ss
  37     ; GFX9: liveins: $sgpr0
  38     ; GFX9-NEXT: {{  $}}
  39     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  40     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
  41     ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
  42     ; GFX9-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
  43     ; GFX10-LABEL: name: fabs_s32_ss
  44     ; GFX10: liveins: $sgpr0
  45     ; GFX10-NEXT: {{  $}}
  46     ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  47     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
  48     ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
  49     ; GFX10-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
  50     %0:sgpr(s32) = COPY $sgpr0
  51     %1:sgpr(s32) = G_FABS %0
  52     $sgpr0 = COPY %1
  53 ...
  54
  55 ---
  56 name: fabs_s32_vv
  57 legalized: true
  58 regBankSelected: true
  59 tracksRegLiveness: true
  60
  61 body: |
  62   bb.0:
  63     liveins: $vgpr0
  64     ; GCN-LABEL: name: fabs_s32_vv
  65     ; GCN: liveins: $vgpr0
  66     ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  67     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
  68     ; GCN: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
  69     ; GCN: $vgpr0 = COPY [[V_AND_B32_e32_]]
  70     ; SI-LABEL: name: fabs_s32_vv
  71     ; SI: liveins: $vgpr0
  72     ; SI-NEXT: {{  $}}
  73     ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  74     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
  75     ; SI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
  76     ; SI-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
  77     ; VI-LABEL: name: fabs_s32_vv
  78     ; VI: liveins: $vgpr0
  79     ; VI-NEXT: {{  $}}
  80     ; VI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  81     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
  82     ; VI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
  83     ; VI-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
  84     ; GFX9-LABEL: name: fabs_s32_vv
  85     ; GFX9: liveins: $vgpr0
  86     ; GFX9-NEXT: {{  $}}
  87     ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  88     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
  89     ; GFX9-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
  90     ; GFX9-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
  91     ; GFX10-LABEL: name: fabs_s32_vv
  92     ; GFX10: liveins: $vgpr0
  93     ; GFX10-NEXT: {{  $}}
  94     ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  95     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
  96     ; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
  97     ; GFX10-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
  98     %0:vgpr(s32) = COPY $vgpr0
  99     %1:vgpr(s32) = G_FABS %0
 100     $vgpr0 = COPY %1
 101 ...
 102
 103 ---
 104 name: fabs_s32_vs
 105 legalized: true
 106 regBankSelected: true
 107 tracksRegLiveness: true
 108
 109 body: |
 110   bb.0:
 111     liveins: $sgpr0
 112     ; GCN-LABEL: name: fabs_s32_vs
 113     ; GCN: liveins: $sgpr0
 114     ; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
 115     ; GCN: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]]
 116     ; GCN: $vgpr0 = COPY [[FABS]](s32)
 117     ; SI-LABEL: name: fabs_s32_vs
 118     ; SI: liveins: $sgpr0
 119     ; SI-NEXT: {{  $}}
 120     ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
 121     ; SI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]]
 122     ; SI-NEXT: $vgpr0 = COPY [[FABS]](s32)
 123     ; VI-LABEL: name: fabs_s32_vs
 124     ; VI: liveins: $sgpr0
 125     ; VI-NEXT: {{  $}}
 126     ; VI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
 127     ; VI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]]
 128     ; VI-NEXT: $vgpr0 = COPY [[FABS]](s32)
 129     ; GFX9-LABEL: name: fabs_s32_vs
 130     ; GFX9: liveins: $sgpr0
 131     ; GFX9-NEXT: {{  $}}
 132     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
 133     ; GFX9-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]]
 134     ; GFX9-NEXT: $vgpr0 = COPY [[FABS]](s32)
 135     ; GFX10-LABEL: name: fabs_s32_vs
 136     ; GFX10: liveins: $sgpr0
 137     ; GFX10-NEXT: {{  $}}
 138     ; GFX10-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
 139     ; GFX10-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s32) = G_FABS [[COPY]]
 140     ; GFX10-NEXT: $vgpr0 = COPY [[FABS]](s32)
 141     %0:sgpr(s32) = COPY $sgpr0
 142     %1:vgpr(s32) = G_FABS %0
 143     $vgpr0 = COPY %1
 144 ...
 145
 146 ---
 147 name: fabs_v2s16_ss
 148 legalized: true
 149 regBankSelected: true
 150 tracksRegLiveness: true
 151
 152 body: |
 153   bb.0:
 154     liveins: $sgpr0_sgpr1
 155     ; GCN-LABEL: name: fabs_v2s16_ss
 156     ; GCN: liveins: $sgpr0_sgpr1
 157     ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 158     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
 159     ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
 160     ; GCN: $sgpr0 = COPY [[S_AND_B32_]]
 161     ; SI-LABEL: name: fabs_v2s16_ss
 162     ; SI: liveins: $sgpr0_sgpr1
 163     ; SI-NEXT: {{  $}}
 164     ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 165     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
 166     ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
 167     ; SI-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
 168     ; VI-LABEL: name: fabs_v2s16_ss
 169     ; VI: liveins: $sgpr0_sgpr1
 170     ; VI-NEXT: {{  $}}
 171     ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 172     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
 173     ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
 174     ; VI-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
 175     ; GFX9-LABEL: name: fabs_v2s16_ss
 176     ; GFX9: liveins: $sgpr0_sgpr1
 177     ; GFX9-NEXT: {{  $}}
 178     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 179     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
 180     ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
 181     ; GFX9-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
 182     ; GFX10-LABEL: name: fabs_v2s16_ss
 183     ; GFX10: liveins: $sgpr0_sgpr1
 184     ; GFX10-NEXT: {{  $}}
 185     ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 186     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
 187     ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
 188     ; GFX10-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
 189     %0:sgpr(<2 x s16>) = COPY $sgpr0
 190     %1:sgpr(<2 x s16>) = G_FABS %0
 191     $sgpr0 = COPY %1
 192 ...
 193
 194 ---
 195 name: fabs_s16_ss
 196 legalized: true
 197 regBankSelected: true
 198 tracksRegLiveness: true
 199
 200 body: |
 201   bb.0:
 202     liveins: $sgpr0
 203     ; GCN-LABEL: name: fabs_s16_ss
 204     ; GCN: liveins: $sgpr0
 205     ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 206     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
 207     ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
 208     ; GCN: $sgpr0 = COPY [[S_AND_B32_]]
 209     ; SI-LABEL: name: fabs_s16_ss
 210     ; SI: liveins: $sgpr0
 211     ; SI-NEXT: {{  $}}
 212     ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 213     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
 214     ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
 215     ; SI-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
 216     ; VI-LABEL: name: fabs_s16_ss
 217     ; VI: liveins: $sgpr0
 218     ; VI-NEXT: {{  $}}
 219     ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 220     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
 221     ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
 222     ; VI-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
 223     ; GFX9-LABEL: name: fabs_s16_ss
 224     ; GFX9: liveins: $sgpr0
 225     ; GFX9-NEXT: {{  $}}
 226     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 227     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
 228     ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
 229     ; GFX9-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
 230     ; GFX10-LABEL: name: fabs_s16_ss
 231     ; GFX10: liveins: $sgpr0
 232     ; GFX10-NEXT: {{  $}}
 233     ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 234     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
 235     ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
 236     ; GFX10-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
 237     %0:sgpr(s32) = COPY $sgpr0
 238     %1:sgpr(s16) = G_TRUNC %0
 239     %2:sgpr(s16) = G_FABS %1
 240     %3:sgpr(s32) = G_ANYEXT %2
 241     $sgpr0 = COPY %3
 242 ...
 243
 244 ---
 245 name: fabs_s16_vv
 246 legalized: true
 247 regBankSelected: true
 248 tracksRegLiveness: true
 249
 250 body: |
 251   bb.0:
 252     liveins: $vgpr0
 253     ; GCN-LABEL: name: fabs_s16_vv
 254     ; GCN: liveins: $vgpr0
 255     ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 256     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
 257     ; GCN: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
 258     ; GCN: $vgpr0 = COPY [[V_AND_B32_e32_]]
 259     ; SI-LABEL: name: fabs_s16_vv
 260     ; SI: liveins: $vgpr0
 261     ; SI-NEXT: {{  $}}
 262     ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 263     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
 264     ; SI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
 265     ; SI-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
 266     ; VI-LABEL: name: fabs_s16_vv
 267     ; VI: liveins: $vgpr0
 268     ; VI-NEXT: {{  $}}
 269     ; VI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 270     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
 271     ; VI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
 272     ; VI-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
 273     ; GFX9-LABEL: name: fabs_s16_vv
 274     ; GFX9: liveins: $vgpr0
 275     ; GFX9-NEXT: {{  $}}
 276     ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 277     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
 278     ; GFX9-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
 279     ; GFX9-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
 280     ; GFX10-LABEL: name: fabs_s16_vv
 281     ; GFX10: liveins: $vgpr0
 282     ; GFX10-NEXT: {{  $}}
 283     ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 284     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32767
 285     ; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
 286     ; GFX10-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
 287     %0:vgpr(s32) = COPY $vgpr0
 288     %1:vgpr(s16) = G_TRUNC %0
 289     %2:vgpr(s16) = G_FABS %1
 290     %3:vgpr(s32) = G_ANYEXT %2
 291     $vgpr0 = COPY %3
 292 ...
 293
 294 ---
 295 name: fabs_s16_vs
 296 legalized: true
 297 regBankSelected: true
 298 tracksRegLiveness: true
 299
 300 body: |
 301   bb.0:
 302     liveins: $sgpr0
 303
 304     ; GCN-LABEL: name: fabs_s16_vs
 305     ; GCN: liveins: $sgpr0
 306     ; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
 307     ; GCN: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
 308     ; GCN: [[FABS:%[0-9]+]]:vgpr_32(s16) = G_FABS [[TRUNC]]
 309     ; GCN: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]](s16)
 310     ; GCN: $vgpr0 = COPY [[COPY1]](s32)
 311     ; SI-LABEL: name: fabs_s16_vs
 312     ; SI: liveins: $sgpr0
 313     ; SI-NEXT: {{  $}}
 314     ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
 315     ; SI-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
 316     ; SI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s16) = G_FABS [[TRUNC]]
 317     ; SI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]](s16)
 318     ; SI-NEXT: $vgpr0 = COPY [[COPY1]](s32)
 319     ; VI-LABEL: name: fabs_s16_vs
 320     ; VI: liveins: $sgpr0
 321     ; VI-NEXT: {{  $}}
 322     ; VI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
 323     ; VI-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
 324     ; VI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s16) = G_FABS [[TRUNC]]
 325     ; VI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]](s16)
 326     ; VI-NEXT: $vgpr0 = COPY [[COPY1]](s32)
 327     ; GFX9-LABEL: name: fabs_s16_vs
 328     ; GFX9: liveins: $sgpr0
 329     ; GFX9-NEXT: {{  $}}
 330     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
 331     ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
 332     ; GFX9-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s16) = G_FABS [[TRUNC]]
 333     ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]](s16)
 334     ; GFX9-NEXT: $vgpr0 = COPY [[COPY1]](s32)
 335     ; GFX10-LABEL: name: fabs_s16_vs
 336     ; GFX10: liveins: $sgpr0
 337     ; GFX10-NEXT: {{  $}}
 338     ; GFX10-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
 339     ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
 340     ; GFX10-NEXT: [[FABS:%[0-9]+]]:vgpr_32(s16) = G_FABS [[TRUNC]]
 341     ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]](s16)
 342     ; GFX10-NEXT: $vgpr0 = COPY [[COPY1]](s32)
 343     %0:sgpr(s32) = COPY $sgpr0
 344     %1:sgpr(s16) = G_TRUNC %0
 345     %2:vgpr(s16) = G_FABS %1
 346     %3:vgpr(s32) = G_ANYEXT %2
 347     $vgpr0 = COPY %3
 348 ...
 349
 350 ---
 351 name: fabs_v2s16_vv
 352 legalized: true
 353 regBankSelected: true
 354 tracksRegLiveness: true
 355
 356 body: |
 357   bb.0:
 358     liveins: $vgpr0
 359     ; GCN-LABEL: name: fabs_v2s16_vv
 360     ; GCN: liveins: $vgpr0
 361     ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 362     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
 363     ; GCN: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
 364     ; GCN: $vgpr0 = COPY [[V_AND_B32_e32_]]
 365     ; SI-LABEL: name: fabs_v2s16_vv
 366     ; SI: liveins: $vgpr0
 367     ; SI-NEXT: {{  $}}
 368     ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 369     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
 370     ; SI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
 371     ; SI-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
 372     ; VI-LABEL: name: fabs_v2s16_vv
 373     ; VI: liveins: $vgpr0
 374     ; VI-NEXT: {{  $}}
 375     ; VI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 376     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
 377     ; VI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
 378     ; VI-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
 379     ; GFX9-LABEL: name: fabs_v2s16_vv
 380     ; GFX9: liveins: $vgpr0
 381     ; GFX9-NEXT: {{  $}}
 382     ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 383     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
 384     ; GFX9-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
 385     ; GFX9-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
 386     ; GFX10-LABEL: name: fabs_v2s16_vv
 387     ; GFX10: liveins: $vgpr0
 388     ; GFX10-NEXT: {{  $}}
 389     ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 390     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147450879
 391     ; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
 392     ; GFX10-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
 393     %0:vgpr(<2 x s16>) = COPY $vgpr0
 394     %1:vgpr(<2 x s16>) = G_FABS %0
 395     $vgpr0 = COPY %1
 396 ...
 397
 398 ---
 399 name: fabs_v2s16_vs
 400 legalized: true
 401 regBankSelected: true
 402 tracksRegLiveness: true
 403
 404 body: |
 405   bb.0:
 406     liveins: $sgpr0
 407     ; GCN-LABEL: name: fabs_v2s16_vs
 408     ; GCN: liveins: $sgpr0
 409     ; GCN: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
 410     ; GCN: [[FABS:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FABS [[COPY]]
 411     ; GCN: $vgpr0 = COPY [[FABS]](<2 x s16>)
 412     ; SI-LABEL: name: fabs_v2s16_vs
 413     ; SI: liveins: $sgpr0
 414     ; SI-NEXT: {{  $}}
 415     ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
 416     ; SI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FABS [[COPY]]
 417     ; SI-NEXT: $vgpr0 = COPY [[FABS]](<2 x s16>)
 418     ; VI-LABEL: name: fabs_v2s16_vs
 419     ; VI: liveins: $sgpr0
 420     ; VI-NEXT: {{  $}}
 421     ; VI-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
 422     ; VI-NEXT: [[FABS:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FABS [[COPY]]
 423     ; VI-NEXT: $vgpr0 = COPY [[FABS]](<2 x s16>)
 424     ; GFX9-LABEL: name: fabs_v2s16_vs
 425     ; GFX9: liveins: $sgpr0
 426     ; GFX9-NEXT: {{  $}}
 427     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
 428     ; GFX9-NEXT: [[FABS:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FABS [[COPY]]
 429     ; GFX9-NEXT: $vgpr0 = COPY [[FABS]](<2 x s16>)
 430     ; GFX10-LABEL: name: fabs_v2s16_vs
 431     ; GFX10: liveins: $sgpr0
 432     ; GFX10-NEXT: {{  $}}
 433     ; GFX10-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
 434     ; GFX10-NEXT: [[FABS:%[0-9]+]]:vgpr_32(<2 x s16>) = G_FABS [[COPY]]
 435     ; GFX10-NEXT: $vgpr0 = COPY [[FABS]](<2 x s16>)
 436     %0:sgpr(<2 x s16>) = COPY $sgpr0
 437     %1:vgpr(<2 x s16>) = G_FABS %0
 438     $vgpr0 = COPY %1
 439 ...
 440
 441 ---
 442 name: fabs_s64_ss
 443 legalized: true
 444 regBankSelected: true
 445 tracksRegLiveness: true
 446
 447 body: |
 448   bb.0:
 449     liveins: $sgpr0_sgpr1
 450     ; GCN-LABEL: name: fabs_s64_ss
 451     ; GCN: liveins: $sgpr0_sgpr1
 452     ; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 453     ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
 454     ; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
 455     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 456     ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
 457     ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
 458     ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 459     ; SI-LABEL: name: fabs_s64_ss
 460     ; SI: liveins: $sgpr0_sgpr1
 461     ; SI-NEXT: {{  $}}
 462     ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 463     ; SI-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
 464     ; SI-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
 465     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 466     ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
 467     ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
 468     ; SI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 469     ; VI-LABEL: name: fabs_s64_ss
 470     ; VI: liveins: $sgpr0_sgpr1
 471     ; VI-NEXT: {{  $}}
 472     ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 473     ; VI-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
 474     ; VI-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
 475     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 476     ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
 477     ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
 478     ; VI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 479     ; GFX9-LABEL: name: fabs_s64_ss
 480     ; GFX9: liveins: $sgpr0_sgpr1
 481     ; GFX9-NEXT: {{  $}}
 482     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 483     ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
 484     ; GFX9-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
 485     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 486     ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
 487     ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
 488     ; GFX9-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 489     ; GFX10-LABEL: name: fabs_s64_ss
 490     ; GFX10: liveins: $sgpr0_sgpr1
 491     ; GFX10-NEXT: {{  $}}
 492     ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 493     ; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
 494     ; GFX10-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
 495     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 496     ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
 497     ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
 498     ; GFX10-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 499     %0:sgpr(s64) = COPY $sgpr0_sgpr1
 500     %1:sgpr(s64) = G_FABS %0
 501     S_ENDPGM 0, implicit %1
 502 ...
 503
 504 ---
 505 name: fabs_s64_vv
 506 legalized: true
 507 regBankSelected: true
 508 tracksRegLiveness: true
 509
 510 body: |
 511   bb.0:
 512     liveins: $vgpr0_vgpr1
 513     ; GCN-LABEL: name: fabs_s64_vv
 514     ; GCN: liveins: $vgpr0_vgpr1
 515     ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 516     ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 517     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 518     ; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 [[S_MOV_B32_]], [[COPY1]], implicit $exec
 519     ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 520     ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
 521     ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 522     ; SI-LABEL: name: fabs_s64_vv
 523     ; SI: liveins: $vgpr0_vgpr1
 524     ; SI-NEXT: {{  $}}
 525     ; SI-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 526     ; SI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 527     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 528     ; SI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec
 529     ; SI-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 530     ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
 531     ; SI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 532     ; VI-LABEL: name: fabs_s64_vv
 533     ; VI: liveins: $vgpr0_vgpr1
 534     ; VI-NEXT: {{  $}}
 535     ; VI-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 536     ; VI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 537     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 538     ; VI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec
 539     ; VI-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 540     ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
 541     ; VI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 542     ; GFX9-LABEL: name: fabs_s64_vv
 543     ; GFX9: liveins: $vgpr0_vgpr1
 544     ; GFX9-NEXT: {{  $}}
 545     ; GFX9-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 546     ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 547     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 548     ; GFX9-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec
 549     ; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 550     ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
 551     ; GFX9-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 552     ; GFX10-LABEL: name: fabs_s64_vv
 553     ; GFX10: liveins: $vgpr0_vgpr1
 554     ; GFX10-NEXT: {{  $}}
 555     ; GFX10-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 556     ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 557     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 558     ; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec
 559     ; GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 560     ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
 561     ; GFX10-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 562     %0:vgpr(s64) = COPY $vgpr0_vgpr1
 563     %1:vgpr(s64) = G_FABS %0
 564     S_ENDPGM 0, implicit %1
 565 ...
 566
 567 ---
 568 name: fabs_s64_vs
 569 legalized: true
 570 regBankSelected: true
 571 tracksRegLiveness: true
 572
 573 body: |
 574   bb.0:
 575     liveins: $sgpr0_sgpr1
 576     ; GCN-LABEL: name: fabs_s64_vs
 577     ; GCN: liveins: $sgpr0_sgpr1
 578     ; GCN: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
 579     ; GCN: [[FABS:%[0-9]+]]:vgpr(s64) = G_FABS [[COPY]]
 580     ; GCN: S_ENDPGM 0, implicit [[FABS]](s64)
 581     ; SI-LABEL: name: fabs_s64_vs
 582     ; SI: liveins: $sgpr0_sgpr1
 583     ; SI-NEXT: {{  $}}
 584     ; SI-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
 585     ; SI-NEXT: [[FABS:%[0-9]+]]:vgpr(s64) = G_FABS [[COPY]]
 586     ; SI-NEXT: S_ENDPGM 0, implicit [[FABS]](s64)
 587     ; VI-LABEL: name: fabs_s64_vs
 588     ; VI: liveins: $sgpr0_sgpr1
 589     ; VI-NEXT: {{  $}}
 590     ; VI-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
 591     ; VI-NEXT: [[FABS:%[0-9]+]]:vgpr(s64) = G_FABS [[COPY]]
 592     ; VI-NEXT: S_ENDPGM 0, implicit [[FABS]](s64)
 593     ; GFX9-LABEL: name: fabs_s64_vs
 594     ; GFX9: liveins: $sgpr0_sgpr1
 595     ; GFX9-NEXT: {{  $}}
 596     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
 597     ; GFX9-NEXT: [[FABS:%[0-9]+]]:vgpr(s64) = G_FABS [[COPY]]
 598     ; GFX9-NEXT: S_ENDPGM 0, implicit [[FABS]](s64)
 599     ; GFX10-LABEL: name: fabs_s64_vs
 600     ; GFX10: liveins: $sgpr0_sgpr1
 601     ; GFX10-NEXT: {{  $}}
 602     ; GFX10-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
 603     ; GFX10-NEXT: [[FABS:%[0-9]+]]:vgpr(s64) = G_FABS [[COPY]]
 604     ; GFX10-NEXT: S_ENDPGM 0, implicit [[FABS]](s64)
 605     %0:sgpr(s64) = COPY $sgpr0_sgpr1
 606     %1:vgpr(s64) = G_FABS %0
 607     S_ENDPGM 0, implicit %1
 608 ...
 609
 610 # Make sure the source register is constrained
 611 ---
 612 name: fabs_s64_vv_no_src_constraint
 613 legalized: true
 614 regBankSelected: true
 615 tracksRegLiveness: true
 616
 617 body: |
 618   bb.0:
 619     liveins: $vgpr0_vgpr1
 620     ; GCN-LABEL: name: fabs_s64_vv_no_src_constraint
 621     ; GCN: liveins: $vgpr0_vgpr1
 622     ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
 623     ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1
 624     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 625     ; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
 626     ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0
 627     ; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
 628     ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 629     ; SI-LABEL: name: fabs_s64_vv_no_src_constraint
 630     ; SI: liveins: $vgpr0_vgpr1
 631     ; SI-NEXT: {{  $}}
 632     ; SI-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
 633     ; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1
 634     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 635     ; SI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
 636     ; SI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0
 637     ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
 638     ; SI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 639     ; VI-LABEL: name: fabs_s64_vv_no_src_constraint
 640     ; VI: liveins: $vgpr0_vgpr1
 641     ; VI-NEXT: {{  $}}
 642     ; VI-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
 643     ; VI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1
 644     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 645     ; VI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
 646     ; VI-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0
 647     ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
 648     ; VI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 649     ; GFX9-LABEL: name: fabs_s64_vv_no_src_constraint
 650     ; GFX9: liveins: $vgpr0_vgpr1
 651     ; GFX9-NEXT: {{  $}}
 652     ; GFX9-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
 653     ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1
 654     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 655     ; GFX9-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
 656     ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0
 657     ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
 658     ; GFX9-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 659     ; GFX10-LABEL: name: fabs_s64_vv_no_src_constraint
 660     ; GFX10: liveins: $vgpr0_vgpr1
 661     ; GFX10-NEXT: {{  $}}
 662     ; GFX10-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
 663     ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub1
 664     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 665     ; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
 666     ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[DEF]].sub0
 667     ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[V_AND_B32_e64_]], %subreg.sub1
 668     ; GFX10-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 669     %0:vgpr(s64) = IMPLICIT_DEF
 670     %1:vgpr(s64) = G_FABS %0:vgpr(s64)
 671     S_ENDPGM 0, implicit %1
 672 ...
 673
 674 ---
 675 name: fabs_s64_ss_no_src_constraint
 676 legalized: true
 677 regBankSelected: true
 678 tracksRegLiveness: true
 679
 680 body: |
 681   bb.0:
 682     liveins: $sgpr0_sgpr1
 683     ; GCN-LABEL: name: fabs_s64_ss_no_src_constraint
 684     ; GCN: liveins: $sgpr0_sgpr1
 685     ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
 686     ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
 687     ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
 688     ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 689     ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
 690     ; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
 691     ; GCN: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 692     ; SI-LABEL: name: fabs_s64_ss_no_src_constraint
 693     ; SI: liveins: $sgpr0_sgpr1
 694     ; SI-NEXT: {{  $}}
 695     ; SI-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
 696     ; SI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
 697     ; SI-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
 698     ; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 699     ; SI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
 700     ; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
 701     ; SI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 702     ; VI-LABEL: name: fabs_s64_ss_no_src_constraint
 703     ; VI: liveins: $sgpr0_sgpr1
 704     ; VI-NEXT: {{  $}}
 705     ; VI-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
 706     ; VI-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
 707     ; VI-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
 708     ; VI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 709     ; VI-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
 710     ; VI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
 711     ; VI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 712     ; GFX9-LABEL: name: fabs_s64_ss_no_src_constraint
 713     ; GFX9: liveins: $sgpr0_sgpr1
 714     ; GFX9-NEXT: {{  $}}
 715     ; GFX9-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
 716     ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
 717     ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
 718     ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 719     ; GFX9-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
 720     ; GFX9-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
 721     ; GFX9-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 722     ; GFX10-LABEL: name: fabs_s64_ss_no_src_constraint
 723     ; GFX10: liveins: $sgpr0_sgpr1
 724     ; GFX10-NEXT: {{  $}}
 725     ; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
 726     ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
 727     ; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
 728     ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
 729     ; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
 730     ; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[S_AND_B32_]], %subreg.sub1
 731     ; GFX10-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 732     %0:sgpr(s64) = IMPLICIT_DEF
 733     %1:sgpr(s64) = G_FABS %0:sgpr(s64)
 734     S_ENDPGM 0, implicit %1
 735 ...