llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-add.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX6 %s
   3 # RUN: llc -march=amdgcn -mcpu=fiji  -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX8 %s
   4 # RUN: llc -march=amdgcn -mcpu=gfx900  -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
   5 # RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64  -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX10-WAVE64 %s
   6 # RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64  -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX10-WAVE32 %s
   7
   8 ---
   9 name:  gep_p0_sgpr_sgpr
  10 legalized:       true
  11 regBankSelected: true
  12
  13 body: |
  14   bb.0:
  15     liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
  16     ; GFX6-LABEL: name: gep_p0_sgpr_sgpr
  17     ; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
  18     ; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
  19     ; GFX6: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
  20     ; GFX6: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub0
  21     ; GFX6: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
  22     ; GFX6: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub1
  23     ; GFX6: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY2]], [[COPY3]], implicit-def $scc
  24     ; GFX6: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY4]], [[COPY5]], implicit-def $scc, implicit $scc
  25     ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
  26     ; GFX6: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
  27     ; GFX8-LABEL: name: gep_p0_sgpr_sgpr
  28     ; GFX8: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
  29     ; GFX8: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
  30     ; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
  31     ; GFX8: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub0
  32     ; GFX8: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
  33     ; GFX8: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub1
  34     ; GFX8: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY2]], [[COPY3]], implicit-def $scc
  35     ; GFX8: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY4]], [[COPY5]], implicit-def $scc, implicit $scc
  36     ; GFX8: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
  37     ; GFX8: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
  38     ; GFX9-LABEL: name: gep_p0_sgpr_sgpr
  39     ; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
  40     ; GFX9: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
  41     ; GFX9: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
  42     ; GFX9: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub0
  43     ; GFX9: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
  44     ; GFX9: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub1
  45     ; GFX9: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY2]], [[COPY3]], implicit-def $scc
  46     ; GFX9: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY4]], [[COPY5]], implicit-def $scc, implicit $scc
  47     ; GFX9: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
  48     ; GFX9: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
  49     ; GFX10-WAVE64-LABEL: name: gep_p0_sgpr_sgpr
  50     ; GFX10-WAVE64: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
  51     ; GFX10-WAVE64: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
  52     ; GFX10-WAVE64: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
  53     ; GFX10-WAVE64: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub0
  54     ; GFX10-WAVE64: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
  55     ; GFX10-WAVE64: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub1
  56     ; GFX10-WAVE64: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY2]], [[COPY3]], implicit-def $scc
  57     ; GFX10-WAVE64: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY4]], [[COPY5]], implicit-def $scc, implicit $scc
  58     ; GFX10-WAVE64: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
  59     ; GFX10-WAVE64: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
  60     ; GFX10-WAVE32-LABEL: name: gep_p0_sgpr_sgpr
  61     ; GFX10-WAVE32: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
  62     ; GFX10-WAVE32: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
  63     ; GFX10-WAVE32: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
  64     ; GFX10-WAVE32: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub0
  65     ; GFX10-WAVE32: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
  66     ; GFX10-WAVE32: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub1
  67     ; GFX10-WAVE32: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY2]], [[COPY3]], implicit-def $scc
  68     ; GFX10-WAVE32: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY4]], [[COPY5]], implicit-def $scc, implicit $scc
  69     ; GFX10-WAVE32: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
  70     ; GFX10-WAVE32: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
  71     %0:sgpr(p0) = COPY $sgpr0_sgpr1
  72     %1:sgpr(s64) = COPY $sgpr2_sgpr3
  73     %2:sgpr(p0) = G_PTR_ADD %0, %1
  74     S_ENDPGM 0, implicit %2
  75
  76 ...
  77
  78 ---
  79 name:  gep_p0_vgpr_vgpr
  80 legalized:       true
  81 regBankSelected: true
  82
  83 body: |
  84   bb.0:
  85     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
  86     ; GFX6-LABEL: name: gep_p0_vgpr_vgpr
  87     ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
  88     ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
  89     ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
  90     ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0
  91     ; GFX6: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
  92     ; GFX6: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1
  93     ; GFX6: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY2]], [[COPY3]], 0, implicit $exec
  94     ; GFX6: %8:vgpr_32, dead %10:sreg_64_xexec = V_ADDC_U32_e64 [[COPY4]], [[COPY5]], killed [[V_ADD_CO_U32_e64_1]], 0, implicit $exec
  95     ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, %8, %subreg.sub1
  96     ; GFX6: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
  97     ; GFX8-LABEL: name: gep_p0_vgpr_vgpr
  98     ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
  99     ; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
 100     ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 101     ; GFX8: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0
 102     ; GFX8: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 103     ; GFX8: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1
 104     ; GFX8: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY2]], [[COPY3]], 0, implicit $exec
 105     ; GFX8: %8:vgpr_32, dead %10:sreg_64_xexec = V_ADDC_U32_e64 [[COPY4]], [[COPY5]], killed [[V_ADD_CO_U32_e64_1]], 0, implicit $exec
 106     ; GFX8: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, %8, %subreg.sub1
 107     ; GFX8: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 108     ; GFX9-LABEL: name: gep_p0_vgpr_vgpr
 109     ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 110     ; GFX9: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
 111     ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 112     ; GFX9: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0
 113     ; GFX9: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 114     ; GFX9: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1
 115     ; GFX9: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY2]], [[COPY3]], 0, implicit $exec
 116     ; GFX9: %8:vgpr_32, dead %10:sreg_64_xexec = V_ADDC_U32_e64 [[COPY4]], [[COPY5]], killed [[V_ADD_CO_U32_e64_1]], 0, implicit $exec
 117     ; GFX9: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, %8, %subreg.sub1
 118     ; GFX9: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 119     ; GFX10-WAVE64-LABEL: name: gep_p0_vgpr_vgpr
 120     ; GFX10-WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 121     ; GFX10-WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
 122     ; GFX10-WAVE64: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 123     ; GFX10-WAVE64: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0
 124     ; GFX10-WAVE64: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 125     ; GFX10-WAVE64: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1
 126     ; GFX10-WAVE64: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY2]], [[COPY3]], 0, implicit $exec
 127     ; GFX10-WAVE64: %8:vgpr_32, dead %10:sreg_64_xexec = V_ADDC_U32_e64 [[COPY4]], [[COPY5]], killed [[V_ADD_CO_U32_e64_1]], 0, implicit $exec
 128     ; GFX10-WAVE64: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, %8, %subreg.sub1
 129     ; GFX10-WAVE64: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 130     ; GFX10-WAVE32-LABEL: name: gep_p0_vgpr_vgpr
 131     ; GFX10-WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 132     ; GFX10-WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
 133     ; GFX10-WAVE32: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 134     ; GFX10-WAVE32: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0
 135     ; GFX10-WAVE32: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 136     ; GFX10-WAVE32: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1
 137     ; GFX10-WAVE32: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 [[COPY2]], [[COPY3]], 0, implicit $exec
 138     ; GFX10-WAVE32: %8:vgpr_32, dead %10:sreg_32_xm0_xexec = V_ADDC_U32_e64 [[COPY4]], [[COPY5]], killed [[V_ADD_CO_U32_e64_1]], 0, implicit $exec
 139     ; GFX10-WAVE32: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, %8, %subreg.sub1
 140     ; GFX10-WAVE32: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 141     %0:vgpr(p0) = COPY $vgpr0_vgpr1
 142     %1:vgpr(s64) = COPY $vgpr2_vgpr3
 143     %2:vgpr(p0) = G_PTR_ADD %0, %1
 144     S_ENDPGM 0, implicit %2
 145
 146 ...
 147
 148 ---
 149 name:  gep_p0_sgpr_vgpr
 150 legalized:       true
 151 regBankSelected: true
 152
 153 body: |
 154   bb.0:
 155     liveins: $sgpr0_sgpr1, $vgpr0_vgpr1
 156     ; GFX6-LABEL: name: gep_p0_sgpr_vgpr
 157     ; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 158     ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 159     ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 160     ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0
 161     ; GFX6: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 162     ; GFX6: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1
 163     ; GFX6: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY2]], [[COPY3]], 0, implicit $exec
 164     ; GFX6: %8:vgpr_32, dead %10:sreg_64_xexec = V_ADDC_U32_e64 [[COPY4]], [[COPY5]], killed [[V_ADD_CO_U32_e64_1]], 0, implicit $exec
 165     ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, %8, %subreg.sub1
 166     ; GFX6: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 167     ; GFX8-LABEL: name: gep_p0_sgpr_vgpr
 168     ; GFX8: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 169     ; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 170     ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 171     ; GFX8: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0
 172     ; GFX8: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 173     ; GFX8: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1
 174     ; GFX8: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY2]], [[COPY3]], 0, implicit $exec
 175     ; GFX8: %8:vgpr_32, dead %10:sreg_64_xexec = V_ADDC_U32_e64 [[COPY4]], [[COPY5]], killed [[V_ADD_CO_U32_e64_1]], 0, implicit $exec
 176     ; GFX8: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, %8, %subreg.sub1
 177     ; GFX8: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 178     ; GFX9-LABEL: name: gep_p0_sgpr_vgpr
 179     ; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 180     ; GFX9: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 181     ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 182     ; GFX9: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0
 183     ; GFX9: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 184     ; GFX9: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1
 185     ; GFX9: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY2]], [[COPY3]], 0, implicit $exec
 186     ; GFX9: %8:vgpr_32, dead %10:sreg_64_xexec = V_ADDC_U32_e64 [[COPY4]], [[COPY5]], killed [[V_ADD_CO_U32_e64_1]], 0, implicit $exec
 187     ; GFX9: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, %8, %subreg.sub1
 188     ; GFX9: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 189     ; GFX10-WAVE64-LABEL: name: gep_p0_sgpr_vgpr
 190     ; GFX10-WAVE64: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 191     ; GFX10-WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 192     ; GFX10-WAVE64: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 193     ; GFX10-WAVE64: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0
 194     ; GFX10-WAVE64: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 195     ; GFX10-WAVE64: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1
 196     ; GFX10-WAVE64: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY2]], [[COPY3]], 0, implicit $exec
 197     ; GFX10-WAVE64: %8:vgpr_32, dead %10:sreg_64_xexec = V_ADDC_U32_e64 [[COPY4]], [[COPY5]], killed [[V_ADD_CO_U32_e64_1]], 0, implicit $exec
 198     ; GFX10-WAVE64: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, %8, %subreg.sub1
 199     ; GFX10-WAVE64: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 200     ; GFX10-WAVE32-LABEL: name: gep_p0_sgpr_vgpr
 201     ; GFX10-WAVE32: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 202     ; GFX10-WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 203     ; GFX10-WAVE32: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 204     ; GFX10-WAVE32: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0
 205     ; GFX10-WAVE32: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 206     ; GFX10-WAVE32: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1
 207     ; GFX10-WAVE32: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 [[COPY2]], [[COPY3]], 0, implicit $exec
 208     ; GFX10-WAVE32: %8:vgpr_32, dead %10:sreg_32_xm0_xexec = V_ADDC_U32_e64 [[COPY4]], [[COPY5]], killed [[V_ADD_CO_U32_e64_1]], 0, implicit $exec
 209     ; GFX10-WAVE32: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, %8, %subreg.sub1
 210     ; GFX10-WAVE32: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 211     %0:sgpr(p0) = COPY $sgpr0_sgpr1
 212     %1:vgpr(s64) = COPY $vgpr0_vgpr1
 213     %2:vgpr(p0) = G_PTR_ADD %0, %1
 214     S_ENDPGM 0, implicit %2
 215
 216 ...
 217
 218 ---
 219 name:  gep_p3_sgpr_sgpr
 220 legalized:       true
 221 regBankSelected: true
 222
 223 body: |
 224   bb.0:
 225     liveins: $sgpr0, $sgpr1
 226     ; GFX6-LABEL: name: gep_p3_sgpr_sgpr
 227     ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 228     ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
 229     ; GFX6: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
 230     ; GFX6: S_ENDPGM 0, implicit [[S_ADD_U32_]]
 231     ; GFX8-LABEL: name: gep_p3_sgpr_sgpr
 232     ; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 233     ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
 234     ; GFX8: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
 235     ; GFX8: S_ENDPGM 0, implicit [[S_ADD_U32_]]
 236     ; GFX9-LABEL: name: gep_p3_sgpr_sgpr
 237     ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 238     ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
 239     ; GFX9: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
 240     ; GFX9: S_ENDPGM 0, implicit [[S_ADD_U32_]]
 241     ; GFX10-WAVE64-LABEL: name: gep_p3_sgpr_sgpr
 242     ; GFX10-WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 243     ; GFX10-WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
 244     ; GFX10-WAVE64: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
 245     ; GFX10-WAVE64: S_ENDPGM 0, implicit [[S_ADD_U32_]]
 246     ; GFX10-WAVE32-LABEL: name: gep_p3_sgpr_sgpr
 247     ; GFX10-WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 248     ; GFX10-WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
 249     ; GFX10-WAVE32: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
 250     ; GFX10-WAVE32: S_ENDPGM 0, implicit [[S_ADD_U32_]]
 251     %0:sgpr(p3) = COPY $sgpr0
 252     %1:sgpr(s32) = COPY $sgpr1
 253     %2:sgpr(p3) = G_PTR_ADD %0, %1
 254     S_ENDPGM 0, implicit %2
 255
 256 ...
 257
 258 ---
 259 name:  gep_p3_vgpr_vgpr
 260 legalized:       true
 261 regBankSelected: true
 262
 263 body: |
 264   bb.0:
 265     liveins: $vgpr0, $vgpr1
 266     ; GFX6-LABEL: name: gep_p3_vgpr_vgpr
 267     ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 268     ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
 269     ; GFX6: %2:vgpr_32, dead %3:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
 270     ; GFX6: S_ENDPGM 0, implicit %2
 271     ; GFX8-LABEL: name: gep_p3_vgpr_vgpr
 272     ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 273     ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
 274     ; GFX8: %2:vgpr_32, dead %3:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
 275     ; GFX8: S_ENDPGM 0, implicit %2
 276     ; GFX9-LABEL: name: gep_p3_vgpr_vgpr
 277     ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 278     ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
 279     ; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
 280     ; GFX9: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]]
 281     ; GFX10-WAVE64-LABEL: name: gep_p3_vgpr_vgpr
 282     ; GFX10-WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 283     ; GFX10-WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
 284     ; GFX10-WAVE64: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
 285     ; GFX10-WAVE64: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]]
 286     ; GFX10-WAVE32-LABEL: name: gep_p3_vgpr_vgpr
 287     ; GFX10-WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 288     ; GFX10-WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
 289     ; GFX10-WAVE32: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
 290     ; GFX10-WAVE32: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]]
 291     %0:vgpr(p3) = COPY $vgpr0
 292     %1:vgpr(s32) = COPY $vgpr1
 293     %2:vgpr(p3) = G_PTR_ADD %0, %1
 294     S_ENDPGM 0, implicit %2
 295
 296 ...
 297
 298 ---
 299 name:  gep_p3_sgpr_vgpr
 300 legalized:       true
 301 regBankSelected: true
 302
 303 body: |
 304   bb.0:
 305     liveins: $sgpr0, $vgpr0
 306     ; GFX6-LABEL: name: gep_p3_sgpr_vgpr
 307     ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 308     ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 309     ; GFX6: %2:vgpr_32, dead %3:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
 310     ; GFX6: S_ENDPGM 0, implicit %2
 311     ; GFX8-LABEL: name: gep_p3_sgpr_vgpr
 312     ; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 313     ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 314     ; GFX8: %2:vgpr_32, dead %3:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
 315     ; GFX8: S_ENDPGM 0, implicit %2
 316     ; GFX9-LABEL: name: gep_p3_sgpr_vgpr
 317     ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 318     ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 319     ; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
 320     ; GFX9: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]]
 321     ; GFX10-WAVE64-LABEL: name: gep_p3_sgpr_vgpr
 322     ; GFX10-WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 323     ; GFX10-WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 324     ; GFX10-WAVE64: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
 325     ; GFX10-WAVE64: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]]
 326     ; GFX10-WAVE32-LABEL: name: gep_p3_sgpr_vgpr
 327     ; GFX10-WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 328     ; GFX10-WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 329     ; GFX10-WAVE32: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
 330     ; GFX10-WAVE32: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]]
 331     %0:sgpr(p3) = COPY $sgpr0
 332     %1:vgpr(s32) = COPY $vgpr0
 333     %2:vgpr(p3) = G_PTR_ADD %0, %1
 334     S_ENDPGM 0, implicit %2
 335
 336 ...
 337
 338 ---
 339 name:  gep_p6_sgpr_sgpr
 340 legalized:       true
 341 regBankSelected: true
 342
 343 body: |
 344   bb.0:
 345     liveins: $sgpr0, $sgpr1
 346     ; GFX6-LABEL: name: gep_p6_sgpr_sgpr
 347     ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 348     ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
 349     ; GFX6: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
 350     ; GFX6: S_ENDPGM 0, implicit [[S_ADD_U32_]]
 351     ; GFX8-LABEL: name: gep_p6_sgpr_sgpr
 352     ; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 353     ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
 354     ; GFX8: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
 355     ; GFX8: S_ENDPGM 0, implicit [[S_ADD_U32_]]
 356     ; GFX9-LABEL: name: gep_p6_sgpr_sgpr
 357     ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 358     ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
 359     ; GFX9: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
 360     ; GFX9: S_ENDPGM 0, implicit [[S_ADD_U32_]]
 361     ; GFX10-WAVE64-LABEL: name: gep_p6_sgpr_sgpr
 362     ; GFX10-WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 363     ; GFX10-WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
 364     ; GFX10-WAVE64: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
 365     ; GFX10-WAVE64: S_ENDPGM 0, implicit [[S_ADD_U32_]]
 366     ; GFX10-WAVE32-LABEL: name: gep_p6_sgpr_sgpr
 367     ; GFX10-WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 368     ; GFX10-WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
 369     ; GFX10-WAVE32: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
 370     ; GFX10-WAVE32: S_ENDPGM 0, implicit [[S_ADD_U32_]]
 371     %0:sgpr(p6) = COPY $sgpr0
 372     %1:sgpr(s32) = COPY $sgpr1
 373     %2:sgpr(p6) = G_PTR_ADD %0, %1
 374     S_ENDPGM 0, implicit %2
 375
 376 ...
 377
 378 ---
 379 name:  gep_p2_sgpr_sgpr
 380 legalized:       true
 381 regBankSelected: true
 382
 383 body: |
 384   bb.0:
 385     liveins: $sgpr0, $sgpr1
 386     ; GFX6-LABEL: name: gep_p2_sgpr_sgpr
 387     ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 388     ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
 389     ; GFX6: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
 390     ; GFX6: S_ENDPGM 0, implicit [[S_ADD_U32_]]
 391     ; GFX8-LABEL: name: gep_p2_sgpr_sgpr
 392     ; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 393     ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
 394     ; GFX8: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
 395     ; GFX8: S_ENDPGM 0, implicit [[S_ADD_U32_]]
 396     ; GFX9-LABEL: name: gep_p2_sgpr_sgpr
 397     ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 398     ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
 399     ; GFX9: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
 400     ; GFX9: S_ENDPGM 0, implicit [[S_ADD_U32_]]
 401     ; GFX10-WAVE64-LABEL: name: gep_p2_sgpr_sgpr
 402     ; GFX10-WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 403     ; GFX10-WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
 404     ; GFX10-WAVE64: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
 405     ; GFX10-WAVE64: S_ENDPGM 0, implicit [[S_ADD_U32_]]
 406     ; GFX10-WAVE32-LABEL: name: gep_p2_sgpr_sgpr
 407     ; GFX10-WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 408     ; GFX10-WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
 409     ; GFX10-WAVE32: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
 410     ; GFX10-WAVE32: S_ENDPGM 0, implicit [[S_ADD_U32_]]
 411     %0:sgpr(p2) = COPY $sgpr0
 412     %1:sgpr(s32) = COPY $sgpr1
 413     %2:sgpr(p2) = G_PTR_ADD %0, %1
 414     S_ENDPGM 0, implicit %2
 415
 416 ...
 417
 418 ---
 419 name:  gep_p999_sgpr_sgpr
 420 legalized:       true
 421 regBankSelected: true
 422
 423 body: |
 424   bb.0:
 425     liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
 426     ; GFX6-LABEL: name: gep_p999_sgpr_sgpr
 427     ; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 428     ; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
 429     ; GFX6: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
 430     ; GFX6: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub0
 431     ; GFX6: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
 432     ; GFX6: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub1
 433     ; GFX6: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY2]], [[COPY3]], implicit-def $scc
 434     ; GFX6: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY4]], [[COPY5]], implicit-def $scc, implicit $scc
 435     ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
 436     ; GFX6: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 437     ; GFX8-LABEL: name: gep_p999_sgpr_sgpr
 438     ; GFX8: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 439     ; GFX8: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
 440     ; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
 441     ; GFX8: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub0
 442     ; GFX8: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
 443     ; GFX8: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub1
 444     ; GFX8: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY2]], [[COPY3]], implicit-def $scc
 445     ; GFX8: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY4]], [[COPY5]], implicit-def $scc, implicit $scc
 446     ; GFX8: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
 447     ; GFX8: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 448     ; GFX9-LABEL: name: gep_p999_sgpr_sgpr
 449     ; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 450     ; GFX9: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
 451     ; GFX9: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
 452     ; GFX9: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub0
 453     ; GFX9: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
 454     ; GFX9: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub1
 455     ; GFX9: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY2]], [[COPY3]], implicit-def $scc
 456     ; GFX9: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY4]], [[COPY5]], implicit-def $scc, implicit $scc
 457     ; GFX9: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
 458     ; GFX9: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 459     ; GFX10-WAVE64-LABEL: name: gep_p999_sgpr_sgpr
 460     ; GFX10-WAVE64: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 461     ; GFX10-WAVE64: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
 462     ; GFX10-WAVE64: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
 463     ; GFX10-WAVE64: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub0
 464     ; GFX10-WAVE64: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
 465     ; GFX10-WAVE64: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub1
 466     ; GFX10-WAVE64: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY2]], [[COPY3]], implicit-def $scc
 467     ; GFX10-WAVE64: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY4]], [[COPY5]], implicit-def $scc, implicit $scc
 468     ; GFX10-WAVE64: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
 469     ; GFX10-WAVE64: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 470     ; GFX10-WAVE32-LABEL: name: gep_p999_sgpr_sgpr
 471     ; GFX10-WAVE32: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 472     ; GFX10-WAVE32: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
 473     ; GFX10-WAVE32: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
 474     ; GFX10-WAVE32: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub0
 475     ; GFX10-WAVE32: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
 476     ; GFX10-WAVE32: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub1
 477     ; GFX10-WAVE32: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY2]], [[COPY3]], implicit-def $scc
 478     ; GFX10-WAVE32: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY4]], [[COPY5]], implicit-def $scc, implicit $scc
 479     ; GFX10-WAVE32: [[REG_SEQUENCE:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
 480     ; GFX10-WAVE32: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 481     %0:sgpr(p999) = COPY $sgpr0_sgpr1
 482     %1:sgpr(s64) = COPY $sgpr2_sgpr3
 483     %2:sgpr(p999) = G_PTR_ADD %0, %1
 484     S_ENDPGM 0, implicit %2
 485
 486 ...
 487
 488 ---
 489 name:  gep_p999_vgpr_vgpr
 490 legalized:       true
 491 regBankSelected: true
 492
 493 body: |
 494   bb.0:
 495     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 496     ; GFX6-LABEL: name: gep_p999_vgpr_vgpr
 497     ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 498     ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
 499     ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 500     ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0
 501     ; GFX6: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 502     ; GFX6: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1
 503     ; GFX6: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY2]], [[COPY3]], 0, implicit $exec
 504     ; GFX6: %8:vgpr_32, dead %10:sreg_64_xexec = V_ADDC_U32_e64 [[COPY4]], [[COPY5]], killed [[V_ADD_CO_U32_e64_1]], 0, implicit $exec
 505     ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, %8, %subreg.sub1
 506     ; GFX6: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 507     ; GFX8-LABEL: name: gep_p999_vgpr_vgpr
 508     ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 509     ; GFX8: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
 510     ; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 511     ; GFX8: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0
 512     ; GFX8: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 513     ; GFX8: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1
 514     ; GFX8: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY2]], [[COPY3]], 0, implicit $exec
 515     ; GFX8: %8:vgpr_32, dead %10:sreg_64_xexec = V_ADDC_U32_e64 [[COPY4]], [[COPY5]], killed [[V_ADD_CO_U32_e64_1]], 0, implicit $exec
 516     ; GFX8: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, %8, %subreg.sub1
 517     ; GFX8: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 518     ; GFX9-LABEL: name: gep_p999_vgpr_vgpr
 519     ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 520     ; GFX9: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
 521     ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 522     ; GFX9: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0
 523     ; GFX9: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 524     ; GFX9: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1
 525     ; GFX9: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY2]], [[COPY3]], 0, implicit $exec
 526     ; GFX9: %8:vgpr_32, dead %10:sreg_64_xexec = V_ADDC_U32_e64 [[COPY4]], [[COPY5]], killed [[V_ADD_CO_U32_e64_1]], 0, implicit $exec
 527     ; GFX9: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, %8, %subreg.sub1
 528     ; GFX9: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 529     ; GFX10-WAVE64-LABEL: name: gep_p999_vgpr_vgpr
 530     ; GFX10-WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 531     ; GFX10-WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
 532     ; GFX10-WAVE64: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 533     ; GFX10-WAVE64: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0
 534     ; GFX10-WAVE64: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 535     ; GFX10-WAVE64: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1
 536     ; GFX10-WAVE64: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY2]], [[COPY3]], 0, implicit $exec
 537     ; GFX10-WAVE64: %8:vgpr_32, dead %10:sreg_64_xexec = V_ADDC_U32_e64 [[COPY4]], [[COPY5]], killed [[V_ADD_CO_U32_e64_1]], 0, implicit $exec
 538     ; GFX10-WAVE64: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, %8, %subreg.sub1
 539     ; GFX10-WAVE64: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 540     ; GFX10-WAVE32-LABEL: name: gep_p999_vgpr_vgpr
 541     ; GFX10-WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
 542     ; GFX10-WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
 543     ; GFX10-WAVE32: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
 544     ; GFX10-WAVE32: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0
 545     ; GFX10-WAVE32: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
 546     ; GFX10-WAVE32: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1
 547     ; GFX10-WAVE32: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 [[COPY2]], [[COPY3]], 0, implicit $exec
 548     ; GFX10-WAVE32: %8:vgpr_32, dead %10:sreg_32_xm0_xexec = V_ADDC_U32_e64 [[COPY4]], [[COPY5]], killed [[V_ADD_CO_U32_e64_1]], 0, implicit $exec
 549     ; GFX10-WAVE32: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, %8, %subreg.sub1
 550     ; GFX10-WAVE32: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
 551     %0:vgpr(p999) = COPY $vgpr0_vgpr1
 552     %1:vgpr(s64) = COPY $vgpr2_vgpr3
 553     %2:vgpr(p999) = G_PTR_ADD %0, %1
 554     S_ENDPGM 0, implicit %2
 555
 556 ...